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WO1996030833A1 - Dispositifs electroniques de stockage de donnees et leurs procedes de fabrication et d'essai - Google Patents

Dispositifs electroniques de stockage de donnees et leurs procedes de fabrication et d'essai Download PDF

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Publication number
WO1996030833A1
WO1996030833A1 PCT/GB1996/000149 GB9600149W WO9630833A1 WO 1996030833 A1 WO1996030833 A1 WO 1996030833A1 GB 9600149 W GB9600149 W GB 9600149W WO 9630833 A1 WO9630833 A1 WO 9630833A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuits
data storage
electronic data
memory
memory system
Prior art date
Application number
PCT/GB1996/000149
Other languages
English (en)
Inventor
Alexander Roger Deas
Original Assignee
Memory Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memory Corporation filed Critical Memory Corporation
Publication of WO1996030833A1 publication Critical patent/WO1996030833A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Definitions

  • This invention relates to electronic data storage devices and, in particular, to a method for providing sub-word write capability in partial memory systems with means for retaining the integrity of the memory architecture between manufacturing stages. It finds application in memory systems where memory circuits are arranged in a matrix
  • the partials have a value
  • word size which is the number of bits that can be read
  • a group of eight 4-bit wide memory dice may be configured as
  • substitute store is normally 4 or more bits
  • Figure 1 shows a 4-bit wide substitute store used in a 32-bit wide SIMM module
  • Figure 2 shows a method for storing the sorted devices to ensure that set integrity is
  • memory control device would rectify these rows by routing these four data bits to the
  • devices #1 through to #8 can work perfectly, but if it is desired to write to only the first byte
  • the partial memory controller will have
  • an electronic data storage device comprising a plurality of
  • addressing means adapted to select sets of said electronic data storage means for
  • addressing means in which the addressing means is adapted to divert data addressed to said
  • embodiment of the invention may be separated into a number of stages.
  • first stage In the first stage,
  • the partials are then sorted, in a second stage, into sets
  • number of subsets is equal to the full word width divided by the width of the smallest
  • Number of sets for one module ((Full word width)/( width of smallest writeable subword) + 1).
  • the sets are initially empty, but either as each device is tested, or as each device is
  • sets for a plurality of memory modules will be sorted simultaneously
  • the sorting is carried out on an automatic device handler attached to
  • test system but may be carried out by manual operators prompted by a suitable
  • the sorted chips are placed into a physical
  • the nine chips may be placed in order in a tube.
  • assembly machine would be programmed to place all nine chips from that tube onto the
  • a manufacturer may place more than one set in a tube, so long as each set is handled correctly by the automatic equipment.
  • a similar assembly system can be instated using memory chips held in trays.
  • one or more memory chips are marked so they can be identified in the assembly
  • the last partial in the set is marked, or a predetermined
  • elements are addressed in the form of a matrix of rows and columns. In particular, it may
  • optical memory systems such as holographic memories.

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

Un procédé destiné à conférer une capacité d'écriture de sous-mots, dans des systèmes de mémoires partielles dotés de moyens permettant de conserver l'intégrité de l'architecture de la mémoire entre les étapes de fabrication, consiste à procéder à l'essai des circuits intégrés afin de localiser les défaillances au niveau de rangées ou de colonnes, à déterminer ceux desdits circuits intégrés présentant des défaillances au niveau de rangées ou de colonnes, et à agencer un nombre approprié de circuits intégrés ne présentant pas de défaillances de rangées ou de colonnes coïncidantes en un groupe, pour former un ensemble utilisable dans un système de mémoires.
PCT/GB1996/000149 1995-03-28 1996-01-24 Dispositifs electroniques de stockage de donnees et leurs procedes de fabrication et d'essai WO1996030833A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9506262A GB2291516A (en) 1995-03-28 1995-03-28 Provision of write capability in partial memory systems
GB9506262.6 1995-03-28

Publications (1)

Publication Number Publication Date
WO1996030833A1 true WO1996030833A1 (fr) 1996-10-03

Family

ID=10771992

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1996/000149 WO1996030833A1 (fr) 1995-03-28 1996-01-24 Dispositifs electroniques de stockage de donnees et leurs procedes de fabrication et d'essai

Country Status (2)

Country Link
GB (1) GB2291516A (fr)
WO (1) WO1996030833A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3897626A (en) * 1971-06-25 1975-08-05 Ibm Method of manufacturing a full capacity monolithic memory utilizing defective storage cells
US4376300A (en) * 1981-01-02 1983-03-08 Intel Corporation Memory system employing mostly good memories
EP0395612A2 (fr) * 1989-04-28 1990-10-31 International Business Machines Corporation Unité de mémoire et son procédé de fabrication
WO1991001023A1 (fr) * 1989-07-06 1991-01-24 Mv Limited Systeme de stockage de donnees insensible aux defaillances
WO1992008193A1 (fr) * 1990-11-02 1992-05-14 Mv Limited Systeme de memorisation de donnees insensible aux defaillances
WO1992020068A1 (fr) * 1991-05-07 1992-11-12 Sophos Technologic Systeme de memoire rapide utilisant des memoires pour la plupart bonnes

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3644899A (en) * 1970-07-29 1972-02-22 Cogar Corp Method for determining partial memory chip categories
US3805243A (en) * 1971-02-22 1974-04-16 Cogar Corp Apparatus and method for determining partial memory chip categories
US3735368A (en) * 1971-06-25 1973-05-22 Ibm Full capacity monolithic memory utilizing defective storage cells

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3897626A (en) * 1971-06-25 1975-08-05 Ibm Method of manufacturing a full capacity monolithic memory utilizing defective storage cells
US4376300A (en) * 1981-01-02 1983-03-08 Intel Corporation Memory system employing mostly good memories
EP0395612A2 (fr) * 1989-04-28 1990-10-31 International Business Machines Corporation Unité de mémoire et son procédé de fabrication
WO1991001023A1 (fr) * 1989-07-06 1991-01-24 Mv Limited Systeme de stockage de donnees insensible aux defaillances
WO1992008193A1 (fr) * 1990-11-02 1992-05-14 Mv Limited Systeme de memorisation de donnees insensible aux defaillances
WO1992020068A1 (fr) * 1991-05-07 1992-11-12 Sophos Technologic Systeme de memoire rapide utilisant des memoires pour la plupart bonnes

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Multi-Chip Planar Memory Package", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 26, no. 7b, December 1983 (1983-12-01), US, pages 3632 - 3635, XP002003813 *
"Use of Partially Good Memory Chips", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 9, February 1979 (1979-02-01), US, pages 3582 - 3583, XP002003812 *

Also Published As

Publication number Publication date
GB2291516A (en) 1996-01-24
GB9506262D0 (en) 1995-05-17

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