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WO1996036925A1 - Processeur central de surveillance pour dispositif logique - Google Patents

Processeur central de surveillance pour dispositif logique Download PDF

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Publication number
WO1996036925A1
WO1996036925A1 PCT/US1996/007017 US9607017W WO9636925A1 WO 1996036925 A1 WO1996036925 A1 WO 1996036925A1 US 9607017 W US9607017 W US 9607017W WO 9636925 A1 WO9636925 A1 WO 9636925A1
Authority
WO
WIPO (PCT)
Prior art keywords
monitor
monitor cpu
semiconductor device
cpu
fpga
Prior art date
Application number
PCT/US1996/007017
Other languages
English (en)
Inventor
Brad Taylor
Original Assignee
Giga Operations Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giga Operations Corporation filed Critical Giga Operations Corporation
Priority to AU58606/96A priority Critical patent/AU5860696A/en
Publication of WO1996036925A1 publication Critical patent/WO1996036925A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/006—Identification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324—Display of status information
    • G06F11/325—Display of status information by lamps or LED's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Definitions

  • This invention relates to a monitor CPU to be used in conjunction with one or more FPGAs.
  • this invention relates to using a small, general purpose CPU to monitor environmental conditions which may affect an FPGA and to modify the system environment when needed to protect the FPGA.
  • a wide variety of semiconductor logic devices are in use today in an overwhelming variety of applications. Each device, however, is designed to operate under certain environmental conditions and if those conditions are not present, operating the device can lead to inaccurate output or perhaps damage to the device. This is particularly true for programmable logic devices, which can be configured in a wide range of electrical characteristics.
  • FPGA field programmable gate array
  • FPGAs have been used in a wide variety of applications. See, for example, United States Patent Nos. 5,077,451 (Mohsen, assigned to Aptix Corporation), 5,036,473 (Butts, et al., assigned to Mentor Graphics Corporation) and 5,109,353 (Sample, et al., assigned to Quickturn Systems, Incorporated).
  • FPGAs provide a designer with a wide variety of interesting functionality and features. However, it is possible to configure an FPGA with certain logic combinations which under certain conditions may drive the FPGA beyond its physical limits and can damage, even destroy, the FPGA. For example, it is possible to program many, if not all, input and output pins in a typical FPGA. If, for example, 64 I/O pins are set low but then shorted to + 5V, this can cause a 3-amp current flow into the FPGA. Dissipating 15 watts of power causes the FPGA package temperature to rise and, if left unchecked, can heat the part above 150° C which can destroy the part.
  • the present invention provides a monitor CPU with inputs for sensors to measure selected environmental conditions and a connection to a semiconductor device that can temporarily disable the device in case an unacceptable environmental condition is detected. This is particularly useful where the semiconductor device is a field programmable gate array (FPGA).
  • the present invention also provides for a monitor CPU which can be loaded with a unique identification number to allow communication over a bus and, in turn, use that as a means for a host to selectively access a connected semiconductor device.
  • the present invention further provides for connection of the monitor CPU to DRAM which ordinarily also is connected to and controlled by a semiconductor device, such as an FPGA. During certain periods when the device (FPGA) is unavailable, the monitor CPU can initiate a DRAM refresh cycle as needed.
  • the present invention further provides for the monitor CPU to be connected directly to the program pin(s) of an FPGA for controlling the configuration state of the FPGA.
  • One object of the present invention is to provide an interface with a unique ID for a semiconductor device, in particular a programmable device. This interface can isolate the semiconductor device from a host system and provide controlled access to specific functions of the semiconductor device. For example, the interface can isolate a programmabie logic device from the host system and provide controlled access to programming functions of the programmable logic device.
  • Yet another object of the present invention is to provide a backup refresh monitor for DRAM normally controlled by a semiconductor device so as to maintain the DRAM even if the semiconductor device is temporarily unable to refresh the DRAM.
  • Figure 1 illustrates a monitor CPU in a system including an FPGA, DRAM, and host system I/O.
  • Figures 2A and 2B illustrate a circuit for current monitoring.
  • Figure 3 illustrates a circuit for a voltage monitor.
  • Figure 4 illustrates a circuit for a temperature monitor.
  • Figures 5A and 5B illustrate connections to a first and to a second monitor CPU.
  • Figure 6 illustrates a three-color, RGB light-emitting diode.
  • the monitor CPU of this invention provides several useful benefits for connecting a system to an FPGA. These include providing a ready means to identify a specific FPGA for programming purposes, a means to control and facilitate programming the FPGA, and a means to monitor the environment and protect the FPGA.
  • Vcc source 10 provides + 5V input along rail 11.
  • a representative sensor 13 is connected across resistor 12.
  • Sensor lines 15, 16 and 17 connect sensor 13 to monitor CPU 20.
  • Power lead 14 connects rail 11 to the power input of monitor CPU 20.
  • Monitor CPU 20 is also connected to a host system (not shown) through receive line (RX) 21, transmit line (TX) 22.
  • Monitor CPU 20 receives a reset signal (e.g., PIC_RESET, see Figure 5A) from the host over line 23 and a host clock (e.g., PIC_Clk, see Figure 5A) over line 24.
  • a reset signal e.g., PIC_RESET, see Figure 5A
  • PIC_Clk see Figure 5A
  • I/O bus 31 is 64 bits wide, but one skilled in the art can select a variety of useful bus sizes. This configuration is particularly useful with a programmable bus, such as one or more of those described in United States Patent Application Serial No. 08/415,750 (noted above, incorporated herein in full by reference).
  • Lines 32, 33, 34, 35 and 36 connect monitor CPU 20 and FPGA 30 as shown to carry program enable (PGM), initialize (INIT), done, program data (PDATA) and Configure Clock (CCIk) signals, respectively, as shown.
  • PGM program enable
  • IIT initialize
  • PDATA program data
  • CCIk Configure Clock
  • Address lines 43 carry address information from FPGA 30 to DRAM
  • DRAM 40 and data lines 44 carry data between these devices.
  • DRAM 40 is divided into two banks (only one shown). The size of each bus is device and system-specific, but selection of these parameters is well within the skill of an average artisan.
  • DRAM RAS and CAS can be driven over lines 41 and 42 (through resistors 45 and 46), respectively, by either FPGA 30 or monitor CPU 20.
  • one or more LEDs 50 can be driven over LED lines 7, 8 and 9 by either FPGA 30 or monitor CPU 20.
  • one LED 50 is an RGB LED capable of providing a wide variety of colors depending on the respective red, green and blue signals on LED lines 7, 8 and 9.
  • most of these elements are replicated with a second FPGA connected to a second monitor CPU, connected in turn to a second sensor unit and to the host system.
  • the first and second FPGA may be connected to each other through one or more programmable connections, but the details of those connections are not the subject of this invention.
  • a variety of devices can be used for a monitor CPU.
  • an 8-bit CPU such as an 8051 is particularly useful.
  • One or more analog to digital converters on inputs to the CPU allows for use of a variety of input devices.
  • One preferred monitor CPU device is the PIC16C71 , available from Microchip Technology Incorporated, 235 West Chandler Blvd., Chandler, AZ 85224-6199. This device provides many useful features, including a language of 35 single word instructions, 1024 x 14 on-chip EPROM program memory (allowing about 1 ,000 lines of code to be stored), 36 x 8 general purpose registers (SRAM), 15 special function hardware registers, an 8 level deep hardware stack, plus more, in addition to peripheral-interaction and special microcontroller features.
  • SRAM general purpose registers
  • 15 special function hardware registers an 8 level deep hardware stack, plus more, in addition to peripheral-interaction and special microcontroller features.
  • PIC16C71 includes four interrupt sources, a four-channel A/D converter and eight TTL I/O pins.
  • the manufacturer provides a number of programming options, including devices with UV-erasable programming, anti-fuse programming, and a variety of in-factory programming methods if desired. Programming such a CPU is not difficult for one skilled in the art.
  • the manufacturer's data book for the PIC16C71 includes dozens of pages including logical description of the part, the op codes and function of instructions for the part, and details about each pin, how to connect it, and how to use it.
  • Adding a monitor CPU between a host system and a semiconductor device provides a number of useful advantages. These include (1 ) providing a connection and protocol for communications with the host; (2) providing a place to store a unique device ID for the monitor CPU and, by extension, a device such as an FPGA connected to the monitor CPU.
  • some portion of the 1 ,000 lines of code in the monitor CPU are dedicated to a primary event loop which tests the status of each selected input and, depending on the result, drives signals on selected outputs.
  • Each analog input can sample at l OOKHz.
  • each analog input can be polled at a rate of 100KHz, although with four analog inputs and a variety of other inputs, plus servicing any request when needed, a more typical time for monitoring each particular input is about 10KHz. This provides more than enough time to initiate corrective action when input conditions warrant.
  • monitor CPU Since the monitor CPU is programmable, it can be programmed to use one or more conventional communication protocols. Using a simple two-line method of communication, lines 21 and 22 for RX and TX will support a number of known communication protocols. These include:
  • RS232 for example from 300-19,200 baud
  • the monitor CPU can be connected to other devices in a variety of ways. One skilled in the art can select how many and which lines might be connected to another part. In the preferred embodiment illustrated in
  • monitor CPU 20 is connected to send program enable (PGM), PData and Configure Clock (CCIk) signals to FPGA 30.
  • FPGA 30 is connected to send INIT and DONE signals to monitor CPU 20.
  • One or more of the EPROM locations or hardware registers can be loaded with an identification number unique to that monitor CPU.
  • the number may be simply a unique serial number.
  • the number might include some information about devices connected to the monitor CPU, for example, encoded information that the monitor CPU is connected to a Xilinx XC4010 FPGA and 2 megabytes of DRAM (in a selected configuration) and that a certain type of sensor is connected to the monitor CPU.
  • the information could include some sort of model number (according, for example, to a company manufacturing modules containing a monitor CPU).
  • the identification number(s) can be used by the host system.
  • the host can scan any connected modules and ascertain from the encoded numbers what sort of resources are connected and available. This might be achieved by polling any connected modules, downloading configuration information from each connected module, then, for example, preparing a database with information from the polling arranged in some useful way.
  • a unique device ID can be used as an identification address to direct host-slave communications to a specific monitor CPU, and then to downstream devices such as an FPGA. This sort of addressing is quite well known in packetized communication as is commonly used in modern PC buses.
  • the monitor CPU can include some instructions stored internally, these instructions can include boot instructions which might be only for the monitor CPU but also might include boot instructions for any connected devices. Such boot instructions might include memory initialization of the module DRAM's. They might also include some basic configuration information for a connected FPGA.
  • the monitor CPU could be connected to a ROM, e.g., an EEPROM, containing some form of configuration information, and the monitor CPU could be programmed to access that configuration information and use it to program and configure an attached FPGA or other connectable components.
  • the system also can be initialized, then controlled by a host system to provide one or more FPGA configurations.
  • a host system could use conventional bus arbitration and communication methods to deliver a request to the monitor CPU to initialize and program a connected FPGA.
  • the program or configuration commands might be available within the monitor CPU programmed memory, within an ROM accessible to the monitor CPU, or may be transmitted by the host system and forwarded by the monitor CPU to the FPGA.
  • a variety of useful sensors is provided by using the analog inputs of the monitor CPU. These include an environment temperature probe, a microphone, a microphone, and a microphone.
  • the voltage reference can be an LM431 D from National Semiconductor, Santa Clara, California. This device provides a ratiometric output comparing the input voltage to a reference voltage. In one preferred embodiment, the reference voltage is 2.5V.
  • the output VREF of the LM431 D is equal to
  • V known input Vcc This is input to VREF, pin 18 of monitor CPU HUP ("H" (m)microProcessor) shown in Figure 5B.
  • the analog value of VREF is compared to a range of 0-5 volts and digitized to one value of 255.
  • the monitor CPU can invert the input value, then divide by Vknown of + 2.5V to deliver the actual input voltage as the result.
  • the actual input voltage can be compared to a pre-set reference (which might, for example, be stored in one of the hardware registers of the monitor CPU) and the monitor CPU can make that comparison with each cycle of the main event loop and can direct appropriate action if the comparison is outside of pre-set limits.
  • a temperature monitor can be made using an LM34D, from National Semiconductor. This device puts out 10mV/°F, so a value of 1.OV corresponds to 100°F.
  • the LM34D output TEMPERATURE is connected to a corresponding input on pin 18 of monitor CPU XUP, shown in Figure 5A. The input is compared to a range of 0-5 volts, then digitized to one value of 255.
  • a threshold value can be stored in a hardware register. As one stage of the main event loop, the program running in the monitor CPU can compare the input value to the stored threshold and can direct appropriate action if the comparison is outside of pre-set limits.
  • the temperature monitor can be positioned in a variety of locations to provide information about temperature where it is most important.
  • a current sensor can be made in a variety of ways.
  • two monitor CPUs are used in conjunction with two FPGAs and two DRAMs, each composed of two banks.
  • Three copies of Vcc are provided, each independently delivered from the power supply. These copies are Vcc (system), Vcc (FPGA.1 ) (supplying FPGA.1 , the "X” FPGA, and DRAM.1 ) and Vcc (FPGA.2) (supplying FPGA.2, the "H” FPGA, and DRAM.2).
  • dual diff amps LMC6842D each monitor one current flow.
  • the Vcc X.FPGA and Vcc (system) are connected across sense resistor R5, and the difference between each leg and ground is compared in diff amp 60 to deliver output XPGA_CURRENT. This in turn is directed to pin 17 of the XUP monitor CPU.
  • the diff amp circuit is selected to deliver a signal of 1V for each ampere of current flowing through Vcc (FPGA.1 ).
  • the 0- 5V input is digitized to one of 255 values to indicate a current of 0-5 amps.
  • Vcc H.FPGA and Vcc (system) are connected across load resistor R10, and the difference between each leg and ground is compared in diff amp 61 to deliver output HPGA_CURRENT. This in turn is directed to pin 17 of the HUP monitor CPU.
  • the actual input voltage can be compared to a pre-set reference
  • the monitor CPU can make that comparison with each cycle of the main event loop and can direct appropriate action if the comparison is outside of pre-set limits.
  • differential op amps are connected rail to rail.
  • Vcc system
  • ground pin 4
  • See Figure 2B Power to the part is taken across Vcc (system) at pin 8 to ground at pin 4 (See Figure 2B). Since the sense resistor is also connected rail to rail, this allows the differential op amp to compare small differences on each leg of the sense resistor to derive an accurate value for current. This allows for an amplification factor of 100 [50mV across 10 milliOhms].
  • An FPGA such as a Xilinx XC 4010 should draw approximately 0.5 amp when active (typical values). For certain circuits, this might rise to about 1 amp under some conditions.
  • the condition of concern here is an unanticipated condition, such as two separate programmable parts trying to drive a signal in opposite directions at the same time (one driving high, one driving low) -- in effect a shorted wire. This condition can easily draw about 100 milliamps per pin, and when taken together as, say, a 32 line bus, this can cause a current draw of 3.2 amps.
  • the monitor CPU can initiate an appropriate action to isolate or turn off the FPGA until the current flows return to acceptable limits.
  • the monitor CPU can be connected to an FPGA to provide several useful functions.
  • the PGM signal (line 32 in Figure 1 ) allows the monitor
  • the CPU to pull a program enable line low to initialize the FPGA.
  • the FPGA is ready to be programmed.
  • the PGM line floats low.
  • this line would normally be driven low only when initializing the FPGA, this provides a convenient escape mechanism to shut down the FPGA to avoid a runaway or other potentially destructive condition.
  • the monitor CPU could assert PGM to shut down the FPGA to protect it from damage.
  • PGM PGM
  • the monitor CPU can preserve the state of the DRAM under certain conditions so that the state of the FPGA, or at least certain stored memory values, can be accessed for analysis of the FPGA state before the runaway condition.
  • the INIT signal (line 33) is driven by the FPGA, usually to request a wait before sending configuration data (usually less than about 2 milliseconds). This line can also be used so the FPGA can indicate an error, for example, detecting that bad data has been shifted into the FPGA (detected by CRC).
  • the DONE signal (line 35) is also driven by the FPGA and is set TRUE when the FPGA has been loaded with all configuration data.
  • the PDATA line (line 35) carries FPGA configuration program data. This configuration data might be communicated by a host to a monitor CPU, then shifted serially into the FPGA.
  • both monitor CPUs (X and H) and FPGAs (X and H) are connected to a single PDATA line and the monitor CPUs control the chip select (PGM), to program each FPGA individually.
  • the PDATA line can also be driven by an FPGA under certain conditions, e.g., to provide status information.
  • the CCIk configuration clock signal (line 36) is used to strobe program data into an FPGA.
  • CCIk does not necessarily have to come from the same monitor CPU that is providing PDATA, and in general it may be preferable to drive CCIk at a different rate than the normal clock for a monitor CPU.
  • an FPGA can provide its own configuration clock signal.
  • an FPGA is connected to an associated DRAM or bank of DRAM devices. This is helpful to provide memory resources directly to an FPGA.
  • RAS and CAS for DRAM are normally sourced by the connected FPGA. However, at certain times, the FPGA may not be available to drive RAS and CAS.
  • monitor CPU 20 line RB4 is connected to series resistor 45 and line RB5 is connected to series resistor 46 so that monitor CPU 20 is weakly coupled to DRAM 40.
  • Resistors 45, 46 are preferably about 1 KOhm. Thus, if corresponding FPGA lines are tristated, monitor CPU 20 can drive RAS and CAS as needed, generally less than or equal to about every 16 microseconds.
  • This refresh is particularly useful before FPGA 30 has been configured to include a circuit to provide RAS and CAS.
  • This monitor CPU-driven refresh is also useful when, for example, FPGA 30 must be temporarily disabled due to some environmental condition that would damage the FPGA if it continued to operate. Once the FPGA is configured and operating conditions are appropriate, it can take over sourcing RAS and CAS refresh signals. By driving lines 41, 42 directly, FPGA 30 can swamp the effect of any drive from monitor CPU 20 so FPGA 30 can guarantee RAS and CAS signals whenever FPGA 30 is running normally but can allow monitor CPU 20 to guarantee that RAS and CAS will always be available.
  • LED 50 may be any of a variety of LED output devices, including, in one preferred embodiment, an RGB LED.
  • the lines PIC_RED_, PIC_BLU_, and PIC_GRN_ can be buffered (not shown) or driven directly.
  • the blue-colored LED particularly prefers to be buffered, drawing up to about 50 mA.
  • red particularly prefers to be buffered
  • SUBSTITUTE SHEET and green LEDs need only 2 mA and 10 microAmp, respectively. If each color is driven at a selected rate, the overall color of the output can be modified to select one of about 4,000 colors. The human eye detects color at about 20Hz. By feeding the LED at selected rates up to about 1 KHz a wide range of display colors is available. For example, if red and green are driven at comparable rates, the output color is yellow. If a green LED is driven at about 100 Hz while a corresponding red LED is driven at about 10Hz, the resulting color is a reddish green. The LED can be connected simultaneously to the monitor CPU and FPGA so the LED can be driven by either source.

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Abstract

L'invention porte sur un processeur central de surveillance (20) comportant des entrées pour des capteurs (13) de mesure de conditions données relatives à l'environnement, et une connexion avec un dispositif à semi-conducteurs pouvant temporairement invalider ce dernier en cas de détection d'une condition inacceptable. Cela s'avère particulièrement utile lorsque le dispositif à semi-conducteurs est un prédiffusé programmable. Le processeur central de surveillance peut être chargé d'un seul numéro d'identification ce qui permet de communiquer par l'intermédiaire d'un bus et donc d'utiliser cela comme moyen donné à un hôte pour accéder sélectivement au dispositif à semi-conducteurs connecté. Le processeur central de surveillance (20) peut être raccordé à une DRAM (40) qui normalement est également reliée à et commandée par un dispositif à semi-conducteurs tel qu'un prédiffusé programmable (30). Pendant certaines périodes, alors que le prédiffusé programmable (30) n'est pas disponible, le processeur central de surveillance (20) peut lancer, si besoin est, un cycle de rafraîchissement de la DRAM (40). Ledit processeur central (20) peut être raccordé directement à la ou aux broches de programmation d'un prédiffusé programmable (30) pour en commander la configuration.
PCT/US1996/007017 1995-05-16 1996-05-15 Processeur central de surveillance pour dispositif logique WO1996036925A1 (fr)

Priority Applications (1)

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AU58606/96A AU5860696A (en) 1995-05-16 1996-05-15 Monitor cpu for a logic device

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US44346295A 1995-05-16 1995-05-16
US08/443,462 1995-05-16

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WO2000004481A3 (fr) * 1998-07-16 2000-03-30 Rambus Inc Appareil et procede de regulation thermique de sous-systemes de memoires
WO2007115251A3 (fr) * 2006-04-04 2007-12-27 Microchip Tech Inc Enregistreur de donnees usb-msd en temps reel et systeme de reglage et d'automatisation
US8332831B1 (en) * 2000-08-07 2012-12-11 Altera Corporation Software-to-hardware compiler with symbol set inference analysis
US20220058028A1 (en) * 2020-08-19 2022-02-24 Toshiba Tec Kabushiki Kaisha Information processing device and information processing method

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US5086238A (en) * 1985-07-22 1992-02-04 Hitachi, Ltd. Semiconductor supply incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
US5233446A (en) * 1987-03-31 1993-08-03 Canon Kabushiki Kaisha Display device
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