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WO1996037050A1 - Entrelaceur/desentrelaceur reconfigurable et generateur d'adresse destines a des flux de donnees imbriques selon un ou plusieurs plans d'entrelacement - Google Patents

Entrelaceur/desentrelaceur reconfigurable et generateur d'adresse destines a des flux de donnees imbriques selon un ou plusieurs plans d'entrelacement Download PDF

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Publication number
WO1996037050A1
WO1996037050A1 PCT/US1996/004758 US9604758W WO9637050A1 WO 1996037050 A1 WO1996037050 A1 WO 1996037050A1 US 9604758 W US9604758 W US 9604758W WO 9637050 A1 WO9637050 A1 WO 9637050A1
Authority
WO
WIPO (PCT)
Prior art keywords
interleaving
data
stream
interleaved
input
Prior art date
Application number
PCT/US1996/004758
Other languages
English (en)
Inventor
Greg Zweigle
Torkjell Berge
Original Assignee
Advanced Hardware Architectures, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Hardware Architectures, Inc. filed Critical Advanced Hardware Architectures, Inc.
Publication of WO1996037050A1 publication Critical patent/WO1996037050A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2732—Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2789—Interleaver providing variable interleaving, e.g. variable block sizes

Definitions

  • the invention relates to the field of data processing and can be used to aid communication systems which require noise tolerance.
  • Communication systems use interleavers to transform data which has been corrupted by correlated noise into data in which the noise appears to be distributed in time with less correlation.
  • the deinterleaver transforms the data back into its original form.
  • the overall interleave/deinterleave operation is such that the received data is identical to the transmitted data in the absence of noise.
  • Several algorithms have been developed which perform the interleave/deinterleave function. These algorithms lend themselves to different implementations, each with their own advantages and disadvantages.
  • FIG. 1 illustrates Ramsey's original implementation of his type II interleaver.
  • the n2 parameter specifies how many contiguous symbols in the interleaved sequence over which the minimum spacing nl is valid.
  • the nl parameter specifies the minimum spacing in the original stream that can be contained in any n2 contiguous symbols in the interleaved stream.
  • the blocks 101, 102, 103, and 104 are shift registers with delay n2-l.
  • the blocks 106, 107, 108, and 109 are adders which serve as muxes when nl and n2 are constrained appropriately.
  • the constraints on n2 and nl are that n2 and nl+1 must be relatively prime and n2 > nl+1.
  • the commutator switch 105 sequences counter-clockwise for every symbol received at the input 111.
  • the continuation symbol 110 indicates that the number of shift and add stages is not explicitly specified by the drawing. For this implementation, a total of nl*(n2-l) delay elements are required.
  • the output is from 112.
  • Figure 2 illustrates a basic Forney type interleaver.
  • the shift registers 200, 201, 202, and 203 are of length specified inside the register and shift the data one position to the right every I th input data symbol.
  • the shift register 200 has a total delay of T*I and the shift register 201 has a total delay of 2*T*I.
  • the commutators 204 and 205 move one position every input symbol and are synchronized with each other.
  • T*I is defined as N.
  • FIG. 3a the data arrives as 306 and exits either interleaved or deinterleaved as 307.
  • the shift register is 304 and the commutators 308 and 309.
  • the control is shown as 305.
  • Fig. 3b the RAM is 300. Data is written into the RAM in 302 and is read from the RAM is 303.
  • the 301 is the address generation and control for the operation.
  • An apparatus implementing a single deinterleaving algorithm suffers from the drawback of only being able to deinterleave data streams interleaved by a single protocol. This proves particularly troublesome when users wish to design a system that can receive and deinterleave data interleaved using different interleaving algorithms.
  • DBS Direct Broadcast Satellite
  • the standard interleaving protocol for Direct Broadcast Satellite (DBS) systems is based on Ramsey's type II algorithm.
  • the protocol for DBS systems is based on Forney's algorithm.
  • the present invention provides a cost effective deinterleaving apparatus that is selectively configurable for data streams interleaved according to one of a plurality of data streams (note that since a deinterleaver is also an interleaver this invention also is a configurable interleaving apparatus).
  • This is accomplished with the invention of a single, cost efficient address generation unit that can be used for multiple algorithms by dynamically controlling key parameters during operation.
  • the system level diagram of the deinterleaver is similar to that shown in Fig. 3b and Fig. 4.
  • the key distinction is that the address generation and control unit is capable of deinterleaving a plurality of interleaved data streams with a cost efficient technique. It should be noted that there are no special constraints placed on the RAM by this invention. It can be any standard type, such as dynamic or static, single port or multiple port.
  • a Generate Write Address block remains the same for all interleaving protocols. It generates an address for writes which restarts every time the last address is written.
  • a Generate Read Address block also remains the same for all interleaving protocols. It generates the read address for a RAM.
  • the parameters specific to each interleaving algorithm are generated in a Parameter Set block. There can be an arbitrary number of Parameter Set blocks, one for each interleaving protocol. A switch selects the correct set of parameters for each interleaving protocol.
  • Such a device allows the deinterleaving apparatus to receive a data stream which has been interleaved according to one of a plurality of interleaving schemes and output the original data stream.
  • a control block is the same for all interleaved data streams and allows the address generation and parameter units to update based on data either being written to or read from the RAM.
  • the Generate Write Address, Generate Read Address and control blocks are used for all interleaving protocols, thereby providing cost efficiency. Additionally, in the preferred embodiment, the most complexity in these three blocks. This allows the Parameter Set blocks to be produced at very low cost.
  • Figure 1 illustrates a Ramsey type II interleaver as described by John L. Ramsey.
  • Figure 2 illustrates a Forney interleaver similar to description of David G. Forney.
  • Figure 3 illustrates two different implementations of interleaver/deinterleavers in the state of the art.
  • Figure 4 illustrates a block diagram of one embodiment of a circuit which performs deinterleaving according to a plurality of protocols.
  • Figure 5 illustrates the a block diagram of the preferred embodiment of the present invention.
  • Figure 6 illustrates one example of a hardware implementation of the address generation unit for deinterleaving a Ramsey type II or Forney interleaved data stream.
  • the present invention is for a deinterleaving apparatus that would be reconfigurable by a user to deinterleave a data stream according to the Ramsey type II or the Forney protocols, or even using a proprietary scheme. This will provide users with a deinterleaver that has greater applicability. More specifically, it allows a user in the United States to receive and deinterleave interleaved data from Europe without having to purchase a deinterleaving apparatus utilizing a different algorithm.
  • One technique for providing a multipurpose deinterleaver is to include the appropriate circuitry for all desired deinterleavers in a single apparatus and then use a hardware or software switch to engage the desired deinterleaver.
  • Such a system for deinterleaving one of two types of interleaved data is shown in Figure 4 for the RAM based deinterleave implementation approach.
  • the RAM is 400
  • the data is in 403
  • the data out is 404.
  • the two different address generation units and control are shown as 401 and 402.
  • the switch 405 is used to activate the desired deinterleaving algorithm.
  • This "brute-force" scheme has the disadvantage of requiring a completely separate apparatus for each allowable type of interleaved data.
  • FIG. 5 shows a block diagram of the preferred embodiment of the present invention which is used in place of 301 in Fig. 3 or in place of 401, 402, and 405 in Fig. 4.
  • the Generate Write Address block 500 remains the same for all interleaving protocols. It generates an address for writes which restarts every time the last address is written.
  • the Generate Read Address block 501 remains the same for all interleaving protocols. It generates the read address for the RAM.
  • the parameters specific to each interleaving algorithm are generated in the Parameter Set blocks 502, 503, and 504. There can be an arbitrary number of these units, one for each interleaving protocol.
  • the commutator 505 switches the correct set of parameters into 500 and 501 for each interleaving protocol. When this device is used in place of 301 in Fig. 3, it allows apparatus 300 to receive a data stream 302 which has been interleaved according to one of a plurality of interleaving schemes and output the original data stream to 303.
  • FIG. 506 is the same for all interleaved data streams and allows the address generation and parameter units to update based on data either being written to the RAM through 302 or read from the RAM through 303. Because the blocks 500, 501, and 506 are reused for all interleaving protocols, cost efficiency is achieved. Furthermore, this invention places the most complexity in blocks 500, 501, and 506 and therefore the parameter sets 502, 503, and 504 can be very low cost.
  • Figure 6 shows one possible hardware implementation of the invention of Figure 5. This example deinterleaves two possible types of interleaved data streams, the Ramsey type II interleaved data stream and the Forney interleaved data stream.
  • This example is designed to work with a single port RAM which requires reads and writes to be disjoint in time, hence the mux 605.
  • a read always precedes a write since the same address can generated by both the read address 604 and write address 600 circuitry.
  • Another possible hardware implementation for a dual port RAM allows concurrent reads and writes and would eliminate the need for the mux 605.
  • Blocks 605, 606, 607, 608, 609, 610, and all objects labeled 612 are two input muxes. These devices route either the '0' input or the '1' input to the 'm' output based on the value of the select signal arriving at the side of the object.
  • All blocks labeled 611 are summation devices and the block labeled 613 is a subtraction device. All blocks labeled 614 are data storage devices. All blocks labeled 615 are equality comparators, whose output goes active when the equality test is evaluated true. The block 616 is a greater-than-or-equal-to comparator.
  • the Write Address Generation Unit 600 increments linearly through the RAM address space until it reaches the RAM size, selected by the mux 606, at which time it starts over at the first address.
  • the go_write signal tells the write address to increment every time a byte is received at the RAM and is generated by the control 506 ( Figure 5).
  • the Read Address Generation Unit 604 changes the read address when the go_read signal is asserted indicating that data is to be removed from the RAM.
  • the go-read signal is generated by the control 506 and will not begin to assert until the RAM has been completely written once. After this time, the go_read signal always asserts when a new byte is received at the RAM. In other words, once the RAM has been written once, data is read out of the RAM only when data is written into the RAM. To flush the RAM, a dummy byte can be written under control 506. When the read address exceeds the RAM size, muxed through 606, then the RAM size is subtracted from the read address.
  • the two sets of parameters 601 and 602 are shown in the example of Figure 6.
  • the Ramsey II parameter set 601 provides dynamic information to the Read Address Generation Unit 604.
  • the Forney parameter set 602 provides fixed information to the Read Address Generation Unit 604.
  • the set of muxes 603 perform the function of the commutator 505 ( Figure 5) and is set before deinterleaving occurs.
  • the set of muxes for this implementation are the RAM size, from mux 606; an additional count number of 0 or 1, from mux 607 the
  • Ramsey type II nl parameter from mux 608; a count parameter, from mux 609; and a mux select signal from mux 610.
  • the select signal to mux group 603 chooses among the two interleave types.
  • the Ramsey type II deinterleave is performed by noticing from Figure 1 that the original data is ordered by offsets of n2 except every nl+1 it is offset by n2+nl+l.
  • the circuit pair 601 and 604 generate the read addresses to extract the original ordering out of the interleaved data stream.
  • the circuit pair 602 and 604 generate the read addresses to extract the data out of the interleaved data stream.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

Appareil de désentrelacement d'un bon rapport coût-efficacité qui offre un choix de configurations pour des flux de données imbriquées selon un ou plusieurs plans d'entrelacement. L'opération se réalise en introduisant une multitude de jeux de paramètres destinés à l'appareil, où chaque jeu correspond à un algorithme de désentrelacement particulier. Un utilisateur peut alors choisir un algorithme de désentrelacement particulier avec lequel il peut appliquer un plan d'entrelacement d'entrée. Le faible coût de réalisation s'explique par la réutilisation d'un seul appareil pour les algorithmes de désentrelacement en ne modifiant que quelques paramètres clés. Ramsey et Forney constituent deux exemples d'algorithmes de désentrelacement que l'on peut appliquer. L'invention s'avère également utile pour l'entrelacement, puisque tout désentrelaceur est aussi un entrelaceur.
PCT/US1996/004758 1995-05-15 1996-04-04 Entrelaceur/desentrelaceur reconfigurable et generateur d'adresse destines a des flux de donnees imbriques selon un ou plusieurs plans d'entrelacement WO1996037050A1 (fr)

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US44107895A 1995-05-15 1995-05-15
US08/441,078 1995-05-15

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Cited By (24)

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Publication number Priority date Publication date Assignee Title
GB2332836A (en) * 1997-12-24 1999-06-30 Daewoo Electronics Co Ltd Adaptive convolutional interleaver and deinterleaver
WO2000010257A1 (fr) * 1998-08-17 2000-02-24 Hughes Electronics Corporation Dispositif d'entrelacement de code turbo a performances quasi optimales
GB2343342A (en) * 1998-10-28 2000-05-03 Int Mobile Satellite Org Satellite communication system with variable data transmission rate
EP1039646A1 (fr) * 1999-03-05 2000-09-27 Mitsubishi Electric France Dispositif et méthode d'entrelacement pour entrelacer un jeu de données
US6574767B2 (en) 1998-01-23 2003-06-03 Hughes Electronics Corporation Forward error correction scheme for cellular mobile radio systems using universal turbo codes
RU2217864C2 (ru) * 1998-12-21 2003-11-27 Самсунг Электроникс Ко., Лтд. Устройство и способ перемежения обращенного перемежения для системы связи
US6862706B2 (en) 1998-08-27 2005-03-01 Hughes Electronics Corp. Method for a general near optimal turbo code trellis termination
US6888897B1 (en) 2000-04-27 2005-05-03 Marvell International Ltd. Multi-mode iterative detector
US6892342B2 (en) 1998-01-23 2005-05-10 Hughes Electronics Corporation Sets of rate-compatible universal turbo codes nearly optimized over various rates and interleaver sizes
US6965652B1 (en) 2000-06-28 2005-11-15 Marvell International Ltd. Address generator for LDPC encoder and decoder and method thereof
US7000177B1 (en) 2000-06-28 2006-02-14 Marvell International Ltd. Parity check matrix and method of forming thereof
US7072417B1 (en) 2000-06-28 2006-07-04 Marvell International Ltd. LDPC encoder and method thereof
US7099411B1 (en) 2000-10-12 2006-08-29 Marvell International Ltd. Soft-output decoding method and apparatus for controlled intersymbol interference channels
WO2006053739A3 (fr) * 2004-11-16 2006-09-14 Infineon Technologies Ag Changement sans coupure de la profondeur d'un entrelaceur convolutionnel general pendant une transmission sans perte de donnees
EP1294153A3 (fr) * 2001-09-14 2007-02-14 Texas Instruments Incorporated Entrelacement pour la prévention d'interférence à large bande dans un système de communication multiporteuse
US7184486B1 (en) 2000-04-27 2007-02-27 Marvell International Ltd. LDPC encoder and decoder and method thereof
EP1919085A3 (fr) * 2004-11-16 2008-05-21 Infineon Technologies AG Changement de profondeur sans interruption d'un entrelaceur à convolution pendant la transmission sans perte de données
US7536624B2 (en) 2002-01-03 2009-05-19 The Directv Group, Inc. Sets of rate-compatible universal turbo codes nearly optimized over various rates and interleaver sizes
US7577892B1 (en) 2005-08-25 2009-08-18 Marvell International Ltd High speed iterative decoder
EP1962196A4 (fr) * 2005-12-16 2010-10-06 Nec Corp Système et méthode d'allocation de zone de stockage et dispositif de commande correspondant
US7861131B1 (en) 2005-09-01 2010-12-28 Marvell International Ltd. Tensor product codes containing an iterative code
EP2395668A1 (fr) * 2010-06-10 2011-12-14 Nxp B.V. Entrelaceur reconfigurable comportant des compteurs reconfigurables
US8321769B1 (en) 2008-11-06 2012-11-27 Marvell International Ltd. Multi-parity tensor-product code for data channel
GB2491377A (en) * 2011-05-31 2012-12-05 British Broadcasting Corp Method and apparatus for memory access in an interleaver

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Cited By (61)

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Publication number Priority date Publication date Assignee Title
GB2332836A (en) * 1997-12-24 1999-06-30 Daewoo Electronics Co Ltd Adaptive convolutional interleaver and deinterleaver
US7346827B2 (en) 1998-01-23 2008-03-18 The Directv Group, Inc. Forward error correction scheme for data channels using universal turbo codes
US7925963B2 (en) 1998-01-23 2011-04-12 Dtvg Licensing, Inc. Sets of rate-compatible universal turbo codes nearly optimized over various rates and interleaver sizes
US7840871B2 (en) 1998-01-23 2010-11-23 The Directv Group, Inc. Forward error correction scheme for data channels using universal turbo codes
US7840869B2 (en) 1998-01-23 2010-11-23 The Directv Group, Inc. Forward error correction scheme for data channels using universal turbo codes
US6892342B2 (en) 1998-01-23 2005-05-10 Hughes Electronics Corporation Sets of rate-compatible universal turbo codes nearly optimized over various rates and interleaver sizes
US6574767B2 (en) 1998-01-23 2003-06-03 Hughes Electronics Corporation Forward error correction scheme for cellular mobile radio systems using universal turbo codes
US6665829B2 (en) 1998-01-23 2003-12-16 Hughes Electronics Corporation Forward error correction scheme for CDMA data channels using universal turbo codes
US7526687B2 (en) 1998-08-17 2009-04-28 The Directv Group, Inc. Turbo code interleaver with near optimal performance
US20130061109A1 (en) * 1998-08-17 2013-03-07 The Directv Group, Inc. Turbo code interleaver with near optimal performance
US8671324B2 (en) * 1998-08-17 2014-03-11 Dtvg Licensing, Inc. Turbo code interleaver with near optimal performance
US6334197B1 (en) 1998-08-17 2001-12-25 Hughes Electronics Corporation Turbo code interleaver with near optimal performance
US6925587B2 (en) 1998-08-17 2005-08-02 Hughes Electronics Corporation Turbo code interleaver with near optimal performance
US7761750B2 (en) 1998-08-17 2010-07-20 The Directv Group, Inc. Turbo code interleaver with near optimal performance
US8321725B2 (en) 1998-08-17 2012-11-27 The Directv Group, Inc. Turbo code interleaver with optimal performance
US7657797B2 (en) 1998-08-17 2010-02-02 The Directv Group, Inc. Turbo code interleaver with near optimal performance
WO2000010257A1 (fr) * 1998-08-17 2000-02-24 Hughes Electronics Corporation Dispositif d'entrelacement de code turbo a performances quasi optimales
US7827465B2 (en) 1998-08-27 2010-11-02 The Directv Group, Inc. Method for a general near optimal turbo code trellis termination
US7487431B2 (en) 1998-08-27 2009-02-03 The Directv Group, Inc. Method for a general near optimal turbo code trellis termination
US7779329B2 (en) 1998-08-27 2010-08-17 The Directv Group, Inc. Method for a general near optimal turbo code trellis termination
US8201048B2 (en) 1998-08-27 2012-06-12 The Directv Group, Inc. Method for a general near optimal turbo code trellis termination
US8429490B2 (en) 1998-08-27 2013-04-23 Dtvg Licensing, Inc. Method for a general near optimal turbo code trellis termination
US6862706B2 (en) 1998-08-27 2005-03-01 Hughes Electronics Corp. Method for a general near optimal turbo code trellis termination
GB2343342A (en) * 1998-10-28 2000-05-03 Int Mobile Satellite Org Satellite communication system with variable data transmission rate
RU2217864C2 (ru) * 1998-12-21 2003-11-27 Самсунг Электроникс Ко., Лтд. Устройство и способ перемежения обращенного перемежения для системы связи
EP1039646A1 (fr) * 1999-03-05 2000-09-27 Mitsubishi Electric France Dispositif et méthode d'entrelacement pour entrelacer un jeu de données
US6701467B1 (en) 1999-03-05 2004-03-02 Mitsubishi Electric Telecom Europe Interleaver device and method for interleaving a data set
US6888897B1 (en) 2000-04-27 2005-05-03 Marvell International Ltd. Multi-mode iterative detector
US7453960B1 (en) 2000-04-27 2008-11-18 Marvell International Ltd. LDPC encoder and encoder and method thereof
US7340003B1 (en) 2000-04-27 2008-03-04 Marvell International Ltd. Multi-mode iterative detector
US7751505B1 (en) 2000-04-27 2010-07-06 Marvell International Ltd. LDPC encoder and encoder and method thereof
US8136005B1 (en) 2000-04-27 2012-03-13 Marvell International Ltd. Multi-mode iterative detector
US7184486B1 (en) 2000-04-27 2007-02-27 Marvell International Ltd. LDPC encoder and decoder and method thereof
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