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WO1997049189A1 - Circuit numerique de quatrieme ordre de mise en forme du bruit - Google Patents

Circuit numerique de quatrieme ordre de mise en forme du bruit Download PDF

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Publication number
WO1997049189A1
WO1997049189A1 PCT/US1997/010735 US9710735W WO9749189A1 WO 1997049189 A1 WO1997049189 A1 WO 1997049189A1 US 9710735 W US9710735 W US 9710735W WO 9749189 A1 WO9749189 A1 WO 9749189A1
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WO
WIPO (PCT)
Prior art keywords
input
output
signal
bit
integrator
Prior art date
Application number
PCT/US1997/010735
Other languages
English (en)
Inventor
Alfredo Linz
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/668,532 external-priority patent/US6005505A/en
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1997049189A1 publication Critical patent/WO1997049189A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
    • H03M7/3033—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs
    • H03M7/3035—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator having a higher order loop filter in the feedforward path, e.g. with distributed feedforward inputs with provisions for rendering the modulator inherently stable, e.g. by restricting the swing within the loop, by removing part of the zeroes using local feedback loops, by positioning zeroes outside the unit circle causing the modulator to operate in a chaotic regime
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M7/3028—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one

Definitions

  • This invention relates to a digital noise shaping circuit. More particularly, this invention relates to a fourth order digital noise shaping circuit for use in a digital-to-analog conversion circuit.
  • DACs digital-to-analog converter circuits
  • resistor/capacitor divider method or use a sigma-delta conversion method, to convert digital signals to analog signals.
  • Sigma-delta DACs are preferred because of their inherent feasibility to be manufactured in integrated circuits.
  • These DACs typically create 1-bit signals from multi-bit digital input signals. This quantization, if performed by merely truncating or rounding the multi- bit signal, would introduce a large amount of noise in the signal passband, thereby destroying the signal quality. Noise shaping pushes the quantization noise out of the signal passband. Also, the 1-bit signal can be converted to an analog signal with no linearity errors.
  • the present invention is for a fourth order digital noise shaping circuit which takes an oversampled multi-bit input signal from the output of an interpolator circuit and converts the multi-bit signal to a 1-bit signal while shaping the quantization noise according to a high-pass function.
  • a signal transfer function (STF) and a noise transfer function (NTF) define the operation of the noise shaper circuit.
  • the NTF is chosen so zeros are introduced inside the noise stopband, which is substantially equal to the signal passband, while also achieving a flat high-frequency response. Once the NTF is determined, the STF is determined.
  • a set of feedback coefficients are used to multiply the 1-bit output signal and feed it back to earlier stages in the noise shaper circuit to achieve the proper frequency response.
  • Another set of coefficients is used to produce local feedback around certain stages of the noise shaper.
  • the coefficients are chosen to achieve equiripple quantization noise density in the passband and a flat stopband. Suitable scaling factors between stages are also used to make the circuit stable for a predetermined range of input amplitudes.
  • a hardware block within the digital noise shaper circuit includes two integrators and associated adders which are identically scaled.
  • two integrators and associated adders which are identically scaled.
  • FIG. 1 is a block diagram of a digital to analog converter block utilizing the noise shaper of the present invention
  • Fig. 2 is a schematic representation of the present noise shaper
  • Fig. 3 is a signal flow graph (SFG) of the present noise shaper
  • Fig. 4 is a plot of the poles and zeros in the s plane for the present noise shaper
  • Fig. 5 is a plot of the noise transfer function magnitude of the present noise shaper
  • Fig. 6 is a plot of the poles and zeros in the z plane of the present noise shaper
  • Fig. 7 is a graph of the noise transfer function, in the 0 - 10 KHz range, of the present noise shaper
  • Fig. 8 is a plot of the ideal and realizable zeros of the present noise shaper
  • Fig. 9 is a plot comparing two embodiments of noise transfer functions
  • Fig. 10 is a plot of the noise and signal transfer functions of the noise shaper
  • Fig. 11 is a plot of the signal transfer function magnitude and phase in the passband of the noise shaper.
  • Fig. 12 is a graph of the group delay (sec.) of the noise shaper.
  • Figure 1 illustrates a block diagram of the playback path of an audio CODEC.
  • a suitable audio CODEC is described in application Serial No. 08/333,467, entitled “Stereo Audio CODEC", filed November 2, 1994, assigned to the common assignee of the present invention and incorporated herein for all purposes.
  • Noise shaper 802 may be a stand-alone circuit, or may otherwise be included in an audio processing circuit, such as the audio CODEC illustrated.
  • noise shaper block 802 of Fig. 2 takes at least one multi- bit audio signal, illustrated as in.l and in.2, quantizes each respective input signal, converting the respective input signal to a 1-bit output signal, while shaping the quantization noise associated with the respective signal according to a high-pass function.
  • the remaining description of noise shaper block 802 is directed to only one multi- bit digital input signal, although the processing of another is identical.
  • the 1-bit output signal 842 is input to integrators 822a and 822b. Integrators 822a and b must have suitable scaling factors on the input, to make the loop stable for a predetermined range of input amplitudes, as determined by the remainder of the digital path shown in Fig. 2.
  • the simple additive noise model shown in Fig. 2 is used to represent the quantizer.
  • a signal Transfer Function (STF) Y/X where X is the digital audio input signal 842
  • a noise Transfer Function (NTF) Y/E where E is the quantization noise (modeled as additive, white, uniformly distributed noise).
  • a signal flow graph (SFG) for noise shaper block 802 is shown in Fig. 3.
  • the transfer functions are developed as follows: Forward Path Gains: The cumulative gains of all possible direct paths from input to output:
  • the transfer functions have the form:
  • the coefficients are chosen to match a Chebyshev function, which yields equiripple quantization noise in the passband and a flat stopband.
  • the values for Ai and the Bi are obtained from the Ci and Wi in the above equations by matching the NTF to the desired shaping function.
  • a function is chosen for the NTF which has zeros equally spaced inside the noise stopband (i.e., the signal band), and a flat high- frequency response.
  • the stopband edge, the stopband attenuation and the filter order must be determined. Since the stopband attenuation is preferably at least 88 dB and the stopband edge is about 4 KHz for an input sampling rate of 8 KHz, or equivalently, about 24 KHz at the maximum sampling rate of 48 KHz, the filter order preferred is four.
  • N 4
  • m ranges from 0 to 3
  • el is related to the attenuation G given in dB by:
  • This is the highest sampling rate at which the noise shaper 802 will operate, and corresponds to an oversampling factor of 64 times the highest sampling rate for the input signal. It should be understood, however, that the noise shaper will be operated at other (lower) sampling rates.
  • Fig. 6 gives the pole-zero diagram in the z-plane for noise shaper 802.
  • the preferred frequency response of the discrete filter for noise shaper 802 is shown in Fig. 7.
  • the numerator in the transfer function of the selected structure must be matched to the discrete filter.
  • the nature of the zeros that can be realized with it are found by equating the numerator of the NTF to zero, producing:
  • CI, C2 are not independent because they are related to Bl, 52 as specified by the NTF equation, previously described.
  • the solution yields the four roots, as follows:
  • Figs. 2 and 3 allow two pairs of complex zeros, both of which have real parts equal to 1. This means they cannot be on the unit circle. However, if their angles are small enough, they will still provide enough attenuation. To actually be able to have zeros on the unit circle, more feedback loops (i.e., more coefficients) must be used.
  • Bl, 52 are selected so that preferably the zeros have the same angles as those required by the ideal transfer function. This is shown in Fig. 8, where the angles are exaggerated.
  • the values of Bl, B2 also depend on the values of K2 and K4.
  • the scaling coefficients k shown in Fig. 2 as k ⁇ -k ⁇ should be adjusted so noise shaper 802 is stable for the desired range of amplitudes for the input signals. Preferably, this is accomplished with the following criteria in mind:
  • the scaling coefficients, k are equal for the first and third integrators 822a (Fig. 2) and also for the second and fourth integrators 822b. This permits re-utilization of one hardware block 830 containing two integrators 822a and b and associated adders 848 without having to change scaling coefficients, k. Hardware block 830 is enclosed inside the dotted line in Fig. 2.
  • the scaling coefficients, k are only negative powers of two, so only hardwired shifts are used, without multiplication.
  • the scaling coefficients, k set the stability range to be compatible with the desired input signal levels.
  • the feedback coefficient values Bl and B2, for positioning the zeros, are obtained using these scaling factors and preferably are:
  • STF Signal Transfer Function
  • A; B; shown in Fig. 2 the STF for noise shaper 802 is fixed. If the oversampling ratio is large enough, the STF will have little effect inside the signal band. Otherwise, the poles can be tweaked to some extent, but this is not desirable, because stability may be compromised.
  • a better embodiment is to compensate for any distortion in the interpolation block 800 (Fig. 1).
  • the magnitudes of the STF and the NTF are shown in Fig. 10 over the entire frequency range.
  • the preferred STF response in the passband appears in more detail in Fig. 11.
  • the group delay inside the passband is shown in Fig. 12.
  • the passband tilt if significant enough to violate the preferred ripple requirement for the entire playback path, can be compensated, preferably in interpolator 800. With regard to group delay distortion, however, it is still acceptable.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

L'invention propose un circuit numérique de mise en forme du bruit qui remplit une fonction de transfert des signaux et une fonction de transfert du bruit, avec des coefficients et des facteurs d'échelle du gain associés; ledit circuit assure une réponse en fréquence prédéterminée ainsi qu'une bande passante du signal et une bande coupée du bruit; il convertit également des signaux à plusieurs bits en des signaux à un bit.
PCT/US1997/010735 1996-06-20 1997-06-20 Circuit numerique de quatrieme ordre de mise en forme du bruit WO1997049189A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/668,532 1996-06-20
US08/668,532 US6005505A (en) 1994-11-02 1996-06-20 Fourth order digital noise shaper circuit

Publications (1)

Publication Number Publication Date
WO1997049189A1 true WO1997049189A1 (fr) 1997-12-24

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Family Applications (1)

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PCT/US1997/010735 WO1997049189A1 (fr) 1996-06-20 1997-06-20 Circuit numerique de quatrieme ordre de mise en forme du bruit

Country Status (1)

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WO (1) WO1997049189A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996015484A2 (fr) * 1994-11-02 1996-05-23 Advanced Micro Devices, Inc. Circuit audio monolithique pour pc
US5598158A (en) * 1994-11-02 1997-01-28 Advanced Micro Devices, Inc. Digital noise shaper circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996015484A2 (fr) * 1994-11-02 1996-05-23 Advanced Micro Devices, Inc. Circuit audio monolithique pour pc
US5598158A (en) * 1994-11-02 1997-01-28 Advanced Micro Devices, Inc. Digital noise shaper circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
TAPANI RITONIEMI ET AL: "DESIGN OF STABLE HIGH ORDER 1-BIT SIGMA-DELTA MODULATORS", PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, NEW ORLEANS, MAY 1 - 3, 1990, vol. 4 OF 4, 1 May 1990 (1990-05-01), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 3267 - 3270, XP000163530 *
TAPANI RITONIEMI ET AL: "MODELLING AND PERFORMANCE ESTIMATION OF SIGMA-DELTA MODULATORS", POSTER SESSIONS, SINGAPORE, JUNE 11 - 14, 1991, vol. 5 OF 5, 11 June 1991 (1991-06-11), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 2705 - 2708, XP000298990 *

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