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WO1997011492A1 - Dispositif a semi-conducteurs et son procede de fabrication - Google Patents

Dispositif a semi-conducteurs et son procede de fabrication Download PDF

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Publication number
WO1997011492A1
WO1997011492A1 PCT/JP1995/001875 JP9501875W WO9711492A1 WO 1997011492 A1 WO1997011492 A1 WO 1997011492A1 JP 9501875 W JP9501875 W JP 9501875W WO 9711492 A1 WO9711492 A1 WO 9711492A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
semiconductor device
bonding
metal thin
semiconductor
Prior art date
Application number
PCT/JP1995/001875
Other languages
English (en)
Japanese (ja)
Inventor
Yasuhiko Sasaki
Akiomi Kohno
Masaya Horino
Mitsuo Usami
Masahide Tokuda
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/001875 priority Critical patent/WO1997011492A1/fr
Priority to JP51256397A priority patent/JP3400459B2/ja
Publication of WO1997011492A1 publication Critical patent/WO1997011492A1/fr

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    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which various semiconductor elements are joined to achieve high density and multifunctionality, and a method of manufacturing the same.
  • Hei 5-109593 discloses that a semiconductor device is stacked via a solder plate and then heated. A method for manufacturing a semiconductor device for bonding a semiconductor element is disclosed.
  • No. 17 1643 discloses that solid-state bonding is performed by irradiating an atom or ion energy beam to the electrodes of a substrate of a semiconductor device and a CCB bump as a bonding material. A bonding method for performing liquid phase bonding by reflowing bumps is disclosed.
  • the method of bonding the silicon substrate by bringing the silicon substrate into close contact and heating according to the prior art 1 is a bonding method with high dimensional accuracy after bonding, but the bonding temperature is low. Since it is as high as 10 oot or more, if this bonding method is used to join the silicon substrate (conductor element) on which the element is formed, the semiconductor element will be destroyed due to melting of the wiring inside the semiconductor element, diffusion of the semiconductor element, etc. It has been done.
  • the bonding operation can be easily performed because the adhesive is used. There is a possibility that the bonded semiconductor element may be detached, and the reliability as a semiconductor device is not sufficient. In addition, since the heat resistance of the bonding portion is large, it is difficult to dissipate the heat of the semiconductor element bonded by the adhesive, and the heat may hinder the semiconductor device. Furthermore, since the adhesive is liquid and it is difficult to control the film thickness, it is difficult to secure the dimensional accuracy of the joint.
  • the method of manufacturing a semiconductor device in which the semiconductor elements of the prior art 3 are stacked via a solder plate and then heated to join the semiconductor elements can easily perform the joining work as in the above-described prior art 2.
  • the flux contained in the solder is caught in the connection portion and evaporates, voids are generated and it is difficult to secure the bonding strength. Also, the residual flux may cause corrosion at the joint.
  • the bonding temperature is higher than the melting point of the solder, the semiconductor elements that can be bonded are limited to those whose heat-resistant temperature is lower than the melting point of the solder.
  • the melting temperature of the joint is the melting point of the solder, it is not possible to use the same solder when joining a plurality of semiconductor devices in sequence according to the manufacturing process.
  • An object of the present invention is to provide a highly reliable semiconductor device in which various semiconductor elements are joined and a method for manufacturing the same.
  • the above object can be achieved by solid-state bonding of at least two or more semiconductor elements to a junction between the semiconductor elements via a metal thin film.
  • the joint In order to manufacture a highly reliable semiconductor device by joining semiconductor elements, the joint must have sufficient strength, the joint must have high heat dissipation, and the dimensional accuracy after joining must be high. It is necessary that the heating temperature at the time is low.
  • FIG. 8 (a) is a graph showing the relationship between bonding strength and bonding pressure at a bonding temperature of 10 Ot: where the vertical axis indicates bonding strength and the horizontal axis indicates bonding pressure.
  • Fig. 8 (b) is a graph showing the relationship between the joining strength and the joining temperature at a joining pressure of 5 MPa, where the vertical axis represents the joining strength and the horizontal axis represents the joining temperature.
  • a bonding temperature of 100 or more and a bonding pressure of 5 OMPa are required.
  • the pressure may be set to MPa or more.
  • the junction temperature range is 100 to 400 and the junction pressure range is 5 to 50 MPa. This temperature Since the pressure range and the pressure range are sufficiently low for the semiconductor device, this bonding method is adopted for the bonding of the semiconductor device, and the high-density, multifunctional and highly reliable semiconductor The device can be provided.
  • the semiconductor element is solid-phase bonded in a thickness direction of the semiconductor device.
  • the semiconductor element is arranged on a substrate in a length direction or a width direction of the semiconductor device and solid-phase bonded.
  • An optical semiconductor element and an optical waveguide are solid-phase bonded on a substrate via a metal thin film.
  • the metal film is composed of two or more thin film layers made of different materials.
  • the metal film is composed of a titanium (Ti) thin film and a gold (Au) thin film.
  • the metal film may be a titanium (Ti) thin film of 0,5 to 1 OOO nm and a gold (Au) of 2 to 1 OOOO nm It is composed of a thin film.
  • a plurality of films are formed electrically independently on the bonding surface of the semiconductor element, and a part or all of the plurality of formed metal thin films is used as an electrode.
  • Desirable aspects of the method for manufacturing a semiconductor device of the present invention are as follows.
  • the solid-state bonding is performed in such a manner that at least one of the bonding surfaces of the semiconductor elements to be bonded to each other is a bonding surface on which a metal thin film is formed in advance, and the solid-state bonding is performed in a vacuum.
  • the metal thin film is formed in a bonding atmosphere in which the bonding surface does not re-contaminate.
  • the joining surfaces are brought into close contact with each other at a temperature equal to or lower than the solidus temperature and pressurized to join in the solid state.
  • the metal thin film is composed of two or more thin film layers made of different materials.
  • the metal thin film is composed of a titanium (Ti) thin film and a gold (Au) thin film.
  • the metal thin film comprises a titanium (Ti) thin film of 0.5 to 1000 nm and a gold (Au) thin film of 2 to 1000 nm.
  • a semiconductor element has an independent function
  • a component of a semiconductor device Refers to a component of a semiconductor device.
  • an optical waveguide in an optical semiconductor device is also called a semiconductor element.
  • solid-phase bonding means bonding at a temperature lower than the solidus of the bonding material, and includes bonding at a temperature higher than the solidus of the bonding material.
  • the solid-state bonding of the semiconductor element via the metal thin film can lower the bonding temperature and the bonding pressure, so that the reliability of the semiconductor device can be secured. In addition, sufficient bonding strength can be ensured, and there is no concern that the semiconductor element will be detached because the bonded portion does not deteriorate with time. In addition, since the melting temperature of the bonding portion is sufficiently higher than the bonding temperature, the semiconductor device that has been bonded once can be bonded many times under the same bonding conditions. The semiconductor element can be bonded to the substrate. Further, since the bonding portion is a metal bonding, heat of the semiconductor element can be efficiently radiated.
  • the integration density with respect to the installation area of the semiconductor device can be increased.
  • semiconductor devices with different functions selected according to the required specifications are arranged in the length direction or width direction of the semiconductor device and solid-phase bonded on the substrate, so that they can be individually designed. Compatible semiconductor devices can be manufactured in a short time.
  • solid-state bonding of an optical element and an optical waveguide to a substrate via a metal thin film allows a high-performance optical semiconductor device to be manufactured in a short time.
  • a gallium arsenide semiconductor device is interposed on a silicon semiconductor device via a metal thin film.
  • a highly accurate optical transmission semiconductor device can be manufactured.
  • the peel strength of the metal thin film from the semiconductor element can be increased.
  • a plurality of metal thin films are formed electrically independently on the bonding surface of the semiconductor element and part or all of the formed metal thin films are used as electrodes, wiring between the semiconductor elements is unnecessary. Therefore, labor saving of wiring work can be achieved. Further, since the wiring length is shortest, the operation speed of the semiconductor device can be increased.
  • FIG. 1 is an external view of a stacked semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a method of manufacturing a stacked semiconductor device according to a first embodiment of the present invention.
  • FIG. 3 is a metal cross-sectional view of a bonding interface according to the first embodiment of the present invention.
  • FIG. 4 is an external view of a planar junction type semiconductor device according to a first embodiment of the present invention.
  • FIG. 5 is a diagram illustrating a method of manufacturing an optical transmission semiconductor device according to a second embodiment of the present invention.
  • FIG. 6 is a diagram showing a method for manufacturing an optical semiconductor device according to a third embodiment of the present invention.
  • FIG. 7 is a diagram showing a defect repair method for a large-scale semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 8 is a diagram showing a relationship between bonding conditions and bonding strength of the present invention.
  • Fig. 1 shows the appearance of the stacked semiconductor device.
  • 4 11 1 is the gate of the transistor
  • 4 12 is the gate oxide film of the transistor
  • 4 4 is the wiring
  • 4 7 1 is the upper electrode
  • 7 2 is the lower electrode
  • 4 7 3 is the substrate electrode
  • Reference numerals 481 and 82 denote metal thin films
  • 46 denotes a conductive film
  • 404 denotes a substrate
  • 410, 402, and 403 denote semiconductor elements for stacking and bonding.
  • FIG. 2 shows a method of manufacturing a stacked semiconductor device.
  • 49 is an argon (Ar) atomic beam.
  • FIG. 3 shows a metal cross section at the bonding interface.
  • 21 is a gold thin film
  • 22 is twin deformation
  • 23 is a bonding interface
  • 24 is a void.
  • Fig. 4 shows the appearance of a planar junction type semiconductor device.
  • Reference numeral 61 denotes a substrate
  • reference numerals 61 to 606 denote semiconductor elements for planar bonding
  • reference numerals 631 and 632 denote metal thin films.
  • the stacked semiconductor device is a semiconductor device in which a plurality of stacked junction semiconductor elements shown in FIG. 1 (a) are stacked as shown in FIG. 1 (b), and which achieves high density and multifunctionality.
  • the transistor is manufactured by forming a gate 411 gate oxide film 412 and the like using a normal semiconductor process.
  • the transistors are isolated from each other by a front insulating layer 421, a rear insulating layer 42, and an inter-element insulating film 43, and both ends of the single-crystal silicon film 43 of each transistor.
  • Wirings 44 are respectively connected to the source and drain 432 formed at the bottom.
  • the wiring 44 is connected to the upper electrode 471 via a conductive film 46 filled in a surface through hole 451 formed on the surface insulating layer 421.
  • the wiring 44 is connected to the lower electrode 472 via a conductive film 46 filling the rear through hole 452 formed in the rear insulating layer 42.
  • the upper electrode 471 and the lower electrode 472 have a thickness of 0. ⁇
  • Ti titanium
  • Au gold
  • the thickness range of the titanium (Ti) thin film is set to 0.5 to 100 nm is that, in this range, the titanium (Ti) forms a thin film and the titanium (Ti) thin film is formed. This is because there is no decrease in peel strength due to internal stress and sufficient bonding strength is exhibited.
  • the reason why the thickness range of the gold (Au) thin film is set to 2 to 1000 ⁇ is that within this range, the surface roughness of the silicon where the gold (Au) thin film is the bonding surface can be covered.
  • the workability of providing a gold (Au) thin film is good and the strength is sufficient.
  • the gold (Au) thin film was inserted on the titanium (Ti) thin film in order to increase the peel strength of the gold (Au) thin film, and instead of titanium, the peel strength of a thin gold film such as chromium (Cr) was used. May be inserted.
  • the wiring can be omitted by using the bonding surface as an electrode, so that it is possible to save the labor of the semiconductor manufacturing process and improve the operation speed of the semiconductor device.
  • a titanium (Ti) thin film having a thickness of 0.5 to 100 nm as a metal thin film 481, and then a gold (Au) thin film as a metal thin film 481 are provided on the surface of the surface insulating layer 421 for fixing the device.
  • a thickness of 2 to 1000 nm is formed, and a similar metal thin film 482 is formed also on the surface of the backside insulating layer 422, each having a gold (Au) surface as a bonding surface. I have.
  • the joining step will be described.
  • Figure 4 urchin by showing (a), the Arugo emissions (Ar) atomic bi chromatography beam 4 9 pressure under that can by irradiation morphism (eg if 1 X 1 0 one 4 ⁇ 1 X 1 0- 3 Torr).
  • the first stacked junction semiconductor element 401 is placed below and the second stacked junction semiconductor element 402 is placed above, and the front side of the first stacked junction semiconductor element 401 is placed in a vacuum.
  • the bonding surface and the bonding surface on the back side of the second stacked bonding semiconductor element 402 are irradiated with an argon (Ar) atomic beam 49.
  • Ar argon
  • the bonding surfaces are opposed to each other in a vacuum of 5 ⁇ 10 to 16 Torr or less, and then bonded together in a solid state.
  • the bonding time of the pressure not be a vacuum below 5 X 1 0- 6 Torr, argon (Ar) atoms beam 4
  • Any atmosphere may be used as long as the bonding surface irradiated with 9 does not recontaminate.
  • the third stack of FIG. 4 (c) to I shown urchin, argon (Ar) atoms beam 4 under a pressure 9 can be irradiated (e.g., 1 x 1 0- 4 ⁇ 1 x 1 0- 3 Torr of vacuum)
  • the argon (Ar) atomic beam 49 is irradiated to the front-side bonding surface of the semiconductor device 401 for use and the rear-side bonding surface of the third stacked bonding semiconductor device 400 3.
  • any atmosphere may be used as long as the bonding surface irradiated with 9 does not recontaminate.
  • the temperature of the joining surface that is, the joining temperature is 100 to 400, and the joining pressure is 5 to 50 MPa.
  • the oxide film (Si02) of the surface insulating layer 421 is used as a eutectic film between silicon (Si) as a base material and gold (Au) of a metal thin film.
  • the melting temperature of the joint can be set to 600 T or more. Since this temperature is sufficiently higher than the joining temperature of 100 to 400 ° C., the joined portion does not melt even if the joining is performed several times.
  • the eutectic protection In this embodiment, the oxide film of the soI wafer itself is used as the stop film, but the same effect can be obtained by using a thermal oxide film or an oxide film formed by CVD. Also, under the conditions of the bonding temperature and the bonding pressure, as shown in FIG.
  • twin deformation 22 occurs in the gold (Au) thin film 21 which is a metal thin film, so that the bonding surfaces are bonded to each other.
  • bonding with few voids 24 at the bonding interface 23 can be performed.
  • the strength of the joint is equal to or more than l OM pa, which is sufficient for the soldering of the semiconductor device manufacturing process.
  • FIG. 4 shows that semiconductor elements 600 1 to 600 are arranged in a plane on a substrate 610 and joined according to the present invention.
  • semiconductor elements 600 1 to 600 are arranged in a plane on a substrate 610 and joined according to the present invention.
  • a semiconductor device that has been conventionally designed according to individual specifications can be manufactured in a short time. Can be manufactured.
  • FIG. 5 shows a junction in an optical transmission semiconductor device.
  • 51 is a silicon substrate
  • 52 is an optical waveguide
  • 53 is an optical semiconductor element
  • 54 is an optical fiber
  • 515 to 554 are metal thin films.
  • the optical transmission semiconductor device has an optical waveguide 52, an optical semiconductor element 53 fixed on a silicon (Si) substrate 51, and an optical fiber 54 attached. It has a structure.
  • the optical waveguide 52, the optical semiconductor element 53, and the optical fiber 54 cannot exhibit their performance unless their mounting accuracy is high.
  • a titanium (Ti) thin film was formed to a thickness of 0.5 to 100 nm by vacuum evaporation as metal thin films 551, 552, and then Money (Au)
  • the optical element 53 formed with 54 is placed under a pressure (for example, a vacuum of 1 xl O— 4 to 1 xl O— 3 Torr) under which the argon (Ar) atom beam 56 can irradiate, and Irradiate an argon (Ar) atomic beam 56.
  • the bonding surfaces of the silicon substrate 51 and the optical element 53 are brought into close contact with each other and bonded in a solid state.
  • the temperature of the bonding surface that is, the bonding temperature is 100 to 400C
  • the bonding pressure is 5 to 50 MPa.
  • the optical semiconductor element 53 and the optical waveguide 52 are joined according to the present invention, the only member that may cause a dimensional error due to the joining is the metal thin film. If it is correct, the position after joining can be set correctly.
  • FIG. 6 shows the manufacturing process of the optical semiconductor device.
  • 31 is a silicon semiconductor device
  • 32 is a gallium arsenide semiconductor device
  • 34 is argon (Ar) Atomic beam
  • 331 and 332 are metal thin films.
  • Optical semiconductor devices consist of silicon (Si) semiconductor devices and gallium arsenide.
  • GaAs GaAs It can be manufactured by joining different materials of semiconductor elements.
  • a titanium (Ti) thin film is formed to a thickness of 0.5 to 100 nm by vacuum evaporation and then a gold (Au) thin film as a metal thin film 331.
  • the joint surface irradiated with 4 does not recontaminate the surface.
  • the temperature of the joining surface that is, the joining temperature is 100 to 400, and the joining pressure is 5 to 50 MPa.
  • the height of the silicon semiconductor device 31 and the height of the gallium arsenide semiconductor device 32 can be made the same. Since the wiring between them can be made of thin-film metal wiring, the wiring density is increased, and high integration of semiconductor devices becomes possible. In addition, by using a part of the joint surface as a contact point, it is possible to save labor in wiring work.
  • FIG. 7 shows a method for repairing a defect in a large-scale semiconductor device.
  • 11 is a large-scale semiconductor device
  • 13 is a junction groove
  • 15 is a thin-film large-scale semiconductor device
  • 16 is an argon (Ar) atomic beam
  • 121, 122 are macro
  • 123 are defects
  • the relief macro, 141 and 142 are metal thin films.
  • defects are remedied to improve yield. This is to remove the defective macro from the circuit blocks that have individual functions called macros that make up a large-scale semiconductor device, and join macros without defects to them. The task is to rescue large-scale semiconductor devices that have become defective.
  • FIG. 7 (a) shows a large-scale semiconductor device requiring defect relief.
  • Large-scale semiconductor devices 11 made from SOI wafers are composed of circuit blocks with individual functions called macros 121 and 122. For example, it is assumed that there is no defect in the circuit of the macro mouth 1221, and that the circuit of the macro 122 has a defect.
  • the defect removing step will be described.
  • the macro 122 having this defect is removed by etching to form a junction groove 13 as shown in FIG. 1 (b).
  • a titanium (Ti) thin film having a thickness of 0.5 to 1000 nm is formed in the joining groove 13 as a metal thin film 141 by vacuum evaporation, and then a gold thin film is formed.
  • Ti titanium
  • Au gold
  • a thin film is formed with a thickness of 2 to 1000 ⁇ , and the gold surface is used as a bonding surface.
  • the reason why the titanium thin film is inserted between the bonding groove 13 and the gold thin film is to increase the peel strength of the gold thin film.
  • a thin film such as chromium (Cr) that increases the peel strength of the gold thin film is used. May be inserted.
  • the thin-film large-scale semiconductor element 15 shown in Fig. 1 is a thin-film version of a large-scale semiconductor element having a circuit configuration similar to that of the large-scale semiconductor element 11, and is the same as the macro-122. No defect has occurred in the defect repair macro 123.
  • Fig. 1 ( e ) As shown in (5), the thin-film large-scale semiconductor device 15 is divided into macro units, and the defect relief macros 123 are extracted. Then, as shown in FIG. 1 (f), a metal thin film 142 is formed in the same manner as the bonding groove 13 and the gold (Au) surface is used as the bonding surface.
  • the joining step will be described with reference to FIG.
  • a large semiconductor element 1 1 and remedies macros 1 2 3 argon (Ar) atoms beam 1 6 under pressure that can be irradiated (1 x 1 0 one 3 Torr of vacuum example 1 x 1 0- 4 ⁇ )
  • the joint surface is irradiated with an argon (Ar) atomic beam 16.
  • contaminants such as an oxide film, moisture, oils and fats adhering to the joint surface are removed, and the joint surface is activated.
  • the surface irradiated with the argon (Ar) atomic beam 16 is a metal surface, the irradiated surface does not charge up and does not damage the semiconductor device electrically. Thereafter, Remind as in FIG.
  • the adhesion is allowed after being opposed joint surfaces each other at 5 X 1 0- 6 To rr in the following vacuum bonding state of the solid phase.
  • the bonding time of the pressure not be a vacuum below 5 x 1 0- 6 Torr, the bonding surface was irradiated with argon (Ar) atoms beam 1 6 may be any atmosphere that does not re-contamination.
  • the temperature of the bonding surface that is, the bonding temperature is 100 to 400, and the bonding pressure is 5 to 50 MPa. Since bonding can be performed at a low temperature and a low pressure in this manner, bonding can be performed while ensuring the reliability of the integrated circuit.
  • the dimensional accuracy is high, and the height of the relief macro 123 and the height of the defect-free macro 122 can be the same.
  • the wiring between the macros is thin-film like the non-defective large-scale semiconductor device. Since the wiring can be formed using metal wiring, the wiring density can be increased, and high integration of semiconductor devices can be achieved. Also, since the joint is a metal joint, the relief macros 123 can sufficiently dissipate heat.
  • the oxide film (Si02) in the joint groove 13 and the relief macro 123 Is used as an anti-eutectic film between silicon (Si), which is the base material of the large-scale semiconductor element 11 and the defect relief macro 123, and gold (Au) as a metal thin film.
  • the melting temperature of the joint can be raised to 600 ° C. or higher. Since this temperature is sufficiently higher than the joining temperature of 100 to 400 ° C., the joined portion does not melt even if this joining is performed several times.
  • the oxide film of the SOI wafer itself is used as the eutectic prevention film. However, the same effect is obtained with a thermal oxide film or an oxide film formed by CVD.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention a trait à un dispositif à semi-conducteurs dont la densité d'intégration est élevée et qui présente de nombreuses fonctions. On fabrique ce dispositif en assemblant les éléments semi-conducteurs les uns avec les autres par soudage en phase solide dans des couches métalliques minces. L'assemblage des éléments semi-conducteurs selon le procédé de l'invention au lieu de les assembler de manière classique au moyen d'un adhésif ou d'une soudure, permet d'améliorer les caractéristiques de résistance et de rayonnement calorifique ainsi que la précision dimensionnelle du raccord et de diminuer la longueur de câblage, sinon de la supprimer. On empile les éléments semi-conducteurs au moyen de ce procédé d'assemblage, produisant, de la sorte, un dispositif à semi-conducteurs à densité élevée exécutant très rapidement des opérations de calcul et se révélant, de surcroît, des plus fiable.
PCT/JP1995/001875 1995-09-20 1995-09-20 Dispositif a semi-conducteurs et son procede de fabrication WO1997011492A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP1995/001875 WO1997011492A1 (fr) 1995-09-20 1995-09-20 Dispositif a semi-conducteurs et son procede de fabrication
JP51256397A JP3400459B2 (ja) 1995-09-20 1995-09-20 半導体デバイスおよび製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1995/001875 WO1997011492A1 (fr) 1995-09-20 1995-09-20 Dispositif a semi-conducteurs et son procede de fabrication

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WO1997011492A1 true WO1997011492A1 (fr) 1997-03-27

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999057765A1 (fr) * 1998-05-05 1999-11-11 Dense-Pac Microsystems, Inc. Empilement de puces et son procede de production
JP3447690B2 (ja) 2000-12-04 2003-09-16 日本電気株式会社 半導体チップの積層実装方法
JP2008198263A (ja) * 2007-02-09 2008-08-28 Konica Minolta Opto Inc 近接場光発生器、光アシスト式磁気記録ヘッド、光アシスト式磁気記録装置
JP2008302370A (ja) * 2007-06-05 2008-12-18 Panasonic Corp 接合方法
US7489030B2 (en) 2005-12-08 2009-02-10 Elpida Memory, Inc. Stacked semiconductor device
JP2012124497A (ja) * 2011-12-26 2012-06-28 Hitachi Metals Ltd 半導体装置
WO2012087364A1 (fr) * 2010-12-20 2012-06-28 Tessera, Inc. Liaison de tranche et jonction d'interconnexion simultanées
JP2014517545A (ja) * 2011-06-17 2014-07-17 インテル コーポレイション マイクロエレクトロニクスダイ、当該ダイを含む積層ダイ及びコンピュータシステム、当該ダイ内に多チャネル通信路を製造する方法、並びに、積層ダイパッケージの部品間での電気通信を可能にする方法
US9359480B2 (en) 2009-04-06 2016-06-07 Entegris, Inc. Non-dewetting porous membranes

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JPH0362566A (ja) * 1989-01-17 1991-03-18 Texas Instr Inc <Ti> デカップリングコンデンサを備えた集積回路パッケージ
JPH03171643A (ja) * 1989-11-29 1991-07-25 Hitachi Ltd 半導体集積回路装置の製造方法および製造装置
JPH0456262A (ja) * 1990-06-25 1992-02-24 Matsushita Electron Corp 半導体集積回路装置
JPH04148525A (ja) * 1990-10-12 1992-05-21 Fujitsu Ltd Ｓｏｉ基板およびその製造方法
JPH05109593A (ja) * 1991-10-14 1993-04-30 Fuji Electric Co Ltd 半導体装置の製造方法

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JPH0362566A (ja) * 1989-01-17 1991-03-18 Texas Instr Inc <Ti> デカップリングコンデンサを備えた集積回路パッケージ
JPH03171643A (ja) * 1989-11-29 1991-07-25 Hitachi Ltd 半導体集積回路装置の製造方法および製造装置
JPH0456262A (ja) * 1990-06-25 1992-02-24 Matsushita Electron Corp 半導体集積回路装置
JPH04148525A (ja) * 1990-10-12 1992-05-21 Fujitsu Ltd Ｓｏｉ基板およびその製造方法
JPH05109593A (ja) * 1991-10-14 1993-04-30 Fuji Electric Co Ltd 半導体装置の製造方法

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999057765A1 (fr) * 1998-05-05 1999-11-11 Dense-Pac Microsystems, Inc. Empilement de puces et son procede de production
JP3447690B2 (ja) 2000-12-04 2003-09-16 日本電気株式会社 半導体チップの積層実装方法
US6803253B2 (en) 2000-12-04 2004-10-12 Nec Corporation Method for laminating and mounting semiconductor chip
US7489030B2 (en) 2005-12-08 2009-02-10 Elpida Memory, Inc. Stacked semiconductor device
JP2008198263A (ja) * 2007-02-09 2008-08-28 Konica Minolta Opto Inc 近接場光発生器、光アシスト式磁気記録ヘッド、光アシスト式磁気記録装置
JP2008302370A (ja) * 2007-06-05 2008-12-18 Panasonic Corp 接合方法
US10179842B2 (en) 2009-04-06 2019-01-15 Entegris, Inc. Non-dewetting porous membranes
US9359480B2 (en) 2009-04-06 2016-06-07 Entegris, Inc. Non-dewetting porous membranes
CN103370784A (zh) * 2010-12-20 2013-10-23 德塞拉股份有限公司 同时的晶圆结合及互连接合
US8486758B2 (en) 2010-12-20 2013-07-16 Tessera, Inc. Simultaneous wafer bonding and interconnect joining
US8709913B2 (en) 2010-12-20 2014-04-29 Tessera, Inc. Simultaneous wafer bonding and interconnect joining
WO2012087364A1 (fr) * 2010-12-20 2012-06-28 Tessera, Inc. Liaison de tranche et jonction d'interconnexion simultanées
CN103370784B (zh) * 2010-12-20 2016-08-24 德塞拉股份有限公司 同时的晶圆结合及互连接合
JP2014517545A (ja) * 2011-06-17 2014-07-17 インテル コーポレイション マイクロエレクトロニクスダイ、当該ダイを含む積層ダイ及びコンピュータシステム、当該ダイ内に多チャネル通信路を製造する方法、並びに、積層ダイパッケージの部品間での電気通信を可能にする方法
JP2012124497A (ja) * 2011-12-26 2012-06-28 Hitachi Metals Ltd 半導体装置

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