[go: up one dir, main page]

WO1997014220A3 - Electrically reprogrammable, reduced power, programmable logic device circuit - Google Patents

Electrically reprogrammable, reduced power, programmable logic device circuit Download PDF

Info

Publication number
WO1997014220A3
WO1997014220A3 PCT/IB1996/001041 IB9601041W WO9714220A3 WO 1997014220 A3 WO1997014220 A3 WO 1997014220A3 IB 9601041 W IB9601041 W IB 9601041W WO 9714220 A3 WO9714220 A3 WO 9714220A3
Authority
WO
WIPO (PCT)
Prior art keywords
gates
arrays
programmable logic
logic device
reduced power
Prior art date
Application number
PCT/IB1996/001041
Other languages
French (fr)
Other versions
WO1997014220A2 (en
Inventor
Ronald L Cline
Original Assignee
Philips Electronics Nv
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics Nv, Philips Norden Ab filed Critical Philips Electronics Nv
Publication of WO1997014220A2 publication Critical patent/WO1997014220A2/en
Publication of WO1997014220A3 publication Critical patent/WO1997014220A3/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1735Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

Large multi-input CMOS logic gates may be formed by a sequence of alternating CMOS NAND and NOR logic gates. The sequence of alternating gates may be compactly laid out in an integrated circuit to form arrays of functional AND or OR gates useful in PLAS. These arrays of CMOS gates consume low power and have response times suitable for integrated circuits. These arrays may be programmed by EEPROM or EPROM transistors or in the alternative, binary latches may be used to store information determinative of the desired programming.
PCT/IB1996/001041 1995-10-13 1996-10-03 Electrically reprogrammable, reduced power, programmable logic device circuit WO1997014220A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54324795A 1995-10-13 1995-10-13
US08/543,247 1995-10-13

Publications (2)

Publication Number Publication Date
WO1997014220A2 WO1997014220A2 (en) 1997-04-17
WO1997014220A3 true WO1997014220A3 (en) 1997-05-09

Family

ID=24167202

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1996/001041 WO1997014220A2 (en) 1995-10-13 1996-10-03 Electrically reprogrammable, reduced power, programmable logic device circuit

Country Status (1)

Country Link
WO (1) WO1997014220A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424567B1 (en) 1999-07-07 2002-07-23 Philips Electronics North America Corporation Fast reconfigurable programmable device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4636661A (en) * 1984-12-21 1987-01-13 Signetics Corporation Ratioless FET programmable logic array
US4652777A (en) * 1984-12-18 1987-03-24 Cline Ronald L CMOS programmable logic array
US5270587A (en) * 1992-01-06 1993-12-14 Micron Technology, Inc. CMOS logic cell for high-speed, zero-power programmable array logic devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4652777A (en) * 1984-12-18 1987-03-24 Cline Ronald L CMOS programmable logic array
US4636661A (en) * 1984-12-21 1987-01-13 Signetics Corporation Ratioless FET programmable logic array
US5270587A (en) * 1992-01-06 1993-12-14 Micron Technology, Inc. CMOS logic cell for high-speed, zero-power programmable array logic devices

Also Published As

Publication number Publication date
WO1997014220A2 (en) 1997-04-17

Similar Documents

Publication Publication Date Title
GB8828828D0 (en) Semiconductor integrated circuit
US6373771B1 (en) Integrated fuse latch and shift register for efficient programming and fuse readout
US6150837A (en) Enhanced field programmable gate array
US9087169B2 (en) Automated metal pattern generation for integrated circuits
CA2038162C (en) Programmable connector
US20070210826A1 (en) Programmable logic devices comprising time multiplexed programmable interconnect
EP0415542A3 (en) Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
DE69737731D1 (en) Integrated circuit with adaptive input / output gate
EP0961290A3 (en) Flash memory with improved erasability and its circuitry
US20070052444A1 (en) Programmable interconnect structures
EP0663669A3 (en) Improvements in or relating to fuse and antifuse link structures for integrated circuits
WO2005034175A3 (en) Programmable system on a chip
US5016217A (en) Logic cell array using CMOS EPROM cells having reduced chip surface area
KR960008823B1 (en) Non-volatile semiconductor memory device
AU6408096A (en) Nonvolatile reprogrammable interconnect cell with fn tunneling and programming method thereof
GB2289964B (en) Programmable logic array integrated circuits
EP0818891A3 (en) Programmable logic arrays
EP0905904A3 (en) Semiconductor integrated circuit having tri-state logic gate circuit
EP0863472A3 (en) Semiconductor integrated circuit with two supply voltage levels
JPH05276007A (en) Integrated circuit device
DE69632271T2 (en) INTEGRATED MEMORY CIRCUIT ARRANGEMENT WITH LOGIC CIRCUIT COMPATIBLE STRUCTURE
US7336097B2 (en) Look-up table structure with embedded carry logic
WO1988000372A1 (en) One-time programmable data security system for programmable logic device
JPH0241211B2 (en)
WO2005098865A3 (en) Rewriteable electronic fuses

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

AK Designated states

Kind code of ref document: A3

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase