WO1997016003A1

WO1997016003A1 - Security chip

Info

Publication number: WO1997016003A1
Application number: PCT/DE1996/001813
Authority: WO
Inventors: Günther EBERHARD; Jürgen GESSNER; Wolf-Dietrich Moeller; Manfred Schäfer
Original assignee: Siemens Aktiengesellschaft
Priority date: 1995-10-25
Filing date: 1996-09-25
Publication date: 1997-05-01
Also published as: JPH11513864A; DE19539700C1; EP0857382A1; RU2180987C2; UA46064C2

Abstract

The invention relates to a security chip (SC) which is disconnected from application hardware (AHW) and only connected to the application hardware (AHW) by way of a data interface (DS) and a command interface (BS). The security chip (SC) has its own processor (P) and a plurality (VZ) of independent algorithm modules (AMi) for carrying out symmetric encryption algorithms (SV) and/ or asymmetric encryption algorithms (AV), all components of the security chip (SC) being connected via a bus (IB) inside the chip. The methods for encryption management and for cryptographic user data processing are carried out together on the security chip (SC), and consequently the security features of said chip (SC) are considerably improved in relation to known arrangements.

Description

description

Security chip

To maintain the security of communication relationships, for example data communication or voice communication, cryptographic algorithms are used to encrypt the actual communication data. Various algorithms are used, for example, to ensure the integrity, confidentiality or authenticity of the transmitted data or the communication partner.

Security chips are therefore required which carry out the cryptographic methods and protocols for a wide variety of information technology applications.

Special security modules designed for individual applications are known, for example a security module for secure fax transmissions (Siemens, data security module DSM-Fax, secure fax transmissions, Siemens area security technology) or also for encryption of telephone conversations (Siemens, DSM -Voice-Telephoning in Confidence, Sie¬ mens area security technology; Luis Cypher, LC-1 The digital voice encryptor for tap-proof telephone calls).

Furthermore, special chip card controllers and coprocessors developed for asymmetric crypto-algorithms are known (IS-Aktuell, Products / Systems, pp. 7-17 to 7-18, April 1993, 1993).

Other security chips are known in which either the symmetrical crypto-algorithm is carried out with hardware support, but the asymmetrical crypto-algorithm is only supported by the software, or vice versa (L. Gold¬berg, New Encryption strategy uses hardware and software to protect data on public networks, Electronic Design, pp. 39-40, March 1995; G. Eberhard, Two new crypto products from Siemens: the SLE44C200 chip card controller and the SLE44CP2 coprocessor, processors for asymmetric algorithms, IS-Aktuell, pp. 7-17 - 7-18, April 1993).

These known security modules have the disadvantage that they are only limited to very specific applications. Above all, either only an asymmetrical algorithm, both of which run directly with hardware support, is provided for data encryption on a single security chip, or only symmetrical data encryption on a chip.

This limitation leads to a further disadvantage of the previous solutions that security-critical information in a computing unit carrying out the encryption algorithms is sometimes still transmitted via an unsecured bus of the computing unit, for example in the case of key management of cryptographic keys and the transmission of user data and thus can be intercepted by an attacker.

The invention is therefore based on the problem of specifying a security chip which avoids the disadvantages mentioned above.

The problem is solved by the security chip according to patent claim 1.

The security chip is completely decoupled from the application hardware and can only be “addressed” via a data interface and a command interface. Because the security chip also has its own processor, an on-chip bus to which the application hardware cannot access, and different algorithm modules which the most diverse security services based on asymmetrical and symmetrical algorithms perform, is the security universally applicable and does not provide any security-relevant information to the application hardware.

As a result, the application hardware and the application software could be loaded, configured and adapted as desired without endangering the security of the various crypto functions that are carried out with the algorithm modules.

The further development of the security chip in accordance with patent claim 5 makes it possible to detect attacks on the security chip and also possibly react to them, for example, by deleting all the data.

The development of the security chip according to claim 6 implements an extension of the algorithm modules by additional security services and thus extends the applicability of the security chip.

Further developments of the invention result from the dependent claims.

A preferred exemplary embodiment of the invention is shown in the drawings and is described in more detail below.

Show it

Figure 1 is a sketch describing a possible arrangement of the security chip;

FIG. 2 shows a block diagram describing possible algorithm modules;

FIG. 3 shows an arrangement which represents the construction of a safe timer module. The invention is explained further with reference to FIGS. 1 to 3.

An arrangement of a security chip SC is shown in FIG.

The security chip SC has at least the following components:

a processor P,

a large number of VZ of independent algorithm modules AMi for performing encryption algorithms,

a memory SP,

a data interface DS which is independent of the performance of the processor P,

a secure command interface BS which is either led into a chip-internal data bus DB or directly into the processor P,

the chip-internal data bus DB, via which the plurality VZ of independent algorithm modules AMi is coupled to the data interface DS, and

- An on-chip bus IB, with which all components are coupled except for the data interface DS.

By decoupling the data interface DS from the chip internal bus IB, the encryption performance is no longer dependent on the processor P. In addition, the chip internal data from the chip internal bus IB cannot be intercepted by an unauthorized third party, in particular at the data interface DS or manipulated.

Furthermore, the security chip SC can have the following components:

- a timer module ZM,

- A sensor module SM and

- an actuator module AKM. These components are also coupled to the bus IB inside the chip.

A wide variety of communication protocols can be used for communication between the individual components, that is to say for sequence control, of course independently of the communication protocol used by an application hardware AHW.

The data interface DS and the command interface BS are the only access points for the application hardware AHW on the security chip SC.

In another way, the application hardware AHW has no possibility of accessing the security chip SC and thus also the security-relevant data that are used and / or stored in the security chip SC.

By decoupling the security chip SC from it

"Outside world" it is no longer possible for an unauthorized third party, that is to say an attacker, to receive security-relevant data of any kind from the security chip SC.

The processor P can be any processor with a suitable speed which results directly from the requirements of the planned application.

The algorithm modules AMi are independent modules, each of which is “responsible” for a cryptographic protocol or method. These include, for example, methods or protocols for the encryption and decryption of user data, for integrity protection, or for digital signature (signature) or hash value formation. The index i uniquely identifies each algorithm module AMi. It is any natural number in the range from 1 to n. Here n is the number of different Algorithm modules AMi implemented on the security chip SC.

Possible exemplary embodiments for the algorithm modules AMi are explained below.

An algorithm module AMi is, for example, a module that is specifically designed to carry out a cryptographic symmetrical method SV, for example the data description standard method (DES method). The module can also be designed such that it can carry out the DES process with different key lengths, for example also the triple DES process. Experienced further symmetrical cryptographic methods SV can be implemented in further algorithm modules AMi.

In a further exemplary embodiment, it is provided that asymmetrical cryptographic algorithms AV are also carried out in the algorithm modules AMi. Examples of asymmetric cryptographic algorithms AV are well known to any person skilled in the art, for example the RSA method.

These symmetrical encryption algorithms SV and asymmetrical cryptographic algorithms AV described above can be provided both separately and together in different algorithm modules AMi on the security chip SC.

Several algorithm modules AMi of the same type can also be provided on the security chip SC to carry out the same method, for example to increase the performance of the security chip SC. This can e.g. For example, it can also be provided in a way that an algorithm module AMi for processing an incoming data stream and another algorithm module AMi of the same design for processing an outgoing data stream is provided. The algorithm modules AMi are used, among other things, for the encryption of user data, which are placed in plain text by the application hardware AHW on a chip-internal data bus DB via the data interface DS and with any encryption method defined by the application hardware AHW via the command interface BS that the algorithm module AMi used is selected from the plurality VZ of the independent algorithm modules AMi are encrypted.

The user data encrypted in the respective algorithm module AMi are again transmitted to the application hardware AHW via the chip-internal data bus DB and the data interface DS, now in encrypted form.

The parameters of the respective encryption request for the user data are made known to the security chip SC by the application hardware AHW via the command interface BS. This can be, for example, the encryption algorithm to be used, the key length, or similar parameters that are necessary for the encryption of user data. Furthermore, the method, ie for example encryption of user data, is started by the application hardware AHW via the command interface BS.

The processor P controls the administrative processes for encrypting data in the security chip SC and also cryptographic protocols described below.

However, the processor P does not necessarily transport the encrypted, decrypted or processed with cryptographic methods user data. If not transported by the processor P, these are usually transported via the on-chip data bus DB and, which leads to a further advantage of the security chip SC, that the encryption performance SC is not dependent on the processor P. In addition, the decoupling of the chip-internal data bus DS from the chip-internal bus IB ensures that the internal data which are transported via the chip-internal bus IB are not listened to or manipulated at the data interface DS.

This leads to a significant improvement in the security properties of the security chip SC compared to known security modules, since security-relevant data, such as cryptographic keys used for encryption, can no longer be intercepted by unauthorized persons.

Both unencrypted data and data that have to be buffered in order to carry out cryptographic algorithms are stored in the memory SP, for example intermediate keys in methods that work on the principle of exponential key exchange or intermediate keys that are used in the DES method be used, .

Additional algorithm modules AMi can be provided to carry out different security services, for example from known authentication protocols, or also to carry out methods for key exchange or for key generation of cryptographic keys.

The sensor module SM detects physical attacks on the security chip SC, possibly evaluates them and reports them to the processor P via the chip-internal bus IB.

On the instruction of the processor P, steps are carried out in the actuator module AKM to ward off attacks detected by the sensor module SM. These security measures can be, for example, the deletion of all data stored in the memory SP at the time. The ZM timer module has at least the following components:

a timer interface SIO, a timer controller ZC,

a counting circuit ZS, the counting circuit ZS having at least:

a data buffer DB,

- a real time counter RZ, - a clock adjustment TA, and

- A counter switch CLOSE.

The ZM timer module carries out autonomous tasks, for example to provide time stamps. The time stamps are made available to other applications of the SC security chip via the ZIO timer interface.

The timer controller ZC controls the processes of the timer module ZM.

The timer interface ZIO represents the bus interface of the timer module ZM to the on-chip bus IB. The timer interface ZIO is primarily required to handle communication with external controllers, in the case of the security chip SC with the processor P.

Connections are therefore provided to control the sequence of the cryptographic communication protocol, that is to say to control communication with other controllers, that is to say with the processor P. Furthermore, a connection is provided via which the timer module ZM attempts to tamper with the sensor module SM, be reported, e.g. B. manipulations on the clock. Additional connections are provided for exchanging the data of the timer module ZM, that is to say an absolute or relative time which is determined by the timer module ZM. No crypto-algorithms are carried out in the timer module ZM itself. The other modules of the security chip SC are responsible for handling authentication protocols and other security functions. The processor P must decide and monitor who is allowed to access the timer module ZM in what way via the timer interface ZIO.

The timer controller ZC controls the timer interface ZIO and the counter circuit ZS. In addition, the timer controller ZC receives logic commands from the processor P via the timer interface ZIO.

The logic commands of the processor P are interpreted by the timer controller ZC and implemented in the internal control of the timer module ZM. The timer controller ZC thus monitors the functional sequence of the entire module. It thus represents the control unit of the timer module. Commands with which the timer controller ZC influences the sequence of the timer module ZM can include the following functions, for example:

- Setting the time of the timer module ZM (date, time, synchronization mechanism); - Transfer of loaded clock parameters into the current clock function;

- Reading out the time of the timer module ZM;

- Setting calendar functions (monthly rhythm, taking leap years into account, taking summer time into account, etc.);

- Specifying clock reset functions, ie specifying whether a reset should take place at an ordered time or at any time;

- Starting and stopping the ZM timer module; Parameterizing the clock adaptation TA, that is to say defining the parameters which are required for the clock adaptation TA; - Parameterizing the resolution accuracy of the timer module, that is the setting whether the timer module ZM should measure the time in seconds, in milliseconds or in microseconds; - Parameterization of the transmission format of the time of the timer module ZM

- Reading out status information via the timer module ZM;

- Parameterizing the counting mode, ie whether binary or modulo is to be counted; - Switching a test mode for the timer module ZM on and off.

In addition, a data access control and a function access control are carried out by the timer controller ZC. In this context, this includes, for example:

- Access to the timer module ZM is only permitted after a secret number has been successfully checked; - Access is only allowed after successful authentication;

- Access is only permitted for reading;

- Access is only permitted in writing.

The counter circuit ZS of the timer module ZM has, as described in the previous, among other things the real time counter RZ.

The real-time counter RZ is a counting circuit that is made up of cascaded modulo counters. The cascading and synchronization of the real-time counter RZ can take into account the peculiarities of time jumps, for example caused by summer time or leap years, etc. For some cryptographic applications, a counting of the “relative” time, ie a monotone counting binary counter of sufficient length corresponding to the required time, is also provided. The clock adaptation TA is used to generate a suitable time base for the time measurement in the timer module ZM with an external clock supply, as is the case, for example, with chip cards customary today.

The data buffer DB is used to store data that is required in the timer module ZM.

It is furthermore advantageous if the algorithm modules AMi are designed in such a way that the key management is supported directly in hardware. This offers considerable performance advantages, especially in the case of rapid key changes between differently encrypted data streams. This is of particular importance in the area of packet-oriented telecommunications or data connections or in application sharing systems or multimedia applications, for example in a local area network (LAN) in which many packets are transmitted to different communication partners and processed differently by cryptography Need to become.

Claims

claims

1. Security chip (SC), in which the security chip (SC) is only coupled to an application hardware (AHW) via a data interface (DS) and a command interface (BS),

- in which a processor (P) is provided,

- in which a large number (VZ) of independent algorithm modules (AMi, i = l..n) for carrying out

Encryption algorithms are provided, the independent algorithm modules (AMi) being coupled to the processor (P) via an on-chip bus (IB) and being coupled to the data interface (DS) via an on-chip data bus (DB), and

- In which a memory (SP) is provided, which is coupled to the internal chip bus (IB).

2. Security chip (SC) according to claim 1, in which at least one algorithm module (AMi) of the plurality (VZ) of the Algorithmen¬ modules (AMi) is provided for performing symmetrical encryption algorithms (SV).

3. Security chip (SC) according to claim 1 or 2, in which at least one algorithm module (AMi) of the plurality (VZ) of the algorithm modules (AMi) is provided for performing asymmetrical encryption algorithms (AV).

4. Security chip (SC) according to one of claims 1 to 3, in which a timer module (ZM) is provided which determines and provides a reliable absolute time and / or a reliable relative time.

5. Security chip (SC) according to one of claims 1 to 4, in which a sensor module (SM) and / or an actuator module (AKM) is provided for detection and attacks on the security chip (SC) and / or for carrying out Security measures in the event of detected attacks on the security chip (SO.

6. Security chip (SC) according to one of claims 1 to 5, in which further modules are provided for carrying out further

Security services.

7. Security chip (SC) according to one of claims 1 to 6, in which the algorithm modules (AMi) are designed in such a way that key management is supported directly in hardware.