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WO1997039484A1 - Procede de fabrication d'une structure d'interconnexion faisant intervenir le laminage d'une membrane dielectrique poreuse - Google Patents

Procede de fabrication d'une structure d'interconnexion faisant intervenir le laminage d'une membrane dielectrique poreuse Download PDF

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Publication number
WO1997039484A1
WO1997039484A1 PCT/US1997/005555 US9705555W WO9739484A1 WO 1997039484 A1 WO1997039484 A1 WO 1997039484A1 US 9705555 W US9705555 W US 9705555W WO 9739484 A1 WO9739484 A1 WO 9739484A1
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WO
WIPO (PCT)
Prior art keywords
dielectric layer
dielectric
membrane
integrated circuit
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Prior art date
Application number
PCT/US1997/005555
Other languages
English (en)
Inventor
C. Thomas Rosenmayer
David B. Noddin
Original Assignee
W.L. Gore & Associates, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by W.L. Gore & Associates, Inc. filed Critical W.L. Gore & Associates, Inc.
Priority to AU24372/97A priority Critical patent/AU2437297A/en
Publication of WO1997039484A1 publication Critical patent/WO1997039484A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to the fabrication of semiconductor devices More particularly, an integrated circuit element, and method of manufacture, is provided wherein a low dielectric constant insulation layer is disposed on an integrated circuit structure using a planar, solvent free dielectric layer
  • Integrated circuits are created from a silicon wafer using various etching, doping and depositing steps that are well known in the art of fabricating integrated circuit devices.
  • a silicon wafer may be comprised of a number of integrated circuit dies that each represent a single integrated circuit chip Ultimately, the chip may be packaged by transfer molding a plastic encasement around the chip with a variety of pin-out or mounting and interconnection schemes.
  • An integrated circuit is comprised of many interconnected transistors and associated passive circuit elements that perform a function or functions These functions may be random access memory, central processing, communications, etc.
  • patterned conductive layers must be used to provide electrical interconnection between active and passive devices comprising the integrated circuit structure.
  • Many integrated circuits now contain multiple levels of metallization for interconnections.
  • the need to integrate more functions onto a chip has caused the semiconductor industry to search for ways to shrink, or scale, the size of individual transistors and other devices commonly integrated on a chip.
  • the shrinkage of sizes in such integrated circuit structures includes shrinkage of the horizontal spacing between adjacent conductors on the same plane.
  • Such shrinkage of feature size results in a corresponding rise in the impedance of the conductors, as well as an increase in capacitive coupling between conductors and the integrated circuit structure
  • capacitive coupling increases both RC delay and cross ⁇ talk, both of which reduce the speed at which the circuit may be operated
  • the capacitance between conductors of an integrated circuit structure is highly dependent on the insulator, or dielectric, used to separate them
  • Conventional semiconductor fabrication commonly employs silicone dioxide as a dielectric, which has a dielectric constant of about 3 9 '
  • the lowest possible, or ideal, dielectric constant is 1 0, which is the dielectric constant of a vacuum, whereas air has a dielectric constant of less than 1 001 Therefore, the amount of capacitance formed between adjacent lines, either horizontally or vertically, of an integrated circuit structure, may be reduced by reducing the impedance of the lines
  • This may be achieved by substituting a different insulation material having a lower dielectric constant, e g , using some insulation material other than the commonly used silicone dioxide (S ⁇ 0 2 ), or by somehow reducing the dielectric constant of the particular insulation mate ⁇ al being used, e.g , somehow reducing the dielectric constant of an S ⁇ 0 2 insulation layer
  • the ideal material would have a low dielectric constant, low thermal expansion, good physical properties such as high
  • a semiconductor device and method that forms air gaps between metal leads of an integrated circuit structure to provide a composite having a low-dielectric constant of about 1 25 thereby reducing the capacitive coupling between conductors in the integrated circuit structure
  • the method for forming air gaps between metal leads of a semiconductor device comprises the steps of depositing a metal layer on a substrate, etching the metal layer to form metal leads, depositing a disposable solid layer between the metal leads, depositing over the disposable solid layer and the metal leads a porous dielectric layer, and removing the disposable solid layer through the porous dielectric layer to form air gaps between the metal leads beneath the porous dielectric layer
  • an improved method for forming an integrated circuit structure wherein air gaps are formed between metal leads by using a planar, solvent free dielectric layer
  • an integrated circuit element comprising at least one base substrate, or multilayer base substrate, having an integrated electric circuit disposed thereon
  • the integrated electric circuit is covered by a planar dielectric layer
  • the dielectric layer is comprised of a porous polymer matrix layer which may contain within at least some of its pores or which may have disposed on a surface thereof as a coating, an additional dielectric mate ⁇ al
  • the additional dielectric material may also be contained within substantially all of the pores of the porous polymer matrix layer
  • the dielectric polymer coating may be disposed ad j acent the electric circuit
  • the plana ⁇ ty of the applied dielectric layer is less than 200 nm over 2 0 mm
  • the dielectric layer has a dielectric constant of less than 3 9, and may have a dielectric constant of less than 2 0
  • the dielectric layer has a thickness of 5 micrometers, or less, and may have a thickness of 2 0 micrometers, or less
  • a multiple layer integrated circuit comprising a p'urality of integrated circuit elements bonded together
  • the dielectric layer is comprised of a porous, expanded polytetrafluoroethylene (ePTFE) membrane having a thickness of 5 micrometers, or less, and a dielectric constant of less than 3 0
  • the base substrate may be comprised of silicon, gallium arsenide, or ceramic, for example
  • the dielectric layer may be applied so as to produce an air gap dielectric between closely spaced conductors of the integrated electric circuit in a manner which does not require an extraction step to remove a filler material
  • the dielectric layer may also be impregnated with inorganic materials such as silicon dioxide, boron nitride, aluminum nitride, aluminum oxide, or silicon nitride
  • Figure 2 is an scanning electron photomicrograph (SEM) cross-section of a 0 7 ⁇ m ePTFE membrane - cyanate ester composite dielectric layer disposed between two silicon wafers,
  • Figure 3 is an SEM cross-section of a 0 6 ⁇ m ePTFE membrane - TFE- PDD copolymer composite dielectric layer disposed between two silicon wafers
  • Figure 4 ts an SEM cross-section of a 4 0 ⁇ m ePTFE membrane dielectric layer disposed between two silicon wafers
  • Figure 5 is an SEM cross-section of a 2 0 ⁇ M ePTFE membrane - cyanate ester composite dielectric layer disposed between a patterned silicon wafer and a metal foil
  • an integrated circuit element is provided generally at 10, which may be an active or passive element
  • the integrated circuit element is comprised of at least one substrate 1 1 and a planar dielectric layer 12 having a thickness of 5 micrometers, or less, and a dielectric constant of less than 3 9
  • the dielectric layer is preferably a fluoropolymer film which is either coated or impregnated with a low ionic content resm
  • a metal surface 13 may be disposed on a surface of the dielectric layer 1 1
  • a preferred fluoropolymer film is expanded, porous polytetrafluoroethylene membrane
  • a preferred resin component is a low-ionic content polymer having a low dielectric constant, high thermal stability, and low thermal expansion Examples of such resins are polyimide, benzocyclobutene, cyanate ester, polyarylether, parylene, fluorinated versions of the preceding, PFA, FEP, LCP, or TFE-PDD Air gaps 14 are formed between conductive tracers 15 As
  • PTFE shall mean a membrane which may be prepared by any number of known processes, for example, by stretching or drawing processes, by papermaking processes by processes in which filler materials are incorporated with the PTFE resin and which are subsequently removed to leave a porous structure or by powder sintering processes
  • the porous polytetrafluoroethylene membrane is porous expanded polytetrafluoroethylene membrane having a microstructure of interconnected nodes and fibrils as described in U S Patent Nos 3 953,566 4 187 390, and 4 110 392 which are incorporated herein by reference, and which fully describe the preferred material and processes for making them
  • the expanded porous polytetrafluoroethylene membrane may have a microstructure which is comprised substantially of fibrils, as desc ⁇ bed in U S Patent 5,476,589 incorporated herein by reference
  • plana ⁇ ty is defined as the maximum vertical deviation from flatness over a given length All products according to the invention have plana ⁇ ty less than 200 nm over 2 0 mm
  • the dielectric layer may be made from a polytetrafluoroethylene (PTFE) fine powder that has a low amorphous content and a degree of crystallization of at least 98%
  • PTFE polytetrafluoroethylene
  • This paste is then molded into the shape dictated by the intended use of the finished product by a molding method that imparts shear deformation, such as extrusion molding or calender molding It is usually molded into the form of a tape by extrusion
  • the polytetrafluoroethylene used herein is a coagulated dispersion or fine powder polytetrafluoroethylene Several such resins that have been used demonstrate that the various commercially available fine powders from the several suppliers of such resins are suitable in the process Some such resins can tolerate more extrusion aid than others and still yield products within the range of permeability desired Some such resins suitable for use are Fluoride (PTFE) fine powder that has a low amorphous content and a degree of crystallization of at least 98%
  • the coagulated dispersion powders are lubricated with a hydrocarbon extrusion aid, preferably an odorless mineral spirit such as Isopar K (made by Exxon Corp )
  • a hydrocarbon extrusion aid preferably an odorless mineral spirit such as Isopar K (made by Exxon Corp )
  • the lubricated powder is compressed into cylinders and extruded in a ram extruder to form tapes
  • Two or more layers of tape can be stacked together and compressed between two rolls
  • the tape or tapes are compressed between rolls to an appropriate thickness, e g 5 to 40 mils or so
  • the wet tape is stretched transversely to 1 5 to 5 times its original width
  • the extrusion aid is driven off with heat
  • the dried tape is then expanded longitudinally between banks of rolls in a space heated to a temperature that is below the polymer melting point (327°C)
  • the longitudinal expansion is
  • the tape after the longitudinal expansion, is expanded transversely at a temperature that is less than 327°C to at least 1 5 times and preferably to 6 to 15 times the input width of the original extrudate while restraining the membrane from longitudinal contraction While still under constraint the membrane is preferably heated to above the polymer melting point (327°C) and then cooled
  • the present invention provides a dielectric layer which is applied to a wafer substrate as a film or membrane
  • the dielectric layer may contain a resin at least partially penetrating into the pores or void spaces of the ePTFE This provides a high degree of flexibility in resin selection
  • Dielectric layer thicknesses may range from about a maximum of 5 micrometers to about less than 2 micrometers
  • the thickness of the dielectric layer is a function of the ePTFE membrane which acts as a scaffolding
  • the ePTFE membrane permits very thin films to be cast without pinholes
  • yields of the dielectric resin material may be improved to at least 50%, and possibly greater than 80%, as compared to about 5% yields with the conventional spinning processes This of course results in tremendous cost savings compared to the conventional spinning processes Potentially, even more significant cost savings can be obtained resulting from the reduction in processing steps which are presently employed by conventional methods to create air gaps within an integrated circuit element
  • the dielectric layers produced in accordance with the teachings of the present invention can be imaged well through a metal mask using laser ablation techniques or reactive ion etching
  • an integrated circuit element may be made by initially coating and/or impregnating the dielectric layer with a resin solution, or with molten resin Thereafter the solution is partially cured and/or dried
  • the ratio of resm to solvent may be varied in order to produce the correct degree of loading
  • a low solids content solution may be used in order to provide a minimum degree of loading, for example to just coat the fibrils of the ePTFE membrane comprising the dielectric layer
  • an inorganic material such as silicon dioxide, boron nitride, aluminum nitride, aluminum oxide, or silicon nitride may be introduced into the ePTFE dielectric layer by blending with the resm prior to its introduction into the membrane
  • the resin may be introduced into the ePTFE dielectric layer prior to the expansion process step of the ePTFE
  • the resm would typically be a thermoplastic in the form of small particles or powder
  • the amount and type of resin added may be varied in order to optimize the final properties of the dielectric material
  • an inorganic material such as silicon dioxide, boron nitride, aluminum nitride, aluminum oxide, or silicon nitride in powder form may be introduced into the ePTFE dielectric layer prior to the expansion process
  • the ePTFE may be used without resin additions of any kind, or these additions may be made to the base wafer prior to the lamination of the ePTFE sheet
  • the dielectric layer may be laminated to the base substrate by any suitable process, such as by an autoclave or a vacuum hot press process, for example
  • the autoclave process utilizes a pressurized gas to create a hydrostatic compressive force
  • This method has the benefit of a very uniform stress field, which is helpful in preventing brittle parts, such as silicon base wafers, from fracturing
  • a suitable autoclave process in accordance with the present invention is a modified process of the type described in detail in U S Patent 5 034 801 incorporated herein by reference Unlike the process taught by U S Patent 5 034 801 the autoclave process employed in the present invention does not cause resm to fill the gaps between narrowly disposed conductive traces of the integrated electric circuit In order to accomplish this, the autoclave lamination process described in U S Patent
  • 5,034,801 must be modified to account for three main variables namely pressure, temperature, and dwell time Dwell time is the amount of time at the maximum temperature and pressure selected for the process The selection of the appropriate values for each of these variables is dependent on the material to be laminated The pore size, pore volume, resin type and resin loading are all important in determining the lamination process variables
  • the vacuum hot press process is a conventional process which is used in the iamination of printed circuit boards
  • the press applies a unidirectional force to the parts to be laminated, rather than an isostatic force in the case of the autoclave
  • the main advantage to this method is high throughput Typically, several layers of parts to be laminated can be stacked together This process is also suitable for automation since no bag is required
  • a limitation of this process is that the lamination pressure is only uniform if the parts to be laminated are soft or ductile, or have exactly uniform thickness and if the press itself is dimensionally true The latter is not usually the case because of the distortions induced by the temperature and pressure gradients in the press
  • a press pad is typically a very soft, high temperature material such as silicone rubber
  • the mechanical compliance of the soft material helps to create a uniform stress field
  • very stiff, brittle base wafers are used with a conventional press pad, there is still a stress concentration around the periphery of the wafer This stress
  • the dielectric layer Since the dielectric layer thickness and the thickness of the conductive traces on the integrated circuit are roughly equivalent, the dielectric layer must be compressed by about 50 percent so that the dielectric layer can contact the substrate in areas not occupied by metal lines In order to allow for such compression, the dielectric layer must have at least 50 percent void space In addition, the lamination process must be controlled such that the dielectric polymer contained within the porous matrix is not allowed to flow into these gaps The pressure, temperature, and dwell time must be optimized such that the dielectric adheres properly to the substrate without flowing into the gaps
  • a metallization 13 on a top surface of the dielectric layer 12 This metallized surface is necessary to provide a subsequent level of interconnections for the integrated circuit
  • the metallized surface may be laminated to the dielectric layer concurrent with the lamination of the dielectric layer to the base wafer It is also possible to apply the metallized surface to the dielectric layer prior to laminating the dielectric layer to the base wafer, such as by physical vapor deposition, chemical vapor deposition, plating, or lamination
  • the prior application of metal to the dielectric layer has the advantage of permitting quality inspections prior to the lamination of the dielectric/metal combination to the base wafer
  • a 1 5 ⁇ m ePTFE membrane having a microstructure comprised substantially of fibrils was impregnated with a 50% cyanate ester/methyl ethyl ketone (MEK) solution The MEK was allowed to evaporate leaving the b- stage cyanate ester resm within the microstructure of the ePTFE membrane
  • MEK cyanate ester/methyl ethyl ketone
  • the composite of ePTFE membrane and resm was placed between two polished silicon wafers and laminated in a vacuum hot press at 175 psi and 225° C
  • the resulting laminate was cross-sectioned and examined in an SEM Figure 2 shows a resultant dielectric layer thickness of about 0 7 microns
  • a 1 5 ⁇ m ePTFE membrane having a microstructure comprised substantially of fibrils was impregnated with a 1 % TFE-PDD obtained from E I duPont de Nemours and Co under the tradename Teflon® AF solution The solvent was allowed to evaporate, leaving the TFE-PDD resin within the microstructure of the ePTFE membrane
  • the composite of ePTFE membrane and resin was placed between two polished silicon wafers and laminated in a vacuum hot press at 175 psi and 225° C The resulting laminate was cross- sectioned and examined in an SEM Figure 3 shows a resultant dielectric layer thickness of about 0 6 microns
  • Example 4 The cyanate ester/ePTFE membrane of Example 1 was placed between a silicon wafer with 0 65 ⁇ m high patterned metal features and Cu/polyimide/Cu foil The combination was then laminated in accordance with the teachings of Example 1
  • Figure 5 shows a planar structure with dielectric thickness between metal features of about 2 0 microns

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Laminated Bodies (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un élément de circuit intégré, qui peut être un élément actif ou passif. Cet élément de circuit intégré comporte une couche diélectrique plane (12) qui est laminée sur la surface des tracés électroconducteurs (15) et du substrat des semi-conducteurs (11). L'épaisseur de cette couche diélectrique (12) n'excède pas 5 νm pour une constante diélectrique inférieure à 3,4. La couche diélectrique (12) est de préférence un film fluoropolymère revêtu ou imprégné d'une résine à faible teneur en ions. Le film fluoropolymère préféré est du polytétrafluoroéthylène expansé, le composant résine préféré étant un polymère à faible teneur en ions, caractérisé par une faible constante diélectrique, une stabilité thermique élevée et une faible dilatation thermique.
PCT/US1997/005555 1996-04-12 1997-04-02 Procede de fabrication d'une structure d'interconnexion faisant intervenir le laminage d'une membrane dielectrique poreuse WO1997039484A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU24372/97A AU2437297A (en) 1996-04-12 1997-04-02 Method of fabricating an interconnect structure comprising lamination of a porous dielectric membrane

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63139196A 1996-04-12 1996-04-12
US08/631,391 1996-04-12

Publications (1)

Publication Number Publication Date
WO1997039484A1 true WO1997039484A1 (fr) 1997-10-23

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999018582A1 (fr) * 1997-10-07 1999-04-15 Abb Ab Dispositif electrique haute tension
DE10142223A1 (de) * 2001-08-29 2003-04-10 Infineon Technologies Ag Mittels Polymerisation erzeugte Hohlräume mit Submikrometer-Abmessungen in einer Halbleitereinrichtung
DE10142201A1 (de) * 2001-08-29 2003-04-10 Infineon Technologies Ag Mittels einer gefrierenden Prozessflüssigkeit erzeugte Hohlräume mit Submikrometer-Strukturen in einer Halbleitereinrichtung
DE10142224A1 (de) * 2001-08-29 2003-04-24 Infineon Technologies Ag Mittels eines Quellvorgangs erzeugte Hohlräume mit Submikrometer-Abmessungen in einer Halbleitereinrichtung
EP1316995A4 (fr) * 2000-08-15 2005-05-11 Tokyo Electron Ltd Dispositif a semi-conducteurs et son procede de fabrication
EP2706088A4 (fr) * 2011-05-06 2015-04-22 Guangdong Shengyi Sci Tech Co Matériau composite, carte de support de circuit à haute fréquence constitueé dudit matériau et procédé de production associé
US10676344B2 (en) 2015-11-30 2020-06-09 W. L. Gore & Associates, Inc. Protective environmental barrier for a die

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034801A (en) * 1989-07-31 1991-07-23 W. L. Gore & Associates, Inc. Intergrated circuit element having a planar, solvent-free dielectric layer
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034801A (en) * 1989-07-31 1991-07-23 W. L. Gore & Associates, Inc. Intergrated circuit element having a planar, solvent-free dielectric layer
US5461003A (en) * 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999018582A1 (fr) * 1997-10-07 1999-04-15 Abb Ab Dispositif electrique haute tension
EP1316995A4 (fr) * 2000-08-15 2005-05-11 Tokyo Electron Ltd Dispositif a semi-conducteurs et son procede de fabrication
DE10142224C2 (de) * 2001-08-29 2003-11-06 Infineon Technologies Ag Verfahren zum Erzeugen von Hohlräumen mit Submikrometer-Abmessungen in einer Halbleitereinrichtung mittels eines Quellvorgangs
DE10142224A1 (de) * 2001-08-29 2003-04-24 Infineon Technologies Ag Mittels eines Quellvorgangs erzeugte Hohlräume mit Submikrometer-Abmessungen in einer Halbleitereinrichtung
DE10142201C2 (de) * 2001-08-29 2003-10-16 Infineon Technologies Ag Verfahren zur Erzeugung von Hohlräumen mit Submikrometer-Strukturen in einer Halbleitereinrichtung mittels einer gefrierenden Prozessflüssigkeit
DE10142223C2 (de) * 2001-08-29 2003-10-16 Infineon Technologies Ag Verfahren zum Erzeugen von Hohlräumen mit Submikrometer-Abmessungen in einer Halbleitereinrichtung mittels Polymerisation
DE10142201A1 (de) * 2001-08-29 2003-04-10 Infineon Technologies Ag Mittels einer gefrierenden Prozessflüssigkeit erzeugte Hohlräume mit Submikrometer-Strukturen in einer Halbleitereinrichtung
US6645850B2 (en) 2001-08-29 2003-11-11 Infineon Technologies Ag Semiconductor device having cavities with submicrometer dimensions generated by a swelling process
US6696315B2 (en) 2001-08-29 2004-02-24 Infineon Technologies Ag Semiconductor device configuration with cavities of submicrometer dimensions and method of fabricating structured cavities
US6734095B2 (en) 2001-08-29 2004-05-11 Infineon Technologies Ag Method for producing cavities with submicrometer patterns in a semiconductor device using a freezing process liquid
DE10142223A1 (de) * 2001-08-29 2003-04-10 Infineon Technologies Ag Mittels Polymerisation erzeugte Hohlräume mit Submikrometer-Abmessungen in einer Halbleitereinrichtung
EP2706088A4 (fr) * 2011-05-06 2015-04-22 Guangdong Shengyi Sci Tech Co Matériau composite, carte de support de circuit à haute fréquence constitueé dudit matériau et procédé de production associé
US10194528B2 (en) 2011-05-06 2019-01-29 Guangdong Shengyi Sci. Tech Co., Ltd. Composite material, high-frequency circuit baseboard made therefrom and production method thereof
US10676344B2 (en) 2015-11-30 2020-06-09 W. L. Gore & Associates, Inc. Protective environmental barrier for a die

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