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WO1998007230A1 - Convertisseur de puissance fournissant une onde de sortie specifique - Google Patents

Convertisseur de puissance fournissant une onde de sortie specifique Download PDF

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Publication number
WO1998007230A1
WO1998007230A1 PCT/US1997/013978 US9713978W WO9807230A1 WO 1998007230 A1 WO1998007230 A1 WO 1998007230A1 US 9713978 W US9713978 W US 9713978W WO 9807230 A1 WO9807230 A1 WO 9807230A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
cunent
signal
output
register
Prior art date
Application number
PCT/US1997/013978
Other languages
English (en)
Inventor
Harold C. Scott
Chiping Sun
Kandarp I. Pandya
William J. Anderson
Original Assignee
Coleman Powermate, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/695,558 external-priority patent/US5900722A/en
Priority claimed from US08/752,230 external-priority patent/US5886504A/en
Application filed by Coleman Powermate, Inc. filed Critical Coleman Powermate, Inc.
Priority to AU41473/97A priority Critical patent/AU4147397A/en
Priority to CA002263451A priority patent/CA2263451A1/fr
Publication of WO1998007230A1 publication Critical patent/WO1998007230A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
    • H02P25/16—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the circuit arrangement or by the kind of wiring
    • H02P25/18—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the circuit arrangement or by the kind of wiring with arrangements for switching the windings, e.g. with mechanical switches or relays
    • H02P25/188—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the circuit arrangement or by the kind of wiring with arrangements for switching the windings, e.g. with mechanical switches or relays wherein the motor windings are switched from series to parallel or vice versa to control speed or torque
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B63/00—Adaptations of engines for driving pumps, hand-held tools or electric generators; Portable combinations of engines with engine-driven devices
    • F02B63/04—Adaptations of engines for driving pumps, hand-held tools or electric generators; Portable combinations of engines with engine-driven devices for electric generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P9/00—Arrangements for controlling electric generators for the purpose of obtaining a desired output
    • H02P9/10—Control effected upon generator excitation circuit to reduce harmful effects of overloads or transients, e.g. sudden application of load, sudden removal of load, sudden change of load
    • H02P9/107—Control effected upon generator excitation circuit to reduce harmful effects of overloads or transients, e.g. sudden application of load, sudden removal of load, sudden change of load for limiting effects of overloads
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P9/00—Arrangements for controlling electric generators for the purpose of obtaining a desired output
    • H02P9/14—Arrangements for controlling electric generators for the purpose of obtaining a desired output by variation of field
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P9/00—Arrangements for controlling electric generators for the purpose of obtaining a desired output
    • H02P9/48—Arrangements for obtaining a constant output value at varying speed of the generator, e.g. on vehicle
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B63/00—Adaptations of engines for driving pumps, hand-held tools or electric generators; Portable combinations of engines with engine-driven devices
    • F02B63/04—Adaptations of engines for driving pumps, hand-held tools or electric generators; Portable combinations of engines with engine-driven devices for electric generators
    • F02B63/044—Adaptations of engines for driving pumps, hand-held tools or electric generators; Portable combinations of engines with engine-driven devices for electric generators the engine-generator unit being placed on a frame or in an housing
    • F02B2063/045—Frames for generator-engine sets
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P2101/00—Special adaptation of control arrangements for generators
    • H02P2101/45—Special adaptation of control arrangements for generators for motor vehicles, e.g. car alternators

Definitions

  • the present invention relates to systems for converting mechanical to electrical energy, and, more specifically, to power conversion systems capable of accommodating a wide iange of input and load conditions
  • the generator typically comprises a rotor and stator arranged for relative rotation
  • the rotor is d ⁇ ven by the energy source, often mounted on the shaft of the motor
  • the rotor typically generates a magnetic field (using either permanent magnets or windings) which interacts with windings maintained on the stator
  • an elect ⁇ cal current is generated
  • the induced current is typically applied to a bridge rectifier, sometimes regulated, and provided as an output
  • the rectified signal is applied to an inverter to generate an AC output
  • Generators which use permanent magnets to generate the requisite magnetic field tend to be lighter and smaller than traditional wound field generators
  • the power supplied by permanent magnet generator has histo ⁇ cally been difficult to regulate or conttol
  • the voltage supplied by the generator vanes significantly according to the speed of the rotor
  • the voltage tends to vaty inversely with the current delivered, l
  • generators capable of starting motoi vehicles are typically ungainly, and heavy, weighing on the order of 180 pounds or more
  • the present invention provides a generatoi capable ot providing a regulated voltage regardless of speed and current fluctuations
  • the generator is light weight and compact, while at the same time suitable for high output applications
  • a generator is implemented using a controller which selectively activates individual windings to achieve a desired output
  • the windings may be connected a fully parallel configuration to provide high current at relatively low voltage levels, or in se ⁇ es to provide high voltage capacity
  • the controller varies the power output of the generator according to system parameters, such as current or temperature
  • system parameters such as current or temperature
  • a limiting feature to prevent current overload or system overheating may be provided
  • the controller vanes the order in which the windings are activated and deactivated Varying the activation tends to provide optimal heat dist ⁇ bution among the several windings
  • Another aspect of the invention provides a system for generating a plurality of regulated DC rail voltages, and an AC signal
  • throttle control is effected in accordance with load to facilitate fuel economy and noise abatement
  • FIG. 1 is a block diagram of an exemplary generator system according to various aspects of the present invention
  • Figure 2 is a schematic side view representation of a fully wound stator in accordance with vanous aspects of the present invention employing three-pole winding groups in a twelve pole system
  • Figure 3 is a schematic side view of a partially wound stator in accordance with vanous aspects of the present invention employing a one-pole winding group in a twelve pole system
  • Figure 4 is a schematic side view of a partially wound stator in accordance with vanous aspects of the present invention employing a three-pole winding group in a twelve pole system,
  • Figure 5 is a block schematic diagram of a multi-coil system for generating a plurality of regulated DC rail voltages and an AC output
  • Figure 6 is a schematic diagram of a zero crossing detector suitable for use in the system of Figure 5
  • Figure 7 is an illustration of a sine wave simulated by first and second pulses of opposite pola ⁇ ty
  • Figure 8 is an illustration of a sine wave simulated by stacked sets of pulses
  • Figure 9 is a schematic diagram of one embodiment ol microprocessor-based digital control circuit
  • Figure 12 is a functional flow chart of a MAIN routine effected by the microcomputer of Figure 9,
  • FIG. 1 is a functional flow chart oi a TIMERO routine effected by the microcomputer of Figure 9,
  • Figure 14 is a functional flow chart of an Inverter UPDATE routine effected by the microcomputer of Figure 9,
  • Figure 15 is a functional flow chart of a zero crossing subroutine effected by the microcomputer of Figure 9
  • Figures 16 A and 16B (collectively referred to as Figure 16) is a functional flow chart of a se ⁇ al output routine effected by the microcomputer of Figure 9,
  • Figures 17A and 17B (collectively refened to as Figure 17) is a functional flow chart of a TIMER1 routine effected by the microcomputer of Figure 9,
  • Figures 18A and 18B (collectively referred to as Figure 18) is a functional flow chart of a powei out subroutine routine effected by the microcomputer of Figure 9,
  • FIG 19 is a functional flow chart of a THROTTLF routine effected by the microcomputer of Figure 9,
  • Figures 20A and 20B are schematic illustrations of a throttle control in respective states routine effected by the crocomputer of Figure 9
  • Figure 21 is a schematic diagram of a power converter suitable for use in the system of Figure
  • Figure 22 is a block schematic diagram of an inverter rail generator suitable for use in the system of Figure 5,
  • Figures 25 and 26 are schematic diagrams of alternative power converters suitable for use in the system of Figure 5
  • Figure 27 is a block schematic diagram of a power converter employing a switched capacitor suitable for use in the system of Figure 5
  • Figure 28 is an illustration of a sine wave generated by the power converter of Figure 27,
  • Figures 30 and 31 are schematic illustrations of power convertei 2700 illustrating accommodation of lagging currents caused by inductive load
  • Figure 32 is a block schematic of converter 2700 employing a capacitive dump feature
  • Figures 33A and 33B are block diagrams illustrating stepping motors and controls
  • Figure 34 is a block diagram more particularly illustrating a unidirectional stepping motor configuration
  • Figure 35 is a block diagram of a direct d ⁇ ve throttle control
  • Figures 36A, B, C and D are mechanical linkage for a throttle control
  • Figures 37 and 38 illustrate a cam drive for a throttle control
  • Figure 39 is a block schematic diagram of a multipurpose system for providing a relatively high voltage, low current AC signal suitable for powenng lighting and appliances, a relatively high output current suitable for battery charging and starting vehicles, and an output suitable for are welding,
  • Figure 40 is a schematic diagram of an inverter rail generator suitable for the system of Figure 39,
  • Figure 41 is a block schematic of a controller suitable for the system of Figure 39,
  • Figure 42 is a block schematic of suitable gating circuit tor the system of Figure 39
  • Figure 43 is a cunent sensor suitable for sensing welding operations
  • Figure 44 is a suitable cunent sensor for use in the system of Figure 39,
  • Figure 44A is a block schematic of a suitable negative voltage supply.
  • Figure 47 is a functional flow chart of an initialization routine.
  • Figures 48A and 48B are a functional flow chart of a continuous p ⁇ mary loop program
  • Figure 49A is a functional flow chart of a main program relating to inverter mode operation
  • Figure 49B is a functional block diagram of the process relating to coordinating voltage sampling with the operation of the switched capacitor of Figure 27,
  • Figure 49C is a functional flow chart of an A to D subroutine
  • Figures 50A and 50B (collectively refened to as Figure 50) is a functional flow chart of a IRQ4 interrupt routine, pertaining to pulse population modulation control of the power converter,
  • Figures 51 A and 51 B (collectively referred to as Figure 1 ) is a functional flow chart of a IRQ5 interrupt routine, pertaining to pulse population modulation control of the power converter
  • Figure 52A is a functional flow chart of an IRQ2 routine relating to voltage sensing
  • Figure 52B is a flow chart of an IRQ3 interrupt routine, relating to ovei cunent sensing
  • Figure 53 is a functional flow chart of the POSDIR subroutine relating to adjusting the throttle in a positive direction;
  • Figure 54 is a functional flow chart of the NEGDIR subroutine relating to adjusting the throttle in a negative direction
  • Figure 57 is a schematic diagram of a circuit for generating a welding signal and battery charging signal from the same alternator winding
  • Figure 58 is a schematic diagram of a suitable IR compensation circuit
  • Figure 59 is a block schematic of a throttle control employing a servo motor
  • Figure 60 is a block schematic diagram of a combination starter, battery chai er suitable for use in the system of Figure 39
  • Figure 61 is a schematic block diagram of a generatoi system in one embodiment of the present invention.
  • Figure 64 is a schematic diagram of the feedback sealer shown in Figure 62
  • FIG 68 is a functional flow chart of a throttle initialization routine performed by the microcontroller shown in Figure 62
  • Figure 69 is a functional flow chart of a routine that advances the throttle in the positive direction performed by the microcontroller shown in Figure 62
  • Figure 70 is a functional flow chart of a stepper advance routine performed by the microcontroller shown in Figure 62
  • Figure 72 is a functional flow chart of an interrupt service routine performed by the microcontroller shown in Figure 62
  • Figure 73 is a functional flow chart of an over cunent recovery process performed by the microcontroller shown in Figure 62
  • Figure 73 A is a graph of engine RPM for the system shown in Figure 61
  • Figure 74 is a functional flow chart of a voltage regulation routine performed by the microcontroller shown in Figure 62
  • Figure 74A is a functional flow chart of an interrupt service routine performed by the microcontroller shown in Figure 62
  • Figure 75 is a functional flow chart of a routine for idle tuning performed by the microcontroller shown in Figure 62
  • Figure 76 is a functional flow chart of a dynamic control routine performed by the microcontroller shown in Figure 62
  • Generator unit 16 suitably includes a multi-winding stator 18, a rotor 20, a control circuit 22, a switching circuit 24, output terminals 26 and 28, and at least one sensor, e g , sensors 30A, 30B, 30C, and 30D, collectively refened to as sensors 30
  • Energy source 14 may compnse any source of rotational energy, such as, for example, a conventional steam-driven turbine, a conventional diesel engine or conventional internal combustion engine with a rotational output shaft 32 and throttle 34
  • Engine 14 transfers power to generator unit 16 by causing shaft 200 to rotate at a speed in accordance with the setting of throttle 34 If desired, system
  • Throttle control device 36 suitably comprises an electra-mechanical actuator for controlling the setting of throttle 34 in accordance with control signals from control circuit 22
  • Examples of suitable throttle contiol mechanisms will be desenbed in conjunction with Figures 19, 20A and 20B, 33-38 and 59
  • Generator unit 16 converts mechanical energy, e g , rotation of shaft 32, into electrical energy to selectively supply load 12.
  • Stator 18 and rotor 20 are disposed such that rotation of rotor 20 induces current in the windings of stator 18
  • the control is suitably effected in accordance with feedback provided by one or more of sensors 30
  • Engine 14 and generator 16 may be directly coupled, 1 e , shaft 32 may be the engine shaft, oi may be indirectly coupled, e g., as in an automotive application where shaft 32 is a separate bolt driven shaft If desired, engine 14 and generator 16 may be mounted together as a unit on a common frame, e g , as in a genset Refernng now to Figure 2, rotor 20 is preferable a permanent magnet rotor of sufficiently light weight that it can be maintained in axial alignment with, and rotated in close proximity to, stator 18 (I e., with a relatively small predetermined air gap 202, e.g., in the range of .020 to .060 inch, and preferable .030 inch) without the necessity of any bea ⁇ ngs in addition to those conventionally included within engine 14.
  • stator 18 I e., with a relatively small predetermined air gap 202, e.g., in the range of .020 to .060 inch, and preferable .030 inch
  • Rotor 20 suitably manifests a generator output power to rotor weight ratio in excuse of 150 or 200 watts per pound, preferable in excuse of 500, more preferable in excuse of 700, and most preferable in excuse of 800.
  • the prefencd embodiment manifests a generator output power to rotor weight ratio in the range of 800 to 900 in watts per pound.
  • rotor 20 would suitably weigh no more than approximately 2.40 pounds.
  • rotor 20 preferable weighs no more than 1.06 pounds. This is achieved economically by employing high energy product magnets and consequence poles, as discussed in copending applications U.S Patent
  • Stator 18 preferable includes a plurality of three-phase windings 400 to generate low voltage, high cunent outputs, preferable wound with the respective coils of each phase grouped together, and concunently wound about a laminate core as a unit to provide particularly advantageous heat dissipation charactenstics.
  • stator 18 includes twelve windings configured as tour sets of three-phase star windings (as schematically shown in Figure 10, for example). Each stator winding includes a predetermined number of turns conesponding to the voltage output associated with that winding.
  • stator 18 includes a soft magnet core 302 having a crenelated inner periphery with a predetermined number of equally spaced teeth 304 and slots 306
  • the number of slots 306 is equal to a predetermined multiple ot the number of poles of rotor 20 times the number of phases.
  • the minimum number of slots 306 is equal to the number of poles times the number of phases, i.e., the minimum number of teeth provided per pole is equal to the number of phases.
  • at least 36 slots 306 will be provided in stator core 302
  • a predetermined number of independent groups of windings are provided on core 302, wound through slots 306 about predetermined numbers of teeth 304
  • the predetermined number of groups of windings is an integer fraction of the number of poles, i.e , for 12 poles, there could be a single group using all 12 poles (conventional); two groups using six poles each; three groups using four poles each; four groups using three poles each; six groups using two poles each; or twelve groups using one pole each.
  • the power provided by each group is relatively unaffected by the status of the other groups.
  • controller circuit 22 selectively completes cunent paths to the individual groups of windings to achieve a desired output.
  • a one-pole winding group 310 in a three-phase system comprises respective phase windings. A, B and C connected together at one end, 312, in a star configuration.
  • the winding conesponding to each phase is wound about the predetermined number of teeth conesponding to a pole, e.g., 3, with each successive phase winding shifted by one slot, and wound in the opposite direction from the preceding phase winding.
  • the one pole group is therefore wound about a group of five teeth: first phase A winding is wound about teeth 304A, 304B, and 304C; phase B is wound about teeth 304B, 304C, and 304D; and phase C is wound about teeth 304C, 304D, and 304E.
  • stator core 302. twelve such one pole winding groups 310 (only one shown) would be provided about stator core 302. As will be discussed, a separate controlled cunent path is provided with respect to each winding group to provide output control.
  • the stator employs four three-pole winding groups 400 (only one shown in Figure 3).
  • Each phase winding (A, B, C) of each group 400 is wound in alternating directions about three successive three-teeth groups (each three-teeth group corresponding to a pole), with each successive phase winding shifted by one slot.
  • the winding of one group conesponding to a given phase may partially overlap the windings of an adjacent group conesponding to the other phases, i.e., the winding of one group conesponding to a given phase may share two (the number of phases) teeth with the windings of an adjacent group.
  • the overlap of the windings causes some small magnetic interaction between adjacent groups.
  • sensors 30 suitably measure various system parameters, such as, voltage output (sensor 30A), cunent output (sensor 30B), temperature (sensor 30C) and/or rotor (engine) RPM (sensor 30D). Sensors 30 provide appropriate signals to control circuit 22 to indicate, for example, whether system 10 is providing appropriate output voltage or cunent, is operating at an appropriate engine speed, or whether a preselected maximum and/or minimum voltage, cunent, temperature has been reached.
  • control circuit 22 suitably generates control signals to activate and deactivate the various windings 400 and/or adjusts the setting of throttle 34 to achieve the desired output, engine speed or temperature. For example, if signals from sensors 30 indicate that the system output voltage is below the desired voltage, control circuit 22: activates more windings 400, thus adding the cunent generated by the additional windings 400 and raising the overall current and voltage to the desired level; increases the percentage of the rotor cycle dunng which windings are activated by, e.g., varying fi ⁇ ng angle (pulse width) or pulse population (number of pulses per unit time); and/or varies the throttle setting to increase rotor (e.g., engine) speed.
  • fi ⁇ ng angle pulse width
  • pulse population number of pulses per unit time
  • one or more windings 400 may be deactivated to reduce the number of windings 400 supplying load 1 , the percentage of the rotor cycle dunng which windings are activated decreased, and/or the rotor speed increased.
  • damage to components caused by cunent surges due to vanations in load can be avoided by sensing an impending over-current condition, and using one or more of the forgoing techniques, decreasing the system output by a predetermined amount or lo a predetermined level, then gradually increasing the output to bring the system back to desired operating conditions
  • Switching circuit 24 under the auspices of control circuit 22, selectively completes cunent paths through the respective winding groups to achieve desired output characteristics or temperatuie
  • switching circuit 24 may be responsive to digitally generated control signals or to analog generated control signals, and may be configured to effectively connect the windings in parallel to provide a high cunent output at relatively low voltage levels, or may be configured to effectively connect the windings in series to provide high voltage capacity
  • switching circuit 24, suitably comprises a controlled cunent path associated with each winding 400, effectively configured as a plurality of switching rectifier circuits.
  • the controlled cunent paths are suitably effected using a power diode; a connecting switch or relay, such as a semiconductor controlled rectifier (SCR), a control diode, and a control switch or relay, such as a transistor.
  • a connecting switch or relay such as a semiconductor controlled rectifier (SCR), a control diode, and a control switch or relay, such as a transistor.
  • SCR semiconductor controlled rectifier
  • control circuit 22 is suitably responsive to a control signal from control circuit 22
  • Control circuit 22 suitably comprises a microprocessor-based system for receiving data from sensors 30 and activating or deactivating the control switches of switching circuit 24, accordingly
  • Control circuit 22 may be voltage regulated, i.e , the control circuit activates and deactivates the various windings to achieve a desired voltage.
  • control circuit 22 may be cunent and temperature limiting, so that if either the cunent or the temperature exceeds a preselected threshold, control circuit 22 automaticallv reduces the number of activated windings 400, regardless of the voltage output
  • the current and temperature limiting functions diminish the likelihood of overloading or burning out components of generator unit 16. Those functions could be varied, of couise, to regulate the output according to any parameter, and limit output according to any otheis.
  • control circuit 22 may suitably be designed to alternate which windings 400 are activated and deactivated and the duration for which they remain activated
  • the windings may be activated and deactivated on a first in, first out (FIFO) basis
  • FIFO first in, first out
  • the cunent path that has been activated for the longest time is the first to be deactivated as required
  • the cunent path that has been deactivated for the longest time is the first to be activated as required
  • none of the windings 400 remains activated significantly longer than any other winding 400 so that heal generation is distnaded more or less evenly among windings 400
  • Vanous suitable configurations of control circuit 22 are described in copending applications U S Patent Application Serial Nos 08/306,120 and 08/370,577
  • a stator winding control system in accordance with various aspects of the present invention can be utilized in a number of different applications and is of particular utility where a rotary source (e g , engine) is d
  • a system 500 foi geneiatmg a plurality of regulated DC rail voltages responsive to a wide range of input d ⁇ ve speeds may be formed utilizing a predetermined numbei e g , four (4), of winding groups 400 to supply respective positive DC rails 501A, 501B, a respective controlled cunent path associated with each winding, effectively configured as a switching regulatoi (e g , three-phase regulated rectifier bndge) 502, associated with each winding group 400, a single phase control winding 504, a single phase regulator (e g , regulated rectifier bridge 506), cooperating with control winding 504, respective conventional regulator devices 508 and 510 (such as, e g , Motorola
  • 78LXX se ⁇ es pass three load regulator devices) to provide stable regulated DC outputs at designated levels (e g , 15 volts, 5 volts), a suitable zero crossing detector 512, a suitable controller 22, a suitable cunent sensor 514, respective sets of conventional analog switches 516 and 518 (e g , CD405 ) (or a suitable analog multiplexer chip), operating under the contiol of controllei 22, respective push button input switches 520, and respective voltage sensots 522 and 524, e g voltage dividers, to generate indicia (Rvolt) of the DC rail and (Cvolt) control coil voltages at suitable voltage levels
  • Respective DC voltages of predetermined values e g , 300 V and 150 V or 1 50 V and 75 V are provided on positive DC rails 501A and 501B, relative to a negative rail 501 C (suitably floating relative to system ground, via a diode D7)
  • system 500 can also include a suitable power converter (inverter)
  • Inverter rail generation system 540 suitably comprises a separate set of one or more winding groups 400A, 400B on statoi core 302 and coopeiating rectifiers (e g , three-phase regulated rectifier b ⁇ dges and/or unregulated rectifier b ⁇ dges), which do not cont ⁇ bute to the voltages on DC rails 501 A or 501B, but rather establish separate, generally independent inverter rails (542, 544)
  • Use of independent winding groups 400A, 400B and cooperating rectifiers to establish substantially independent DC voltage(s) to supply inverter 530 facilitates concunent operation of inverter and, e g , welder opeiation
  • Regulators 502 provide a respective controlled cunent path associated with each winding, and may be any switching regulator, e g , multi-phase rectifier bndge, responsive to input control signals associated with the respective windings of the group (e g , phases), and capable of accommodating the voltage and cunents at which the system is intended to operate hor example, regulators 502 suitably compnse a multi-phase (e g , three-phase) SCR rectifier bridge having a respective leg associated with each phase comp ⁇ sing a power diode) a connecting switch or relay (e g , a SCR), a control diode, and a control switch or relay, such as a transistor responsive to a control signal, suitably from controller 22 To achieve generation of the desired voltages and cunent control in the embodiment of Hgure
  • Contiollei 22 provides signals to regulators 502 to effectively connect or disconnect respective coils in the operative circuit to provide a desired level of cunent, and adjust the relative finng angles of the respective phases to control voltage output
  • Rotor and stator are designed such that the unit is capable of generating a DC output signal meeting certain cnte ⁇ a (and if inverter 530 is employed, also an AC output signal meeting certain c ⁇ tena) even at the lowest operational rotor RPM (e g , idle speed) At the minimum operational speed (RPM), all (or at least most) of winding groups 400 (and 400A and 400B) would typically be connected in the
  • Controller 22 may be any circuit capable of responding to the sensor signals and providing suitable control signals for regulators 502 to geneiate the desned output, (and preferable to regulatoi 506, and converter 530 and inverter rail generator 540, if employed)
  • controller 22 generates control signals (SCR 1 -SCR 12) to regulators 502, and control signals (SCR13-SCR14) to regulator 506
  • regulator 506 is employed to ensure the availability of a stable power source for the vanous components of the system
  • controller 22 when power converter 530 is included in the system, controller 22 generates switching control signals to power converter 530 (LHRL, RHLL, and/or in vanous embodiments HIV, and/or Top_Left (T_L) Bottom_Lcft (B_L), Top_R ⁇ ght (T_R), and Bottom_R ⁇ ght (B_R), and Cap_Dump (C_D))
  • Controller 22 may also, if desired, generate switching control signals (e
  • Sensor signals suitablv include a signal (Rvolt) indicative of the level of high DC rail 501 A, a signal (Cvolt) indicative of the level of the voltage across control coil 504, a signal (ISEN) indicative of the output cunent from cunent sensor 514, a signal (Tvolt) indicative of the temperature of the unit, from temperature sensor 30C
  • Indicia (Rvolt) of DC rail voltage and indicia of control coil voltage (Cvolt) are provided by voltage sensors 522 and 524, respectively, suitably signals having a voltage (within appropnate ranges) indicative of the measured voltage Sensors 522 and 524 may be any device capable of providing a signal (e g , voltage within appropriate ranges) indicative of the magnitude of the measured voltage
  • Indicia (ISEN) of DC output cunent is provided by cunent sensor 14 suitably a signal having a voltage indicative of the cunent output of the system
  • Cunent sensor 14 may be any device capable of providing a signal (voltage within appropriate ranges) indicative of cunent magnitude
  • a Hall effect sensor it is advantageous to utilize a Hall effect sensor to avoid power loss
  • the voltage generated by cunent flow through a small resistor e g , 0 1 ohm
  • Sensoi circuit 536 may be any device capable of suitably generating a signal (e g voltage within a suitable range) proportional to the average voltage of output signal 532 For example, a suitable sensor circuit
  • 536 may be formed of a single phase diode bridge connected to output terminals LI and L2, suitable low pass filter circuits) a Zener diode) and a voltage divider Output signal 532, as provided at output terminals LI and L2, is applied to the bridge to generate an average DC signal
  • the DC signal is filtered smoothed and limited by the filters and Zener diode, and applied to the voltage divider to generate a signal proportional to the average voltage of output signal 532
  • the signal is applied to analog multiplexer (switch set) 516 for selective application to controller 22
  • Cunent sensor 538 may be any device capable of providing a voltage indicative of cunent
  • the lac voltage may be generated by cunent flow through a small resistor (e g , 0 1 ohm) R3 ( Figure 21 )
  • a Hall effect sensor it is advantageous to utilize a Hall effect sensor to avoid power loss
  • Control winding 504 is suitably wound concuirently on stator core 302 with a predetermined one of the phases (e g., phase A) of one of the winding groups 400 Although physically wound with a winding group 400, control winding 504 is independently controlled (by regulator 506), and is operatively connected in the system inespective of the status of the winding group 400 with which it is wound
  • Control winding 504 cooperates with regulator 506 and regulator devices 508 and 510 to generate stable supply voltages (e g., 5 volts, 15 volts) for the various circuitry
  • Regulator 506 may be any suitable regulated single phase regulator, e g , SCR rectifier bridge, of appropriate power rating
  • a regulated rectifier is preferable to an unregulated bndge to accommodate the range of induced voltages, and assure suitably stable supply voltages over the entire range of operation
  • the parameters of coil 504 are chosen such that it generates a sufficient cunent to generate the supply voltages at the minimum operational speed (RPM), e g , at idle speed, with regulator SCR s "full on" The SCR firing angles are then vaned to maintain the desired control voltage at higher RPM
  • an unregulated rectifier may be used
  • Control winding 504 also provides a signal from which indicia of phase can be derived Since control coil 504 is physically wound with one of the phases of a winding group 400, winding 504 is in phase with the particular group phase winding Accordingly, zero crossings in the signal induced in coil 504 are concunent with those in the group phase winding with which control winding 504 is wound
  • a suitable zero crossing detector 512 comprises a conventional comparator 602 with the respective inputs thereof connected across control coil 504 (at terminals X 1 and X2) through respective resistors 604 and 606 The inputs aie suitably clamped by diodes Dl 1 , D12, D13, and D14.
  • comparator 602 When the voltage at input XI exceeds input X2, comparator 602 will generate a logic high output Conversely, when input XI is less than the input X2, comparator 602 will generate a logic low output Accordingly, zero crossings are signified by transitions in the output (ZEROX) of comparator 602 To transition between supply voltage levels of different components of the system, comparator 602 is suitably an open drain or upon collector device, when a low logic ou ⁇ ut is generated, the output is effectively connected to ground When a high level output is indicated, the connection to ground is opened and the output effectively connected to a power supply of the desired logic high level
  • Power converter 530 (in the prefened embodiment, in effect, a variable frequency inverter) generates an output signal 532 at terminals LI and L2 of a conventional outlet 534 with a predetermined waveform simulating (e g , having the same RMS value as) the desired AC signal (e g , 120 V, 60 Hz in the U S , 240 V, 50 Hz in Europe)
  • a predetermined waveform simulating e g , having the same RMS value as
  • the desired AC signal e g , 120 V, 60 Hz in the U S , 240 V, 50 Hz in Europe
  • a desired sine wave output can be more closely approximated by shaping the waveform of output signal 532, e g , using stacked sets of a predetermined number of pulses
  • a sine wave is more closely simulated by generating first and second base pulses of opposite polanty 802 and 804, with an intervening dead time 806 from the trailing edge of the first pulse 802 at time Tl , to the loading edge of second pulse 804 at time T2
  • a thud pulse 808 is provided effectively stacked on pulse 802, with a loading edge at time T and trailing edge at time T4
  • a fourth pulse 810 is similarly provided effectively stacked on pulse 804 Contiol of the pulse widths, and dead time in relationship to the voltage levels provides an RMS value approximately equal to that of the desired sin wave
  • a suitable microcomputer controller 900 comprises a conventional microcomputei chip 902, a predetermined number of suitable eight-bit, se ⁇ al input, latched parallel output registers (serial input counters) 904, 905, 906 and 907, such as 74HC595 devices; a conventional seven stage counter 908; a suitable ceramic oscillator 910 providing a clock signal at predetermined frequency, e.g., 8 MHz, to microcomputer 902; and a resistive ladder 912.
  • circuit 900 can also include a suitable throttle control driver 914.
  • Microcomputer 902 may be a conventional microcomputer chip including internal counters, registers, random access memory (RAM) and read only memory (ROM).
  • the registers may be separately addressable hardware registers or may be implemented as locations in RAM.
  • the microcomputer RAM may be implemented as separately addressable hardware registers.
  • the microcomputer chip includes also internal comparators capable of generating interrupt commands in response to external signals. External comparators, providing inputs to interrupt ports of the microcomputer chip, can also be utilized.
  • Microcomputer chip 902 suitably performs a sequence of operations in accordance with a program maintained, e.g., in ROM.
  • the operations are effected using the internal processor, registers and comparators of (or cooperating with) the chip.
  • the amount of random access memory is relatively limited.
  • Such microcomputers typically include a predetermined number of fixed function processor registers, and a plurality of individually addressable registers that effectively serve as RAM. In some instances, however, the registers are divided into nominal groups (pages) that arc accessible only on a mutually exclusive basis. In general, each routine effected by the microcomputer operates within a particular page of registers. However, when the routine requires a data value (variable) stored in a different page of registers, since the respective pages of registers can be accessed only on a mutually exclusive basis, a page change process must be effected.
  • the desired value is placed in a buffer included among the fix processor registers (particularly a stack), a page change process effected to retu ⁇ i to the original page, and the data value transfened from the buffer (stack) to the register on the original page (the transfer process is refened to as passing data between pages).
  • universal variables are so widely accessed, that they are routinely passed to a new page when it is accessed.
  • Each of the universal variables is, in effect, assigned a dedicated register in each of the various pages of register.
  • a plurality of universal variables are involved and the data passing is effected employing a last-in, first-out (LEFO) stack.
  • microcomputer 902 is suitably a Zialog Z86E04 chip which includes a bank of fixed function registers, at least one processor defined fixed function stack, and 16 pages of 16 addressable registers each.
  • the respective pages of memory are accessible only on a mutually exclusive basis, and conventional page change processes are effected as necessary.
  • microcomputer 902 is suitably configured to include two internal comparators, which compare respective selected sensor voltages (provided at microcomputer pins 8 and 9, respectively) to a common reference signal applied at pin 10
  • the common reference signal is suitably a controlled substantially linear (albeit stopped) ramp voltage ranging from O to 5 volts, generated by applying an incremented count to resistive ladder 912
  • the digital count applied to ladder 912 is suitably generated by counter 908, in response to a clock signal from microcomputer 902 (pin 4)
  • the voltage across resistive network 912 is filtered and applied at pin 10 of microcomputer 902
  • the sensor outputs are selectively applied to the comparator inputs through analog switch sets 516 and 518 ( Figure 5)
  • the sensed parameters are divided into a number of groups equal to the number of available microcomputer inputs, e g , two for the present embodiment, pins 8 and 9 of microcomputer 902 ( Figure 9)
  • Analog switches 16 and 518 are selectively actuated, undei control of microcomputer 902 to apply a selected one of the group of parameters to the associated microcomputer input
  • Analog multiplexer chips e g , 8 to 1
  • Switch sets (MUX's) 516 and 518 apply each parameter in the associated group to the microcomputer input sequentially, in successive measurement cycles through switch set
  • system 500 includes mvertei 530, signals Vac, indicative of the load on (average voltage of) inverter 530 and lac, indicative of the current output of inverter 530 are applied as part of the groups associated with pins 8 and 9 respectively
  • Compansons of the selected sensed parameter indicia against the ramp signal are employed to generate digital indicia of the parameters, at the point when the reference voltage ramp reaches the parameter indicia, an accumulated count (A to D), paralleling the contents of counter 908 that generate the ramp, is indicative of the value of the parameter
  • an accumulated count A to D
  • the capture of the parameter value is effected by initiating an approp ⁇ ate interrupt
  • Microcomputer 902 cooperates with se ⁇ al-input-parallel- output registers 904-907 to generate control signals to the SCR s of regulators 502 and 506, analog switches 516 and 518 and push button input switches 520, and an inverter circuit, if employed
  • One of the output pins (e g , pin 13) of microcomputer 902 may be effectively employed as a serial data bus, a desired bit pattern is serially provided on the line and applied at the data inputs of all of the output registers Se ⁇ al data clock signals (SCLK) are selectively provided at respective output pins (e g , 15-18) synchronously with the serial data
  • the se ⁇ al data clock signals are provided only at the output pins conesponding (coupled) to a selected one of registers 904-907 to select, and load the data into the appropnate register
  • a subsequent control signal (RCLK) is provided at pin 12 of microcomputer 902 and applied concunently to each of registers 904-907 to load the
  • senal-input-parallel-output registers 904 and 905 cooperate with microcomputer 902 to generate the control signals SCR1 -SCR14 to the vanous control SCR s of three-phase regulators
  • a data bit pattern conesponding to the desired states of SCR s 1 -8 is provided scnally at pin 13 of microcomputer 902 Se ⁇ al clock input pulses (SCLK) are concomitantly generated at the microcomputer output pin (e g , pin 18) conesponding to se ⁇ al register 904, to shift the bit pattern into register 904 Once register 904 has captured the senal bit pattern, a latch output signal (RCLK) is generated at pin 12 of microcomputer 902 The latch output signal
  • RCLK causes each of registers 904-907 to load the bit pattern contained in the senal input register into the output latch of the device, and hence, apply the bit pattern as contiol signals to the conesponding devices, in the case of register 904, SCR's 1 -8
  • the latch output signal (RCLK) is concunently applied to each of registers 904-907
  • the input shift register of counter 904 accumulated any new data, the contents of the input registers of the other counters remained unchanged
  • Input push button switches 520 are employed to provide operator input to the system with respect to, e g , desired mode of operation, desired output voltage and desired output cunent Foi example, in the context of a multi-mode welder, push button switches 520 would include a welding-mode button, which would be sequentially depressed to sequence through the different types of welding operations, an increment button, which is depressed to increment the target value for cunent or voltage, depending upon the chosen operational mode, and a decrement button, which is depressed to decrement the target value of cunent or voltage depending upon the selected mode
  • Briefly input switches 520 are each connected to a respective output pin (PB01 PB04) of register 906, and, connected in common, to a push button input line (PBTN Nf) to microcomputer 902 (pin 1 , Figure 9)
  • Senal data and concomitant clock signals are generated by microcomputer 902 to generate a bit pattern in register 906 that provides a logic high signal on a particular one of switches 520 The state of input
  • Microcomputer 902 develops and/or maintains a number of variables in RAM. As noted above, depending upon the particular microcomputer chip employed as microcomputer 902, separate hardware registers may be utilized for each variable. If the registers are organized in separate pages, conventional universal variable and page changing techniques would be employed. As set forth in Table 1 , and referring to Figure 1 1 , exemplary variables include:
  • a to D 1 102 Analog to digital A to D conversion count, indicative of the reference ramp voltage
  • VAC 1107 Indicia of the voltage generated by at AC terminals LI , L2
  • RPM 1 1 12 Count indicative of the instantaneous phase of the rotor cycle, incremented every Timer 0 Interrupt (125 microseconds), reset upon zero crossing after updating winding firing phase counts
  • byte 1 142 Used in connection with the senal output of the bits 6,7 SCR control word and inverter control byte to develop the control signals for the SCR's and inverter; identifies which byte (1922 or 1 124 or 1 125) is being operated upon 1 st cycle 1 142b ⁇ t5 Signifies that any initial partial cycle has been completed and a RPM count started at zero crossing is indicative of rotor cycle phase
  • I mode 1 142b ⁇ t3 Indicates selection of cunent mode of operation
  • MODEREG 1 143 Indicates the operational mode of the system
  • Throttle Pulse Width a count indicative of the desired width ol the throttle pulse
  • Vtarget 1152 Indicia of the desired rail output voltage
  • Itarget 1 Current target, indicia of the desired cunent level PHZFTR 1 156 Phase offset, phase factor subtracted from the zero crossing to establish the firing angles of the SCR's in single phase regulator 506 and contiol the supply voltages
  • CHHZFTR 1157 Phase offset, phase factor subtracted from the zero crossing to establish the finng angles of the SCR's in single phase regulator 506 and control the supply voltages
  • SH ⁇ TCNT 1 160 A count indicative of the shifting position of SHIFTREG 1 158
  • AC CNT 1 162 Count representative of the cycle (instantaneous phase) of AC output signal 532 of inverter 530
  • T2 1 166 A count indicative of a half cycle of the output frequency of inverter 530
  • microcomputer 902 is interrupt dnven, vanous interrupt signals are generated in response to predetermined conditions to effect predetermined functions
  • the interrupts set forth in the following Table 2 are generated in the prefened embodiment Table 2
  • IRQO Reference ramp voltage at pin 10 Update measurement of sensor output exceeds sensor voltage applied at voltage provided by first set of analog microcomputer pin 8 (comparator switches 518 to pin 8 (Rvolt or Cvolt). 1)
  • IRQ2 Reference ramp voltage at pin 10 Update measurement of sensor output exceeds sensor voltage applied at voltage provided by second set of microcomputer pin 9 (comparator analog switches 518 to pin 9 (ISEN or 2) Tvolt).
  • IRQ4 Timer 0 time out (e.g., every 130 Selectively generate SCR control sec) signals: update finng angles for SCR's, update inverter switching control signals
  • IRQ5 Timer 1 time out (e.g., every 8.2 If in cunent mode: adjust finng angle msec) of SCR's to vary voltage to maintain constant cunent value.
  • vanous subroutines may be employed. Use of subroutines is particularly advantageous in instances where hardware registers are employed, to facilitate page changing. Exemplary subroutines are descnbed in Table 3
  • Inverter Update #2340 Update status of inverter switching control signals LHRL. RHLL, HP/
  • ZEROX #2400 Zero (0) Crossing Detector: Detects zero crossings, determines RPM, and sets the phase angle employed to set finng angle
  • Throttle #2900 Sets the throttle pulse width in accordance with RPM and rail voltage
  • Push Button #2800 Updates the status readings on the push button input switches 520 to determine modes and set parameters for voltage and cunent
  • Power Out #2700 Updates the phase factor (finng angle) in accordance with the rail voltage when in voltage mode, and updates the SCR enable word in accordance with cunent output when in the cunent mode
  • Se ⁇ al Output #2500 Generates a serial output in accordance with data contents of the SCR control registers
  • Microcomputer 902 suitably operates in a continuous pnmary loop (simple race track) program for implementing the generation of the ramp reference voltage
  • Other functions are dnven by the interrupts set forth in Table 2.
  • vanous timers, registers, ports, and designated variables e.g., throttle pulse width, throttle pulse width minimum and maximum values, first cycle flag, inverter switching times Tl . T2, T3, T4 are initialized (Step 1202).
  • microcomputer 902 effects a continuous pnmary loop to generate the ramp reference voltage used to develop indicia of the sensed external parameters (e.g., rail voltage, output cunent. etc.), and increment POINT in register 1120 to cycle through the vanous sensed parameters (through the addressees of analog MUX's 516, 518), applying each to microcomputer 902 in successive cycles.
  • the sensed external parameters e.g., rail voltage, output cunent. etc.
  • the ramp difference voltage is generated by developing a count in counter 908. and applying that count to resistive ladder 912.
  • a controlled ramp voltage ranging from zero to 5 volts is thus generated and applied at pin 10 of microprocessor 902.
  • a commensurate analog to digital conversion count A to D is maintained in register 1102. More specifically, the A to D count in register 1102, is incremented, and a clock signal to counter 908 generated at pin 4 of microcomputer 902 (Step 1204).
  • the A to D count suitably runs from zero to 256, then rolls over to zero. (Counter 908 similarly rolls over.) Each time the A to D count is incremented, the count is tested to determine if a roll over has occuned (Step 1206).
  • a pointer to the analog switches to be actuated is maintained as universal variable POINT in register 1120.
  • a single pointer is used to, in effect, provide for relative addressing within each group of switches (MUX; the contents of the point register arc used to derive the bit patteni provided to register 906 and presented as control signals (ANALOG 1 -AN ALOG4; Figure 9) to switch sets 516 and 518.
  • the respective sensors in a group are coupled to microcomputer 902 in sequence. Accordingly, analog channel pointer POINT is incremented (Step 1208).
  • a measurement of the parameters selected from the first group of parameters is effected in response to each IRQO interrupt.
  • a measurement of a selected parameter from the second group e.g., DC output cunent ISEN, temperature Tvolt or AC cunent lac
  • the IRQO interrupt is generated when the reference ramp at pin 10 of microcomputer 902 initially exceeds the indicia of the selected first group parameter at pin 8 during the reference ramp cycle.
  • the IRQ2 interrupt is generated when the reference ramp initially exceeds the indicia of the selected second group parameter at pin 9.
  • the A to D count in register 1 102 is indicative of the sampled value of the sensed parameter.
  • various of the parameters e.g., Rvolt, Cvolt, Vac
  • IRQO and IRQ2 Suitable sensor comparison interrupt (IRQO and IRQ2) routines are described in copending application Serial No. 08/370,577.
  • control signals to the respective SCR's of regulators 502 and 506 are generated as a serial data stream, captured by the appropriate serial input parallel output register 904 and 905 (and 907) which provide the control signals to the SCR's (and inverter 530).
  • the states of the SCR's are controlled in accordance with the instantaneous phase of the cycle (rotor rotation), and, depending upon whether the system is in cunent mode and/or voltage mode operation, deviations of the system output signal cunent and/or voltage from respective target values (Itarget in register 1 1 4 and Vtarget in register 1 152)
  • cunent mode operation SCR's conesponding to respective coils are activated or do-activated to provide a desired level of cunent
  • the finng angles oi the SCR's are va ⁇ ed to control voltage output Switching control signals for inverter 530 (e g , LHRL, RHLL, HIV) and enable signals for the respective inverter winding groups 400A, 400B are likewise generated as a serial data stream, captured by the approp ⁇ ate se ⁇ al input parallel output register 907 which provides the control signals to invertei 530
  • the states of the switching control signals are controlled in accordance with count AC CNT representing the instantaneous phase of the AC
  • the desired status of the SCR's, reflected in the SCR control word registers 1 1 16 and 1 1 18 (and desired status of the inverter switching control signals, reflected in the lower nibble of register 1 125) are updated and output signals to the SCR's refreshed on a periodic basis, suitably at 130 microsecond intervals in response to the timer zeio interrupt
  • timer zero interrupt routine 1300 is effected in response to the timing out of timer zero on a penodic basis, e g , every 130 microseconds
  • a count RPM indicative of the rotor cycle phase is maintained in registei 1 1 12, and counts indicative of the relative points in the cycle when the respective phases of the stator windings should be rendered conductive are maintained in registers 1 130, 1 132, and 1 134
  • the firing phase counts in registers 1 130, 1 132, and
  • control registers 1122 and 1 124 update After the status of control registers 1122 and 1 124 update has been completed for all three phases, the status of the bits conesponding to the SCR's associated with control winding 504, e g ,
  • SCR's 13 and 14 are updated. More specifically, the control of control count register 1 1 6 is checked to determine if it is negative, indicative of the negative half of the cycle (Step 1302) If the control count is negative, the bit of SCR control register 1 124 corresponding to SCR 13 is turned on and the bit in SCR control register 1124 conesponding to SCR 14 is turned off (Step 1322) If the control count in register 1 136 is not negative, the control count is checked to determine if it is equal to zero (Step 1324) and if so, the bit in SCR control register 1124 conesponding to SCR 14 is set and the bit conesponding to SCR 14 is turned off (Step 1326) After SCR control register 1 124 has been updated with respect to the desired status of SCR's
  • SCR contiol registers 1122 and 1124 contain a bit pattern conesponding to the desired states of the various SCR's in regulatois 502 and 506
  • Inverter update subroutine 1 40 is then effected to update the contents of inverter control register 1125 Refernng briefly to Figures 14 and 8, AC cycle count AC CNT in register 1 162 is incremented (Step 1442), then tested against respective counts corresponding to Tl, T2, T3 and T4 in
  • Step 1452 CNT count cleared (Step 1452), then a return effected (Step 1448) If AC CNT equals T3 (conesponding to the loading edge of the boost pulse) (Step 1454) the bit in register 1 121 (Step 1456) and a return effected (Step 1448) If AC CNT is equal to T4 (conesponds to the trailing edge of the boost pulse) (Step 1458), the bit conesponding to HiN is reset to 0 (Step 1460) and a return effected (Step l448) If AC CNT is not equal to any of counts Tl , 12, T3, or 14, a return is effected (Step 1448) without changing the state of any of the switching control signals
  • the ZEROX signal provided by zero crossing detector 512 to pin 2 of microcomputer chip 902 changes logic level in accordance with the polanty of the signal generated by control winding 504 Since control winding 504 is physically wound with one of the phases (e g , phase 3) of a winding group 400, winding the respective conesponding phase windings of each group are in phase with each other)
  • the indicia of zero crossings (transitions in the state of ZEROX) generated by zero crossing detector 512 can thus be utilized to derive the relative phases of the respective windings of groups 400 as well as control winding 504 Accordingly, refernng again to Figure 13, the state of the ZEROX input at pin 2 of microcomputei chip 902 is sampled, to determine if a zero crossing has occuned (Step 1 27) to initiate the resetting and updating of the phase counts, as appropnate
  • zero crossing subroutine 1500 is effected (Step 1330) to reinitialize and update the firing angle counts for each of the respective phases contained in registers 1130-1 136, and the firing angle count for control winding 504 contained in register 1 136 and initialize the RPM count in register 1 112.
  • Zero crossing subroutine 1500 will be more fully explained in conjunction with Figure 15. If no zero crossing is detected, or if the 1/2 cycle bit indicates the wrong variety of zero crossing, the ZEROX value is loaded into the 1/2 cycle flag (Step 1331). The RPM count in register 1 112 and is incremented and the firing phase counts in registers 1130-1 136 and throttle control count in register 1 151 decremented (Step 1332) to reflect the advance in rotor cycle phase.
  • Serial output routine 1600 is then called to output the updated contents of the SCR control registers 1 122 and 1 124 to serial input parallel output registers 904 and 905 (Step 1 34). A return is then effected (Step 1336).
  • zero crossing subroutine 1500 is effected (Step 1330) to reinitialize and update the firing angle counts for each of the respective windings contained in registers 1 130-1 136, at the end of each cycle and reset the RPM count in register 1 1 12.
  • Step 1330 zero crossing subroutine 1500 is effected (Step 1330) to reinitialize and update the firing angle counts for each of the respective windings contained in registers 1 130-1 136, at the end of each cycle and reset the RPM count in register 1 1 12.
  • the first cycle flag (register 1 142 bit 6) is checked (Step 1502).
  • the first cycle flag was initialized to zero during start-up (Step 1202) and is set to one only after the zero crossing routine has been initiated. Accordingly, if the first cycle flag is not zero, the system has completed at least one complete cycle, and the RPM count in register 1 1 12 represents the period of the rotor cycle.
  • the respective counts are then adjusted to reflect the desired firing angle (Step 1510). More specifically, the phase factor PHZFTR, representing the offset from zero crossing necessary to achieve the desired phase winding firing angle, is contained in register 1 156, and is subtracted from each of the firing phase counts in registers 1130-1 136. Similarly, the phase factor CPHZFTR, representing the offset from zero crossing necessary to achieve the desired control firing angle, is contained in register 1157, and is subtracted from each of the firing phase count in register 1 136.
  • Step 1512 After the updated firing angles have been established in registers 1 130-1 136, the RPM count in register 1 1 12 is cleared in preparation for tracking rotor phase and through the next cycle, and the first cycle flag set (Step 1512), and a return effected (Step 1514). If, when the zero crossing subroutine is initially called, the first cycle flag is zero (Step 1502), indicative of an initial, possibly incomplete, cycle, the RPM and phase count updating (Steps 1504-1510) are by-passed; the RPM count in register 1 1 12 is cleared, and the first cycle flag set (Step 1512) in preparation for tracking rotor phase through the next cycle, and a return effected (Step 1514).
  • microcomputer 902 cooperates with serial-input-parallel-output registers 904-907 to generate control signals to the SCR's of regulators 502 and 506, analog switches
  • a desired bit pattern is serially provided on one of the output pins (e.g., pin 1 ) of microcomputer 902 and applied at the data inputs of all of the output registers.
  • Serial data clock signals (SCLK) synchronous with the serial data are provided only at the output pin (e.g., one of pins 15-17) conesponding (coupled) to the particular register 904-907 conesponding to the destination device. Thus, the data is loaded into only the appropriate register.
  • a subsequent control signal (RCLK) is provided at pin 12 of microcomputer 902 and applied concunently to each of registers 904-907 to load the accumulated pattern into an output latch, and hence, apply the bit pattern as control signals to the designated recipient devices.
  • Serial output routine 1600 is employed to transfer the updated contents of SCR control registers 1 122 and 1 124 to serial-input-parallel-output registers 904 and 905 on a periodic basis (Step 1334), here, every 130 microseconds in response to the TIMER 0 interrupt. More specifically, referring to Figures 16A and 16B, output shift register 1158 is initially loaded with the contents of SCR control register 1122, conesponding to the desired states of SCR's 1 -8 and the byte (register 1 142 bit 7) is set to 0, indicating operation upon the first byte of the control word (Step 1602). The carry flag of processor 902, typically maintained in a fixed function flags register 1036
  • Figure 10 provides indicia of whether shifting the contents of output register 1 158 causes a one to carry, i.e., the bit shifted out of the least significant bit of the register is a one.
  • the carry flag is initially cleared (Step 1604).
  • the contents of output shift register 1 158 are then shifted right, causing the least significant bit of output shift register 1 158 to be reflected in the state of the carry flag (Step 1606).
  • a count indicative of the number of bits are shifted out of the output shift register is maintained in shift count register 1160. After the shift right operation is effected, shift count register 1 160 is incremented (Step 1608).
  • the Sclock signal to the appropnate one of registers 904, 905 or 907 is generated More specifically, BYTE (register 1142 bits 6, 7) is checked (Steps 1616A, 1616B, 1616C) If the byte is zero, indicating SCR control register 1122 (conesponding to SCR's 1-8), the output pin, e g , p 15, conesponding to the Sclock input of conesponding register 904, is pulsed high, then low, to cause the data bit to be shifted into register 904
  • Step 1704 to capture user input through push button input switches 520, determine and store indicia of the desired mode of operation (Op 0,1 , in flag register
  • Vanous parameters are then set to predetermined values in accordance with the designated mode of operation
  • a multi-mode welder could opei te in one of three different modes ARC (stick), metal inert gas (MIG) (wire feed) and tungsten inert gas (TIG)
  • ARC stick
  • MIG metal inert gas
  • TIG tungsten inert gas
  • the desired mode of operation is input by the operator through push buttons 520 and, at this point, reflected in the I and V mode flags (FLAG 1 register 1 142 bits 0, 1 ) and in bits 0 and 1 of OLDPBTN register 1146
  • I and V mode flags FLAG 1 register 1 142 bits 0, 1
  • OLDPBTN register 1146 For example, ARC, TIG, and MIG operation are suitably designated by cunent and voltage flag (I, V) settings of 1 1 , 01, and 10, respectively
  • the mode prior to the last read cycle is reflected as MODEREG in register 1 143
  • bits 0 and 1 of OLDPBNT are tested against bits O and 1 of MODEREG to determine if there was a change in the desired mode (Step 1708) If a change in mode is detected, OLDPBNT in register 1 146 is loaded into registei 1 143 as MODEREG (Step 1710), then checked against the values conesponding to ARC, (e.g., 1,1), TIG (e.g., 0,1) and MIG (e.g., 1,0) (Steps 1712, 1714, and 1716), and the Itarget and Vtarget values in registers 1152 and 1 154 set to initial values accordingly, for example, as set forth in Table 4 (Step 1718)
  • ARC e.g., 1,1
  • TIG e.g., 0,1
  • MIG e.g., 1,0
  • TIG (0,1 ) 0 1 10 10-300 30 15-30
  • Steps 1720, 1722, 1724, 1726 determinations are made as to whether adjustments to target voltage or cunent are indicated, l e , an unserviced depression of the increment button, or decrement button has occuned (Steps 1720, 1722, 1724, 1726), and the Vtarget and/or Itarget values in registers 1 152 and 1 154 incremented or decremented accordingly by a predetermined unit amount, e g , conesponding to ten amps or ten volts (Steps 1728, 1730, 1732, 1734) More specifically, the state of the voltage mode, decrement and increment flags aie tested (Steps 1720, 1722), and Vtarget in registei 1152 ad j usted accordingly (Steps 1728, 1730) The state of the cunent mode, decrement and increment flags are then tested (Steps 1724, 1726), and Vtarget in register 1 154 adjusted accordingly (Steps 1732, 1734
  • the indicia of measured temperature is compared against indicia of a maximum permitted operating temperature (suitably a predetermined value incorporated into the program) (Step 1736) and the indicia of measured AC output cunent (lac, register 1 1 10) is compared against indicia of a maximum permitted AC cunent (Step 1737) If the temperature or AC cunent has exceeded the maximum values, SCR enable registers 1 126 and 1128 are cleared, to effectively disable operation
  • Step 1740 when an impending over-cunent condition is sensed, the output voltage is decreased to a predetermined value (zero in the example of Figures 17A and 17B), then gradually increased until the desired operating level is reached (or another over-cunent condition is sensed)
  • the particular bits in SCR enable registers 1 126 and 1 128 toggled in steps 1808 and 1810 can be chosen in accordance with a pre-determined algonthm to ensure that no particular winding group is used significantly more or less than the others, and to evenly distribute heat generated in the stator, and or control noise.
  • the finng angle PHZFTR in register 1 156 is adjusted as appropriate.
  • Step 1820 the size of the adjustment increment can be varied with RPM over a range of e.g., 1 to 10 degrees.
  • Steps 1822, 1824 and the phase factor count in registei 1 157 adjusted accordingly If it is determined that the measured value of control voltage (Cvolt) is greater than the desired voltage level (e.g., 2GV) (Step 1822), the count indicative of the firing angle in register 1 157 is decremented by a pre-determined unit amount (e.g., conesponding to 10 degrees) to decrease the finng angle (Step 1826) Conversely, if it is determined that the control voltage (Cvolt) is less than the desired voltage, e.g. 20V (Step 1 24), the phase factor count in register 1 157 is incremented to increase the firing angle and thus increase voltage (Step 1828). If desired, the size of the adjustment increment can be varied with RPM over a range of e.g., 1 to 10 degrees.
  • the inverter system is adjusted to maintain a desired AC cunent level. More specifically, the indicia of AC cunent level (lac) maintained in register 1 1 10 is compared against a predetermined desired AC current value Itac (suitably a predetermined value incorporated into the program) (Steps 1830 and 1832) If the indicia cunent value is less than target cunent Itac, the number of winding groups 400A 400B in the operative circuit is increased (Step 1834), a predetermined number of, e g , at least one additional bit in upper nibble of register 1 125 (preferably pairs of bits conesponding to a cooperating pair of windings 400A, 400B) is toggled from zero to one, to enable operation of regulator Conversely, if the indicia cunent value lac is greater than desired value Itac (Step 1832), the number of, e g , at least one additional bit in upper nibble of register 1 125 (preferably pairs of bits conesponding to a
  • engine speed control is suitably effected in accordance with load rotor RPM is suitably maintained at tht lowest value necessary to provide the desired rail voltage to the load
  • Rotor RPM is controlled by varying the pulse width of the signal provided at pin 3 of microcomputer 902 to driver 914 That pulse width is established by the value of TPW in register 1 1 0 Changes in load are reflected as a variation of the values of the DC rail voltage Rvolt and AC output voltage Vac from predetermined taiget values e g , Vtarget and Vtac
  • the load decreases, the output voltages tend to become less than the target values, and the RPM may be lowered, I e the pulse width of the signal provided to throttle dnver 914 is decreased
  • the increased load requires that the RPM be increased, i e the pulse width of the signal provided to driver 914 is increased This is effected through
  • Step 1900 the indicia of Rail voltage (Rvolt) in registei 1 104 is tested against, e g Vtarget in register 1 152 (Step 1902)
  • Vtarget is initially set in accordance with the selected welding mode (see Table 4), and thereafter adjusted by depressing the increment and decrement buttons
  • the indicia of AC voltage (Vac) contained in registei 1 107 is likewise tested against a predetermined value, e g , Vtag (suitably a predetermined value incorporated into the program) (Step 1904)
  • the throttle pulse width indicia (TPW) in register 1 150 is tested against a predetermined maximum (suitably a predetermined value incorporated into the program code) (step 1906), and so long as the pulse width has not reached the maximum value, the pulse width TPW is incremented by one predetermined unit, (Step 1908), the updated TPW value in register 1 150 is loaded into the pulse width counter 1151 (
  • Step 1914, 1916 If neither the DC rail voltage or AC voltage are greater than the conesponding desired values, a test is effected to see if the loads have decreased, l e , the DC rail voltage or AC voltage has increased to above the conesponding target value (Steps 1914, 1916) If the DC rail voltage or AC voltage is greater than the conesponding target value, the throttle pulse width is deci eased, down to a minimum value The indicia of throttle pulse width contained in register 1 150 is tested against the predetermined minimum value (again, suitably hard programmed) (Step 1918), and, if greater than the minimum, decremented by a predetermined unit value (Step 1920) The updated TPW value is then loaded into TPWCNT register 1 151 (Step 1910) in preparation for the next output cycle (Steps 1332, 1630-1634) and a return effected (Step 1912) Throttle control can be effected, if desired, as a function of either DC rail voltage or AC voltage alone
  • engine speed is controlled by varying the physical angle of a throttle plate or valve pivotally mounted in the engine carburetor (or in connection with a fuel injection system), the larger the angle of the plate, the larger the opening of the throttle, and the faster the speed ( ⁇ m) of the engine
  • the plate angle is manually adjusted by movement of a lever arm linked to the plate
  • Movement of the lever arm is sometimes effected using a cable cooperating with another (more easily accessible) remotely located lever
  • the throttle control apparatus 34 suitably compnses an electro-mechanical actuator, responsive to control signals applied thereto, for controlling the setting of the engine
  • a throttle control 34A responsive to the pulse width of the control signals applied thereto, comprises a cylindrical magnet 2000, magnetized through the length, suitably formed of Alnico, cooperating with a non-magnetic push rod 2002, for example, formed of nylon, and a winding 2001 wound around a suitable core, e g , formed of cast nylon Push rod 2002 cooperates with throttle lever arm 2003
  • Throttle lever arm 2003 typically cooperates with the carburetor (not shown in Figure 20) of the engine
  • a spring 2006 biases throttle arm 2003 into an idle position
  • a cunent path is formed through winding 2001 causing magnetic interaction with cylindrical magnet 2000.
  • the magnetic interaction between coil 2001 and magnet 2000 causes magnet 2000 to move forward ( Figure 20B) against the bias of spnng 2006, throttling up (increasing the RPM) of engine 14.
  • the control signal generated at pin 3 of microcomputer 902 is suitably pulse-width modulated. The wider the pulse width, the more power to coil 2001, and concomitantly, the greater the movement of magnet 2000, push rod 2002, and throttle arm 2003. If desired, a fly-back diode 2004 can be provided across coil 2001.
  • throttle control can be effected using a conventional stepping motor mechanically coupled to the engine throttle.
  • a conventional step motor 3300 typically comprises a rotor 3302, coupled to a shaft 3304, cooperating with respective coils 3306, and 3308.
  • Rotor 3302 includes a predetermined number of poles, preferably formed of permanent magnets. Windings, provided power through a conventional slip ring or brush mechanism, can also be utilized.
  • the number of poles establishes the resolution of the stepper motor.
  • a typical stepper motor includes e.g., 48 poles. While schematically shown in Figures 33A, and 33B, coils 3306, and 3308, are suitably disposed on a soft magnetic core 3310.
  • Core 3310 suitably includes a crenelated inner periphery with a predetermined number of equally spaced teeth and slots (generally analogous to core 302 of Figures 3 and 4). The number of slots are equal to a predetermined multiple of the number of poles of rotor 3302, with at least one slot per pole.
  • two separate soft magnetic cores disposed in planes parallel to rotor 3302, having with teeth extending axially from the periphery of the core, about the periphery of rotor 3302.
  • the teeth of the respective cores are interdigitated.
  • Coils 3306, and 3308 are wound about alternating teeth (or groups of teeth corresponding to a rotor pole,) of their associated cores, and present alternating polarities to the rotor poles.
  • Incremental rotation of rotor 3302 is effected by effecting cunent paths through coils 3306 and 3308 in predetermined sequences to generate magnetic fields which interact with the magnetic components of rotor 3302, and cause rotor 3302 to move in predetermined increments.
  • the poles of rotor 3302 tend to move into alignment with the coils through which cunent is flowing.
  • coils 3306 and 3308 each include a center tap, typically connected to positive supply voltage (e.g., 15 V).
  • Drive circuit 3314 suitably comprises conventional switching devices 3402, 3404, 3406 and 3408, operating in accordance with control signals from controller 22, disposed to selectively complete a cunent path from each end of windings 3306 and 3308 to ground.
  • each of coils 3306, 3308 is connected to switching devices 3402, 3404, 3406 and 3408, each suitably comprising a transistors with collector effectively connected to a respective end of a stepper motor winding (3306, 3308) and emitter connected to ground Transistors 3402-3408 are selectively rendered conductive by control signals from controller 22 applied (at terminals 3412-3420) to the bases of the transistors When rendered conductive by the control signal from controller 22, the transistors selectively effect a cunent path through the associated coil 3306-3308 If desired, fly-back diodes can be provided
  • step motor 3300 is operated either in a single activate winding (low power) mode or in paired winding (high torque) mode
  • respective cunent paths are effected, in sequence, to incrementally advance the rotor by a full step, from pole to pole
  • the rotor pole is forced to a position midway between the stator poles Accordingly, if pairs of cunent paths are effected, in sequence, the rotor can be incrementally advanced by a full step, at full torque, from midpoint to midpoint
  • Such switching sequences in which the two halves of each winding are never energized at the same time, repetitively effected, effectively cycles the magnetic flux about the stator, and causes the rotor poles to incrementally advance, as the rotor poles align with the magnetic fields created by the instantaneous cunent flow through the coils
  • the winding center tap is not employed Instead, in addition to switching devices, 3402-3408 selectively connecting each end windings 3306 and 3308 to ground, a further set of switching devices, 3402'-3408' to selectively couple each end of windings 3306 and 3308 to the positive source, c g , 15 V, are provided Switching devices, 3402-3408, and 3402'-3408' cooperate as, in effect, double pole, double throw switches, with a center off position, which selectively effect cunent flows of selected polanty through the windings For example, the following switching sequence, in which only a single winding is energized at any given time, incrementally advances the rotor by a full step, from stator pole to stator pole
  • the torque versus position curve is the sum of the torque versus position curve for one or the other winding (assuming that no part of the magnetic circuit saturates)
  • the two curves will be T degrees out of phase, and if the cunents in the two windings are equal, the peak of the sum will be displaced T/2 degrees from each and the amplitude of the sum will be 1 414 times the amplitude of the two components
  • the present inventors have determined that in the context of a throttle control system, that the effective resolution, l e , number of steps, from the perspective of the controlled engine, can be multiplied by dithering (switching back and forth) between successive coil actuation states in the rotation sequence, at a rate faster than the mechanical response time of the rotor (as coupled into the overall system) but less than the inductive ⁇ se time of the stepper winding, the engine reacts as if the throttle was at a setting equal to the average setting over the response period of the engine If the dithe ⁇ ng frequency, i e , the rate at which the activation control signals applied to switches 3402-3408 (and 3204 -3408', if employed) are switched, exceeds the inductive rise time of stepper windings 3306,
  • the motor unable to react to the activation currents, loses torque
  • the switching frequency is less than the inductive rise time of the stepper winding, but exceeds the response time of the engine (e g , between 10 microseconds in smaller engines, and 25 to 5 seconds in iarger engines)
  • the effective throttle setting, as perceived by the engine is the position conesponding to the average of the activation states over the pe ⁇ od
  • the frequency is less than the time constant of the system linkage (rotor as connected in the system), but exceeds the response time of the engine, the throttle tends to move between positions corresponding to the iespective actuation states at the dithe ⁇ ng frequence
  • the engine is unable to respond to the throttle movement and perceives the throttle as being in the average position
  • the same averaging effect can, however, be attained without physical oscillation of the throttle plate If the switching frequency exceeds the time constant of the system linkage, l e , the rotor as connected in the system,
  • the throttle can readily, and without additional hardware, be adjusted in steps equivalent to one quarter of angle subtended by the poles of rotor 3302, by dithe ⁇ ng for equal periods between successive coil actuation states More specifically, what would otherwise be a "half-step" activation state sequence employed in a 48 pole step motor, results in a resolution of 3 75°, dithe ⁇ ng at an appropriate frequency between activation states (for equal penods) results in an effective resolution of 1 875° For example, the activation state sequence for a unipolar configuration employing dithe ⁇ ng would be
  • a plurality of intermediate positions can be effectively attained by varying the relative time penods during which the respective coil activation states are maintained For example, in a 48 pole step motor, a resolution of 0 9375° can be achieved, again without any additional hardware, with the following activation sequence
  • a mechanical linkage or cam dnve may be employed
  • a mechanical linkage providing two-to-one resolution, l e , throttle shaft moves one degree for every two degrees rotation of step motor shaft 3304 suitably comprises a step motor actuator arm 3602, a linkage rod 3604 and a throttle actuator arm 3608
  • Step motor actuator arm 3602 is mounted for rotation with, and extends radially outward from step motor shaft 3304
  • throttle actuator arm 3608 is mounted for rotation with and extends radially outward
  • a cam d ⁇ ve for providing in excess of five to one resolution, I e , 70 degrees of throttle actuator arm rotation is effected in response to 360 degrees of step motor shaft rotation, suitably comprises a cam actuator 3702, and cooperating cam follower throttle actuator arm 3704
  • Cam actuator 3702 is mounted for rotation on the step motor shaft 3304 and includes a pe ⁇ pheral side cam surface 3702A, suitably configured to effect throttle movement conesponding to a linear engine response
  • Cammed throttle actuator arm 3704 similarly includes a penphcral side cammed surface 3704A
  • Throttle actuator ami cammed surface 3704A rides on, preferably under spring bias (not shown), and cooperates with motor actuator cam surface 3702A Interaction between cam surfaces 3702A and 3704A causes actuator arm 3704 to turn in response to rotation of cam 3702 The progression of movement is illustrated in Figures 38A through 38E
  • a closed loop servo system can also be employed as throttle control 36
  • a suitable servo system 5900 comprises a conventional servo motor 5902, with positive and negative input terminals, connected in an H bndge with respective switching devices 5904, 5906, 5908, 5910, e g , MOSFET power switches Switches 5904-5910 are suitably selectively driven by a pulse width modulated (PWM) signal generally analogous to that described in connection with Figures
  • PWM pulse width modulated
  • a common PWM signal from microprocessor 22 is employed to drive switches 5904 and 5910. and inverted to drive switches 5906 and 5908
  • switches 5904 and 5910, and switches 5906 and 5908 provide alternative polanty cunent paths to motor 5902
  • switches 5906 and 5908 conductive dunng the low (zero) portion of the PWM signal
  • the PWM control signal would suitably be controlled using a conventional feedback loop, conecting in accordance with the difference between desired and actual voltage Initialization would suitably be effected by moving the motor in a single direction for a time penod sufficient to lodge the carburetor valve shaft against a stop
  • Servo motor 5902 is suitably coupled to the carburetor valve shaft by, for example, a belt dnve
  • power convertei 530 effects controlled application of the DC rail voltage(s) to output terminals LI and L2, in response to respective switching control sign-in-parallel output register 907
  • microcomputer 902 suitably cooperates with se ⁇ al-in-parallel output register 907 to generate respective switching control signals, e g , LHRL (Left High, Right Low), and RHLL (Right High, Left Low) to power converter 530
  • power converter 530 effects controlled application of the DC rail voltage(s) to output terminals LI and L2
  • microcomputer 902 and register 907 cooperate to generate, (at pins QO and Ql of register 907), respective alternative pulses of controlled pulse-width, relative timing, and repetition rate as switching signals LHRL and RHLL
  • Microcomputer 902 and register 907 may also generate, if desired, further a switching signal HIN (High Voltage) (at pin Q2 of register 907) to power converter 530 to effect advantageous shaping of output signal
  • Power converter 530 in response to switching control signals I HRL and RHLL, (or T_L B_L T_R, and B_R and/or further switching signal HIV if utilized) selectively applies DC voltage(s) to terminals LI and L2 of outlet 534 to generate output signal 532 with a predetermined waveform
  • power conversion circuit 530 suitably comp ⁇ ses, in a basic form 2100 respective high-side power switch circuits 2102 and 2104, and respective low-side power switch circuits
  • High-side power switch circuits 2102 and 2104 and low-side power switch circuits 2106 and 2108 each include a power transistor (Ql , Q2, Q3, and Q4 respectively) and a suitable finng circuit (21 12, 21 14) for turning the power transistor on and off in accordance with switching signals LHRL and RHLL High-side power switch circuits 2102 and 2104 are preferably isolated and low-side power switch circuits 2106 and 2108 are preferably non-isolated
  • Power switch circuits 2102-2108 are interconnected in an Hconfiguration high-side power switch circuits 2102 and 2104 define controlled cunent paths between a high-side terminal 2103 (e g , the juncture of the drains of power transistors Ql and Q2) and output terminals LI and L2, respectively, and low-side power switch circuits 2106 and 2108 define controlled current paths between a low-side terminal 2107 (e g , the juncture of the sources of power transistors Q3 and Q4) and output terminals LI and L2, respectively.
  • high-side terminal 2103 e g , the juncture of the drains of power transistors Ql and Q2
  • low-side power switch circuits 2106 and 2108 define controlled current paths between a low-side terminal 2107 (e g , the juncture of the sources of power transistors Q3 and Q4) and output terminals LI and L2, respectively.
  • high-side terminal 2103 is connected to a positive DC source of predetermined nominal voltage (+150 V) and low-side terminal 2107 is connected to a relatively negative potential, e.g., negative rail 501 C (and through isolation diode D7 to system ground).
  • the positive DC source may be e.g., a signal derived from intermediate DC rail 501B, or, preferably, separate inverter rail 544.
  • Power switch circuits 2102-2108 effectively operate as an electronically controlled double throw, double pole switch, selectively connecting the DC source to terminals LI and L2 in response to switching control signals LHRL and RHLL (or, in various embodiments, separate independent signals to each power switch, e.g., Top_Left (T__L), Bottom_Right (B_R), and Top_Right (T_R), Bottom_Left
  • switching signal LHRL is applied to high-side driver 2102 and low-side driver 2108
  • switching signal RHLL is applied to high-side driver 2104 and low-side non-isolated driver 2106
  • switching signal T_L is applied to high-side driver 2102, B_R to low-side driver 2108, T_R to high-side driver 2104 and B_L low-side driver 2106.
  • LHRL (T_L, B_R) is of a predetermined state, (e.g., low)
  • highside terminal LI is connected by driver 2102 to high-side terminal
  • a particularly economical firing circuit 21 12 that provides advantageous turn on and turn off characteristics comprises: a resistor R13 (R16); an NPN transistor Q9 (Q10); a diode D2 (D3); a capacitor C4 (C2); and respective resistor R9 (R1 ) and R6 (RIO).
  • the level of the source voltage (15 volts) and the level to which capacitor C4 (C2) is initially charged, is chosen to initially place power transistor Ql (Q2) into a hard full conduction. However, once diode D2 (D3) is blocked, capacitor C4 (C2) begins to discharge through resistor R9 (R15).
  • the time constant of capacitor C4 (C2) and resistor R9 (R15) is chosen such that the charge on capacitor C4 (C2) (hence the gate voltage) approaches (is only slightly above) the threshold value of power transistor Ql (Q2) at the point in time when the associated control signal LHRL (RHLL) changes state.
  • converter 530 may derive power from one or more of DC rails 501 A and
  • Inverter winding groups 400A, 400B may be wound concunently on stator core 302 with the corresponding windings of winding groups 400
  • winding 400A, 400B would be independently controlled (by system 540), and may be operatively connected the system inespective of the status of the winding group 400 with which it is wound
  • Winding inverter rail windings 400A, 400B in the same physical space and in continuous thermal contact with DC rail windings 400 can piovide particulaily advantageous heat dissipation chaiacte ⁇ stics, the close proximity of the respective coils effectively makes the entire mass of the skein available to dissipate the heat generated by the working w ⁇ nd ⁇ ng(s)
  • inverter winding groups 400A, 400B may be respective ones of winding groups 400 Where a plurality of winding groups 400A, 400B are used, the groups are preferably disposed angularly equidistant about stator core 202
  • the regulators of inverter rail generation system 540 can, if desired (and microcomputer capacity permitting), substantially replicate regulatoi s 502, with the SCR's controlled in a manner analogous to the control of regulators 502 Alternatively- refening to Figure 22, the regulators of inverter rail generation system 540 may be ' self-liming regulatoi s 2202
  • a suitable self-timing regulator 2202 comp ⁇ ses a rectifier bndge 2204, a leve ⁇ ng capacitor C21 , a comparator 2206, and an opto-isolator 2208
  • Rectifier bridge 2204 is suitably formed of respective diodes D28, D29 and D30 and respective SCR's THl , TFI2, and TH3 Comparator 2206 suitably compnses transistor Ql 1 and a voltage divider formed of resistors R21 and R24
  • windings 400A and 400B can be utilized to cooperatively generate the desired voltage at high positive rail 544
  • windings 400A and 400B can be utilized to cooperatively generate the desired voltage at high positive rail 544
  • in such an anangement inding 400B would include a predetermined number of windings conesponding to the desired voltage at intermediate rail 544, and diode bndge 2302 would be te ⁇ osed between regulator 2302 and negative rail 501 C
  • a winding 400C, conesponding to winding 400A, but including a predetermined number of turns conesponding to the difference between the desired voltage at intermediate rail 544 and the voltage, e g , 150 volts, at positive rail 542 is provided
  • booster circuit 2500 is substantially identical to high side isolated power switching circuits 2102 and 2104, including an FET Q5, and an associated finng circuit Booster circuit 2500, however, is responsive to control signal HIN from controller 900 conesponding to pulse 808 (T3-T4) in Figure 8
  • the drain of booster circuit FET Q5 is connected to high voltage positive rail 542.
  • the source of the power transistor is connected through an isolation diode D3 to the drains of the power transistors Ql and Q2 in high side power switching circuits 2102 and 2104.
  • a reverse polarity fly-back diode D6 may be provided, if desired.
  • the abrupt edges of a typical square wave tend to generate significant harmonic signals which are dissipated in the windings as heat
  • the wave form provided by power converter 2700 avoiding the abrupt edges of a typical square wave generates significantly fewer harmonics
  • Power switch circuits 2702-2708 are, like power switch circuits 2102-2108 in the basic configuration of Figure 21 , interconnected in an H-configuration
  • High side power switch circuits 2702 and 2704 define controlled cun
  • Switched capacitor (filter) 2710 selectively couples a capacitance (filter) into the operative circuit only dunng a predetermined portion of the output signal cycle More specifically, refernng to
  • a simulated sine wave voltage waveform 2800 is generated by selectively actuating and deactuating power switch circuits 2702-2708 to controllably connect terminals LI and L2 to a DC source, and capacitive switch circuit 2710 to selectively vary the source voltage. More specifically, respective pulses 2802 (only one shown in entirety) of alternating polarity are generated, with an intervening dead time 2804.
  • Each cycle thus includes a first pulse 2802 of one polarity, an intervening dead time 2804, and a second pulse 2802 of the opposite polarity.
  • Dead time 2804 extends from the trailing edge of the first pulse, at time Tl , to the leading edge of the next successive pulse at time T2.
  • the associated set of high side and low side power circuits e.g., 2702 and 2708 or 2704 and 2706
  • switching circuit 2904 is, in effect, nonconductive, so that capacitance 2902 is effectively out of the operative circuit (and charging through diode 2906) i.e., capacitance 2902 is not within a complete cunent path relative to the high side terminal.
  • the signal provided across output signals LI and L2 is effectively the raw output of inverter rail generator 540, i.e., a full wave rectified signal combining the outputs of the respective phases.
  • the impedance apparent to the output terminals is effectively that of the alternator coils, e.g., an inductor at high frequency, e.g., 360 Hz.
  • the rising edge of voltage pulse 2802 is sloped, generally analogous to the rising edge of a true sine wave, as opposed to the abrupt rising edge of a square wave.
  • switching device 2908 is rendered nonconductive, effectively removing capacitance 2902 from the operative circuit that of a true sine wave is generated.
  • the operative power switch circuits are rendered nonconductive to provide a predetermined dead time 2804.
  • the operative low side power switch (2706 or 2708) can be rendered nonconductive slightly after (at time Tl) the operative high side power switch circuit (2702 or 2704), to accommodate lagging cunents caused by highly inductive loads such as motors.
  • phase differential may be as much as 30 degrees.
  • lagging cunents caused by inductive loads are accommodated by providing a path for the cunent flow occurring after the zero crossing in the voltage waveform. This is accomplished by maintaining the low side power switching circuit 2706 or 2708 conductive for a predetermined period (e.g., 3/32nds of the half cycle of the output signal) after the operative high side power switching circuit 2702 or 2704, is turned off. More specifically, the operative high side switching circuit, 2702 or 2704, is rendered non-conductive at time Tl . This effectively breaks the cunent path to the high side output terminal LI or L2, creating the dead time 2804 in the voltage wave form.
  • a predetermined period e.g., 3/32nds of the half cycle of the output signal
  • a current path is effected from high side juncture 2703 through power switch circuit 2702 to output terminal LI , through the inductive load (L) to output terminal L2, through low side switching circuit 2708 to low side juncture 2707).
  • power switch circuit 2702 is rendered non-conductive, effectively isolating output terminals LI and L2 from high side juncture 2703.
  • power switching circuits 2702-2708 suitably employ power MOSFET's.
  • Conventional power MOSFET's typically include an inherent high speed rectifier (diode). Where other types of switching devices are employed, a separate diode may be utilized. Such diode provides a return cunent path from low side juncture 2707 to high side output terminal LI, providing for a recirculating current, generally indicated as 3100 thus, cunent flow through inductive load L is not cut off at time T) (the zero crossing in the voltage wave form), and full advantage of the cunent is attained.
  • An alternative approach to discharging the capacitor is to create a resistive discharge path through the power switching devices, one or both of the power switches are rendered only partially conductive e g , operating in a linear operation mode, to thus present a resistance in the discharge path
  • at least one, and preferably both (for simplicity of control), of the high side switches is rendered fully conductive, and, at least one, preferably both of the low side power switching circuits are rendered partially conductive, e g , the power switching devices biased into a linear operation mode
  • the low side power switching circuits 2706, 2708 each suitably comp ⁇ se a switching device 3200, (analogous to switching device Q3 (Q4) of low side switching circuit 2106 (2108) of Figure 21), suitably a plurality of MOSFET s in parallel, a full conduction dnver circuit 3202 responsive to the Bottom_Left (B_L) (Bottom_R ⁇ ght (B_R)) control signal
  • a multi-purpose system 3900 suitably comprises: a first portion 3902 for generating the welding output signal at rail 3908; a power converter (e.g., inverter) section 3904 for generating the AC output signal (simulated sine wave) at an outlet 534; a regulated supply section 3906, for generating respective stable voltages for use by the various components of the system; a throttle control section 3908; and a controller 22.
  • system 3900 may also include an additional section 3915 for generating, e.g., a battery charging "boost" signal.
  • Welder output generating section 3902 suitably comprises a predetermined number, e.g., four
  • Power converter section 3904 suitably includes: a power converter 530; an inverter rail generator 540, a conventional outlet 534, and a suitable cunent sensor 3912 Power converter 530, in response to the control signals from controller 22 generates a simulated sine wave at outlet 534
  • Regulated supply section 3906 suitably compnses a single phase control winding 504 and cooperating single phase rectifier 506 (conesponding to coil 504 and rectifier 506 in Figure 5), a voltage sensor 4500, a conventional 15 volt regulator 4502, a conventional 5 volt regulator 4504, and a negative
  • Throttle control section 3908 suitably compnses a throttle driver circuit 3314, preferably of the type descnbed in conjunction with Figure 34, cooperating with a suitable throttle control mechanism 36, preferably of the type described in conjunction with Figures 33 and 35-38
  • a welder generates an open circuit voltage c g , 80 VDC, considerably in excess of that (e.g , 20 VDC) than can safely be employed for battery charging without nsk of damage to electronic equipment, such as ignitions, microprocessors in emission control systems, etc
  • battery charging section 3915 suitably comprises a separate group of multi-phase (e.g , 3-phase) windings 400, and multi-phase rectifier 3920 (e g , diode bridge) to generate appropriate voltage levels
  • rectifier 3920 is suitably formed using six switching devices, preferably power MOSFET's 6002-6012 cooperating with 3-phase coil group 400 on stator 18 of generator 16 If desired, a suitable battery Bl can be added across rectifier 3920 to provide an elect ⁇ c start capabi t)
  • conventional MOSFET devices typically include a parasitic reverse cunent diode Such diodes in effect form a three-phase, full wave bridge rectifiei to recharge battery Bl from cunent induced in coils 400 once engine is running
  • coils 400 in effect, cooperate with rotor 20 of generator 16 as a three-phase brushless starting motor (startet) Switches 6002-6012, undet control of microprocessoi 2910, in a manner generally analogous to the control of power converter 530, are selectively activated to create a six-step three-phase output to winding 400 from battery B 1
  • the signals through coils 400 magnetically interact with rotor 18 ( Figure 1 ), causing the engine shaft to rotate
  • controller 22 is receptive of various input signals, e g , Ra ⁇ l_Voltage, from rail geneiator 540, indicative of the magnitude of the inverter rail, Over_Cunent, from cunent sensor 3912, indicative of over-cunent conditions in the AC output,
  • System 3900 in the absence of contrary indications, suitably operates in an inverter mode Dunng normal inverter mode operation, controller 22 suitably generates control signals SCR to inverter rail generator 540 to effect pulse population modulation control of the rail voltage, in accordance with signal Rail Voltage, to maintain the inverter rail voltage at a predetermined value, e g , 135 volts or 150 volts Control signals T_L, B_R, T_R, B_L and CAP are generated to power converter 530 to effect generation of a simulated sine wave output signal at AC outlet 534 If an over-cunent condition is sensed, as indicated by signal Over_Cunent, power converter 530 is inhibited, a recovery mode operation is initiated Dunng recovery mode the rail voltage is lowered to a predetermined value, or by a predetermined amount, then power converter 530 re-enabled and the rail voltage gradually increased to normal operating levels Cap_Dump_R and/or Cap_Dump_L signals may be generated to dissipate the rail
  • power converter (e g , inverter) section 3904 generates a simulated sine wave output signal at AC outlet 534 More specifically, winding groups 400 cooperate with controlled b ⁇ dges 502 to supply respective DC signals on rails 3908 and 3910 As previously described in connection with Figure 5, rectifiers 502 provide a respective controlled current path associated with each winding Control signals SCR1-SCR12 are suitably provided to bndges 502 by welder control unit 3912
  • Welder control unit 3912 may be an integral part of a common controller 22 (e g , controller 3910) employed in connection with the vanous sections of the system, as was the case in the embodiment of Figure 5 Alternatively, welder control unit 3912 can comprise a separate controllei analogous to controller 22.
  • controller 3912 can be one of the various analog, or microprocessor based embodiments of control circuit described in parent application 08/370,577.
  • cunent sensor 3913 generates a signal.
  • Weld_Sense for application to controller 22 indicative of welding operations, as reflected by cunent flow in any of one or more of windings 400 a suitable cunent sensor 3913 is illustrated in Figure 43. If a particular winding is typically the first to be activated, and thus is always activated dunng generation of a welding output, sensor 3913 may detect cunent flow in that coil alone as indicia of welding operations. If the order of winding actuation is varied to facilitate heat distribution and/or noise control, welding operation would preferably be detected by sensing cunent flow in any of those windings 400 that might be first actuated.
  • a zero crossing detector 3914 in cooperation with a control winding 504 (as previously described in conjunction with Figures 5 and 6) is employed to generate a signal, ZEROX, indicative of the speed (and rotational phase) of the rotor (e.g., engine speed).
  • Regulated supply section 3906 generates respective stable voltages for use by the various components of the system and may comprise any circuit capable of generating such stable voltages. Preferably, such signals are derived from control winding 504.
  • regulated supply section 3906 suitably comprises single phase control winding 504 and cooperating single phase regulator 506 (conesponding to coil 504 and rectifier 506 in Figure 5), a conventional 15 volt regulator 4502, a conventional 5 volt regulator 4504, and a negative 5 volt generator circuit 4600
  • Resistor R3 develops a voltage indicative of the AC output cunent, which is integrated by capacitors C15 and C24. If the voltage accumulated in capacitors C15 and C24 exceeds a predetermined limit, transistor Ql 3 is rendered conductive, effectively pulling the Ovcr_Cunent signal to ground. As will be explained, the Over_Cunent signal is applied as a gating control to controller 22.
  • Inverter rail generator 540 may be any circuit capable of providing a suitable DC rail signal to power converter 530 (e.g., 135 VDC).
  • inverter rail generator 540 maybe of the type described in conjunction with Figure 5.
  • inverter rail generator 540 preferably employs a single three-phase winding group 400A, and cooperating three- phase controlled bridge responsive to a single control signal (SCR) provided by controller 22.
  • SCR single control signal
  • D7 provide isolation between the respective SCR's, preventing the finng of one SCR from feeding back and finng the other SCR's
  • controller 22 is suitably a microcomputer controller 3910, comp ⁇ sing a conventional microprocessor chip 4100, an R/2R resistive network 4102, generally analogous to R/2R network 912 of Figure 9, and a suitable gating logic circuit 4104 for disabling the respective power switch circuits in the event of an over-cunent condition
  • Microprocessor 4100 is suitably a 40 pm microprocessor including internal counters, registers,
  • RAM random access memory
  • ROM read-only memory
  • comparators capable of generating interrupt signals in response to external signals, such as a Zialog Z86E40 microprocessor
  • external signals such as a Zialog Z86E40 microprocessor
  • one or more of such components can be external to the microprocessor chip
  • Ra ⁇ l_Voltage indicative of the magnitude of the inverter rail voltage applied to pin 16.
  • a common teference signal for the comparators is generated by applying incremental count to resistive ladder 4102
  • the ramp voltage is applied to pin 18 of microprocessor 4100 for use as a reference voltage by the internal comparators
  • Over_Cunent assumes a low level (0) effectively grounding pin 18, and effectively inhibiting operation of R2R network 4102
  • only the rail voltage is compared against the reference ramp Counts indicative of the desired state of the respective switching circuits of power converter 530 are provided at, e g , pins 36, 37 and 38, for application to gating logic 4104
  • a count indicative of the desired throttle setting is provided at, e g , pins 19, 22, 23 and 24, for application to throttle control 3908
  • Output signals Cap_Sw ⁇ tch controlling the state of capacitor switching circuit 2710 ( Figure 27) and Cap_Dump to facilitate capacitive dumping, are provided at, e g , pins 39, 2 and 3 respectively,
  • BRDG.MSK 4620 H-bndge pattern bit pattern indicative of the desired state of the control signals to converter 530, e g , T_L, B_L, T_R, and B_R and further control signals Cap, and Cap_Dump, if utilized
  • RPM_TMBS 4622 Output Cycle Count in 8 2 ms increments (a count representing the number of half cycles of the converter output since the last 1 eneine speed measurement) 1 CYC.CNTR 4624 H-BRIDGE COUNTER (count indicative of the instantaneous phase of (number of incremental penods elapsed in) the present half cycle of the converter output signal)
  • PP_CNT 4626 SCR Regulator Clock (count indicative of the desired delay penod between SCR pulses to inverter rail generator 540 for pulse population modulation of the rail voltage, low count conesponds to short delay between pulses, hence high pulse population)
  • SW_HI 4630 (LDG) D_H ⁇ gh) (upper half of address of data st ⁇ ng representative of value output to step motor 3300)
  • SW_LOW 4632 (LDG) D_Low) (lower half of address of data st ⁇ ng)
  • WLD_MODE 4638 Weld Mode Counter (count indicative of the time elapsed since cessation of welding cunent (arc) used to provide for predetermined delay, e g , 4 seconds from the when an arc is broken before the throttle setting is permitted to vary) to facilitate resumption of welding after a short pause
  • P0 4640 Register with bits conesponding to microprocessor port 0 (P s 26, 27. 30. 34, 5, 6, 7, 10) output to R/2R network 4102
  • P2 4642 Register with bits conesponding to microprocessor port 2 (Pms 35, 36. 37. 38. 39. 2, 3. 4)
  • P3 4644 Register with bits conesponding to microprocessor port 3 (Pins 25, 16. 17. 18 19. 22. 24. 23)
  • IRQ2 Voltage Reference ramp voltage at p Update measurement of sensor output voltage Sense 18 exceeds sensor voltage Rail Voltage provided by sensor 4010 to p applied at microcomputer pin 16 16 (comparator 2)
  • IRQ3 (Over- low level Over_Cunent signal turn off converter 530, set pulse population to Cunent Sense) applied to microcomputer pin predetermined minimum 25 (Port 2, Pin 1)
  • IRQ4 Timer 0 Timer 0 time out (e.g., every Selectively generate control signals to effect Interval) 130 ⁇ sec) control of converter 530
  • Timer 1 time out e.g., every pulse population control Interval 8.2 msec
  • vanous subroutines may be employed. Use of subroutines is particularly advantageous in instances where hardware registers are employed, to facilitate page changing. Exemplary subroutines are descnbed in Table 15
  • IN ⁇ P Initializes position of throttle to predetermined position (e.g., against stop)
  • a to D Outputs 8-b ⁇ t count to R/2R network 4102 for generation of analog voltage ramp for application to microprocessor pin 18
  • a suitable initialization routine 4700 configures the microprocessor memory Step 4702; initializes the input and output ports of the microprocessor (Step 4704); initializes hardware counters as timer 0 and timer 1 (Step 4706): initializes the interrupts (Step 4708); initializes a first set of vanables relating to throttle control (Step 4710); calls a throttle initialization subroutine to ensure that the throttle begins operation in a predetermined position (Step 4712) (a suitable throttle initialization subroutine will be descnbed in con j unction with Figure 55); sets vanous other va ⁇ able values (Step 4714) then starts the timers and enables the interrupts (Step 4716).
  • Weld_Mode is a count indicative of the time elapsed since cessation of welding cunent (arc) used to establish a predetermined delay, e g , 4 seconds from when an arc is broken before exiting welder mode, to facilitate resumption of welding after a short pause If the content of Weld_Mode register 4638 is zero, the process jumps to a module (labeled Main 1 ) associated with inverter mode operation (Step 4804) as will be descnbed in connection with Figure 49
  • the engine speed measurement is updated (Step 4806) More specifically, the engine speed is averaged over a predetermined number of cycles, e g , 4 of the (AC) output of converter 530
  • RPM_TMBS in register 4622 is indicative of the number of half cycles of the converter output that have occuned since the last engine speed measurement
  • a ump is suitably effected (Step 4808) to a program module labeled Main, to update the A to D count in register 4610. if appropriate, as will be more fully descnbed in connection with Figure 49
  • RPM_CNT in register 4616 (indicative of the number of zero crossings occurnng dunng the four cycle penod) is loaded into RPM_Val as indicative of the measured RPM
  • Step 4810 Output cycle count RPM_TMBS and zero crossing count RPM_CNT in registers 4622 and 4616 are then cleared (Step 4812)
  • system 3900 engine speed is maintained within a predetermined band of values bounding a predetermined desired speed, preferably providing a ratio-metric conective response in accordance with the extent the engine speed deviates from the desired value Accordingly, after the speed measurement RPM_Val in register 4618 has been updated, as approp ⁇ ate, the engine speed is tested to determine if it is within predetermined limits of the desired engine speed for welding operations, e g , 3600 ⁇ m
  • an engine speed of 3600 RPM corresponds to a RPM_Val less than 31 hexadecimal (31 H), and more than 2A hexadecimal (2AH) (e g , 30H) If RPM_Val is greater than 31H the throttle is incrementally closed.
  • T_DLY_TMR Throttle Recovery Time Count
  • the delay timer may be, in effect, overndden
  • overndden For example, RPMJVal is initially tested against a number, e g , 34H, significantly m excess of the upper acceptable limits (Step 4814) If, e g , 34H is exceeded, T_DLY_TMR is set to zero (Step 4816), and the subroutine NEGDIR is called to effect an immediate incremental closure of the throttle (Step 4818)
  • the NEGDIR subroutine will hereinafter be descnbed in conjunction with Figure 54
  • RPMJVal is then tested against a predetermined count, e g , 32H conesponding to an intermediate speed in excess of the desired upper limit (Step 4820) If the engine speed exceeds the intermediate value, l e , RPMJVal is greater than 32H, the throttle delay timer is again overndden (cleared)(Step 4822), and the NEGDIR subroutine called (Step 4824) to effect an immediate incremental closure of the throttle
  • RPMJVal is then tested against a number conesponding to the upper limit of acceptable speeds, e.g , 31 H (Step 4826) If the upper speed threshold is exceeded, i.e., RPMJVal is greater than 31H, subroutine NEGDIR is again called to incrementally close the throttle (Step 4828) However, in this case, since the speed is not severely out of limits, the throttle delay timer function is not overndden If the engine speed is not above the upper acceptable limit, the speed is tested against the lower limit More specifically, RPMJVal is tested against a first predetermined number, e g , 2AH, conesponding to a speed considerably below the acceptable lower limit of speeds (Step 4830) If the speed is below the predetermined value, throttle recovery timer T_DLYJTMR is set to zero (Step 4832), and the POSDIR subroutine called to effect an immediate incremental
  • RPMJVal is tested against a predetermined number indicative of the lower acceptable limit of speeds, e.g., 2FH. If RPMJVal is less than 2FH, (Step 4842), the POSDIR subroutine is again called (Step 4844), but subject to the recovery timer.
  • the rail voltage is suitably controlled by pulse population modulation (varying the number of SCR pulses per unit time, and hence, rail voltage) so long as the pulse population count (PP_CNT) in register 4626 is within predetermined upper and lower limits (e.g., 08 and 2FH).
  • pulse population modulation varying the number of SCR pulses per unit time, and hence, rail voltage
  • the throttle setting is varied to adjust engine speed, in effect, shifting the band of rail voltages to which the pulse population counts conespond.
  • count PP_CNT in register 4626 is indicative of the desired delay period between SCR pulses to inverter rail generator 540 (e.g., a count of 08 indicates 8 microseconds between pulses); a low value of PP_CNT conesponds to short delay between pulses, and hence, high pulse population.
  • PP_CNT is suitably initially set, during initialization ( Figure 47) to a value (e.g., 7FH) in the center of the permissible range.
  • pulse population count PP_CNT is tested against the predetermined minimum value (e.g., 08) indicative of the minimum threshold time between pulses (highest pulse population) (Step 4902). If pulse population count is below the predetermined limit, the POSDIR subroutine is called to incrementally increase engine speed (Step 4902).
  • Step 4906 a program module relating to coordinating sampling the rail voltage with the operation of switched capacitor 2710 as will be described in conjunction with Figure 49B.
  • pulse population count PP_CNT is greater than the predetermined minimum, it is then tested against a predetermined maximum, e.g., 2FH (indicative of a predetermined maximum delay between pulses, i.e., minimum pulse population) (Step 4908). If PP_CNT is greater than, e.g., 2FH, the predetermined maximum, e.g., 2FH, the
  • NEGDIR subroutine is called to incrementally close the throttle to decrease the rail voltage (Step 4910).
  • Step 4912 the main module, in effect, synchronizes sampling of the inverter rail voltage with the operation of switch capacitor (filter) 2710; the A to D ramp voltage is suspended (not increased) dunng those penods when the capacitor (filter) is effectively absent from and the rail voltage is determined by co panng a signal, RailJVolt, indicative of the actual voltage to a ramp generated by applying an incremented count R/2R network 4102
  • interrupt IRQ2 is generated, to cause the measured voltage value VoltJVal m register 4612 to be updated (averaged with the instantaneous A to D count) as will be explained in con j unction with Figure 52
  • each cycle of the inverter output signal is nominally divided into two half cycles, each including a predetermined number of time segments (counts, e g , 32)
  • switched capacitor (filter) 2710 is effectively removed from the operative circuit dunng a predetermined portion of the beginning and end of each half cycle, e g , the first count and last five counts
  • incrementation of the comparison ramp is suspended dunng those penods when the capacitor is out of the operative circuit Accordingly, the CYC_CNTR count is tested against the lower bound (e g , 2) (Step 4914) and upper bound (e g , 1 AH)
  • Step 4916 of the portion of the output half cycle during which filter 2710 is in the operative circuit
  • switched capacitor (filter) 2710 is not part of the operative circuit (e g , 2 ⁇ CYC_CNTR>1 AH)
  • a ump (Step 4918) is effected to label Mam 0 ( Figure 48 A) and the overall process loop repeated If, however, the value of output cycle count CYC_CNTR conesponds to a portion of the output half cycle dunng which switched capacitor 2710 is in the operative circuit (e g , 1 H>CYC_CNTR ⁇ 2), the A to
  • Step 4922 D subroutine is called (Step 4922) to increment the A to D count A TOD JTNT, and the Zero crossing count RMP_CNT, as appropnate
  • Step 4924 Upon return from the A to D subroutine, process loops back to label Main 0 ( Figure 48A) (Step 4924), and the process repeated
  • Interrupt IRQ2 may be generated only once per A to D cycle, and, once processed is disabled for the remainder of the A to D cycle If A to D count in register 4610 has overflowed, I e equals 0, indicative of the beginning of a new A to D cycle, the voltage sense interrupt IRQ2 is re-enabled (Step 4932).
  • the delay timer for welding operations is reset, if appropriate. More specifically, the A to D count is checked to ensure that it is within a predetermined range, e.g., not less than 3FH, and not more than COH (Steps 4934 and 4936). If the A to D count is within the predetermined range, the signal Weld_Sense applied to pin 4 of microprocessor
  • Step 4938 the Weld_Sense signal is active, e.g., equal to 1, the WeldJ lode timer in register 4638 is reset to a value (e.g., FFH) conesponding to the predetermined period, e.g., 4 seconds during which welding mode operation is maintained after the termination of an arc (Step 4940). If the A to D count is outside of the permissible range, or after the weld mode timer has been reset, the A to D count in register 4610 is incremented, and the count applied to R/2R network 4102 (Step 4942). A return from the subroutine is then effected (Step 4944).
  • FFH FFH
  • interrupt IRQ4 (Timer 0 interval) is generated upon timeout of the timer 0 register, e.g., every 130 micro-seconds (conesponding to a predetermined fraction, e.g., l/32 nd , of a half cycle of the desired frequency, e.g.,
  • Step 5004 upon generation of interrupt IRQ4: the other interrupts are disabled (Step 5002) to prevent interference; timer zero is loaded with TMJBASE_60, contained in register 4604, indicative of the desired AC output frequency (e.g., 60 Hz); and the timer 0 down count reinitiated (Step 5004).
  • a watchdog fail-safe function can be employed; a hardware timer in processor 4100 which, if not timely reset, times out, causing processor 4100 to reinitialize operation.
  • the watchdog timer is suitably reset every 130 microseconds, in response to IRQ4 (Step 5006).
  • control signal SCR employed to initiate conduction in the most negatively biased (conesponding to the most negative phase) of SCR's 4008 in the inverter rail generator 4000, is suitably, a pulse, asynchronous (random) relative to the 3-phase signal from stator windings 400A and of relatively short duration, preferably just sufficient to reliably fire the SCR (e.g., in the range of 5-50 ⁇ seconds, and typically 20-50 ⁇ seconds) such, that only a single output pulse is provided at rail 542 per SCR pulse.
  • Control pulse SCR is provided at pin 35 (port 2, pin 0) of microprocessor 4100, and reflects the content of bit 0 of P2 register 4642. Accordingly, bit 0 of P2 register 4642 is set to 0 to turn off control pulse SCR and facilitate commutation off of SCR's 4008 of inverter rail generator 540 (Step
  • bit 0 of P2 register 4642 is set to 1 to start control pulse SCR in response to IRQ5 interrupts, effected upon time out of a previously determined pulse population delay period.
  • the count CYC_CNTR is maintained (register 4624) indicative of the instantaneous phase (e.g., number of 130 microsecond periods elapsed in) of the converter output signal the present half cycle of the converter output signal.
  • the count is pe ⁇ odically incremented, e.g., each 130 microseconds, in response to the IRQ4 interrupt (Step 5010).
  • the incremented count CYC_CNTR is then checked against a predetermined count generally conesponding to Tl ', in Figure 28, the point at which all of the switching circuits are turned off, chosen to ensure that typical cunent lags are accommodated (e.g., 1FH) (Step 5012).
  • control signals to converter 530 are provided at pins 36-39, and 2-3 of microprocessor 4100 (port 2, pins 1 -6), and reflect the contents of P2 register 4642. Accordingly, the contents of P2 register 4642 are modified to turn off all of the switching circuits of converter 530
  • Step 5016 If, however, the output phase count CYC_CNTR is less than the count indicative of the beginning of the dead time (e.g , 1FH), a jump is effected to the program module labeled TICK0 ( Figure SOB) and a sequence of steps effected to determine whether other converter state changes are called for (Step 5016).
  • lagging cunents caused by highly inductive loads are accommodated by rendenng the operative high side power switch (2702 or 2704) non-conductive at the point in time corresponding to the beginning of the dead time in the desired voltage wave form (e g , Count 1CH, conesponding to time Tl in Figure 28)
  • the operative low side power switch (2706 or 2708) (and hence all of the power switch circuits of converter 2700 are thereafter turned off at a subsequent time, e.g , 1FH, conesponding to time Tl' in Figure 28, to permit continued cunent flow of lagging cunents
  • phase count CYC_CNTR is less than the value (e g., 1FH) indicative of the beginning of the cycle dead time, (Step 5012), refening to Figure 50B it is tested against the predetermined value (e.g., 1CH) indicative of the point in the cycle where the voltage goes to zero (conesponding to time Tl in Figure 28) (Step 5018) If phase count CYC_CNTR is not less than, e.g , 1CH, the operative high side bridge is turned off, e.g , the bits of P2 register 4642 conesponding to the
  • TopJLeft and TopJRight control signals are set to zero (Step 5020).
  • a jump is then effected to a program module labeled TICK3 (Step 5022) whereupon interrupts IRQ0-3 are cleared (Step 5024), to avoid enoneous readings due to switching noise, and a return from the interrupt is effected (Step 5026)
  • phase count CYC_CNTR is tested (Step 5028) against a value indicative of the point in the cycle when switched capacitor 2710 is effectively removed from the circuit (e g , 1BH) conesponding to time T4 in Figure 28 If output phase count CYC_CNTR is equal to the predetermined value (e g , 1BH), conesponding to time T4 in Figure 28, switch capacitance 2710 is effectively moved from the operative circuit (Step 5030).
  • phase count CYC_CNTR is tested against another predetermined value (e g., 1 ) conesponding to the point in the output half cycle when switched capacitance 2710 is connected into the operative circuit (Step 5032) Accordingly, if the AC phase count C YC_CNTR is not greater than 1 , the contents of the port 2 register 4642 are changed to cause generation of the Cap_Sw ⁇ tch signal
  • Step 5034 After the capacitor has been inserted in the operative circuit, or if C YC_CNTR is greater than 1 , then IRQ0-3 are cleared (Step 5024), and a return effected (Step 5026)
  • Step 5012 if in Step 5012, if CYC_CNTR is found not to be less than, e.g , 1FH, indicative of the point in the cycle when all of the switching circuits in converter 2700, the contents of P2 register 4642 are varied accordingly (Step 5014), 1 e , the operative low side switching circuit (2706 or 2708) is turned off
  • Output cycle count CYC_CNTR is then checked against a value conesponding to the end of the half cycle, e g , 20H, (Step 5036) If the output cycle count is not equal to, e g , 20H, process jumps to label TICK3 (Step 5038), IRQ0-3 are cleared (Step 5024), and a return effected (Step 5026) If however, output cycle count CYC_CNTR is equal to 20H the system is re-initialized for the next half cycle (Step 5040) More specifically, a reversal is effected between the respective power switch circuits of converter 2700, I e , the contents of the BRDG-MSK register are switched (XORed with 06H) to indicate the new half cycle, and the bits of Port 2 register 4642 are changed to switch between generation of T_L, BJR and T_R, BJL, or vice versa and reflected at pins 36, 37, 38 and 39, output cycle count
  • Vanous other functions are effected at dynamic pe ⁇ odic intervals, l e , upon time-out of timei 1, reflecting a desired delay between successive pulses on the inverter rail
  • Figures 51 A and 51B (collectively refened to as Figure 51 ), in response to generation of interrupt IRQ5, timer
  • Step 5102 is initially reloaded with a predetermined count PP_CNT from register 4626, indicative of the desired delay between successive pulses on the inverter rail 542 (Step 5102)
  • Step 5104 A test is then made to determine if a new rail voltage measurement has been acquired (Step 5104) and thus, whether or not count PP_CNT should be reviewed for adjustment to reflect changed voltage conditions
  • VOLTJVAL in register 4612 is set to zero prior to a return from an IRQ5, and thus has a non-zero value only in the event of an intervening voltage sense interrupt IRQ2 (Step 5208, as will be discussed) Accordingly, VOLTJVAL in register 4612 is tested against zero, if VOLTJVAL is zero, no new value has been acquired, and accordingly, the adjustment process is by-passed
  • a jump (Step 5106) is effected to the program module labeled TOCK1 , as will be described in conjunction with Figure 51B 76
  • Step 5108 If the voltage value VOLTJVAL is greater than the predetermined value, a jump (Step 5110) is effected to module TOCKB to initiate a sequence of steps to increase population delay count PP_CNT, and thus decrease the pulse population, and rail voltage, as will be explained If the voltage VOLTJVAL is not greater than the set point (e g , 9BH), the pulse population delay count is decreased by a predetermined amount, e g , 4 lo increase the pulse population, and hence the voltage (Step 5112) The modified pulse population delay count PP_CNT is then tested (Step 5114) to determine if it exceeds a predetermined value
  • VOLTJVAL is greater than the predetermined set point, 9BH
  • a jump is effected to module TOCKB (Step 5110), to increase population delay count PP_CNT More specifically, the pulse population count is increased by a predetermined increment, e g , 4 (Step 5118)
  • the increased count is then compared against a predetermined upper limit, e g , EOH (Step 5120) So long as the population delay count is still less than the upper limit, a
  • timer 1 is enabled to begin down counting from the pnor pulse population delay count initially loaded into the timer in Step 5102 (Step 5124)
  • the SCR control pulse is turned on, as appropnate More specifically, the average voltage determined dunng the last A to D cycle is compared (on the next system clock pulse) against a predetermined value, e g , BOH conesponding to a predetermined maximum permissible voltage, e g , 165 volts (Step 5126) If the average voltage is less than the maximum value, bit 0 of P2 register 4642 is set to 1 and control pulse SCR is turned on to initiate conduction in the negatively biased SCR 4008 in inverter rail generator 540 (Step 5128).
  • VOLTJVAL is reset to 0 (Step 5130) to indicate that the most recently sensed voltage has been processed.
  • VOLTJVAL remains at zero until a new voltage reading is taken (Step 5208) as will be described in conjunction with Figure 52A.
  • a return is then effected (Step 5132).
  • Step 52A upon generation of interrupt IRQ2, if desired, an initial test is made to ensure that switch capacitance 2710 is present in the circuit, i.e , that the output count is within the range where the switch capacitance is connected in the circuit, e.g., not less than 2 (Step 5202), or more than 1 AH (Step 5204) If the output is within that part of the cycle where the capacitance is effectively out of the operative circuit, the voltage is not sampled and a return from the interrupt is effected (Step 5206) Assuming that switched capacitance 2700 is present in the operative system, the A to D count is tested against a predetermined lower level, e.g., 5 (Step 5207) A to D counts below that level are potentially within the noise floor, and preferably ignored.
  • a predetermined lower level e.g., 5
  • indicia of a running average of the rail voltage is calculated (Step 5208). More specifically, the average of the instantaneous A to D count, m register 4610, and average volt value (AVRGJVOLT) in register 4606 is calculated, and loaded back into register 4606 as a new average voltage count The new average voltage count is then loaded into voltage value VOLTJVAL register 4612 to indicate a new voltage reading has been taken
  • IRQ2 is then disabled to ensure that only one voltage reading is taken per A to D cycle (Step 5210)
  • Step 5212 an over voltage test can be effected (Step 5212); the new rail voltage value VOLTJVAL in register 4612 is tested against a predetermined maximum, e.g , C8H If the value is exceeded, converter 2700 is inhibited (all power switch circuits turned off), and the pulse population delay count PP_CNT in register 4626 set to a predetermined value, e.g., F0H, conesponding to a relatively long delay, and hence low pulse population (Step 5214)
  • a predetermined maximum e.g., C8H
  • Step 5206 If the rail voltage does not exceed the predetermined maximum, or, if so, after the converter 2700 has been turned off, a return from the interrupt is effected (Step 5206).
  • the over cunent signal generated by cunent sensor 3912 ( Figure 44) is applied to pin 25 of microprocessor 4100 (port 3 pin 0), and is generated when the integral of the output cunent exceeds a predetermined level.
  • the OVER_CURRENT signal assumes a low level, effectively disabling gating logic 4104, and thus power converter 2700.
  • the over cunent signal is also applied to pin 25 of microprocessor 4100 (port 3 pin 0). Refening to Figure 52B, upon generation of the interrupt, a recovery mode operation is initiated.
  • pulse population delay count PP_CNT in register 4626 is set to a predetermined value (e.g., FOH, suitably approaching the maximum permitted value, e.g., E0H), conesponding to a relatively long delay, and hence low pulse population and low rail voltage (Step 5216). A return is then effected (Step 5218).
  • pulse population delay count PP_CNT in register 4626, and the throttle setting will be varied in accordance with the process described in conjunction with Figures 48 and 51 to return the system to appropriate voltage and cunent levels for the load conditions.
  • voltage and cunent levels are gradually increased from the relatively low starting value to desired operational levels, ramping up as the pulse population delay count PP_CNT in register 4626 is decreased, and/or throttle setting increased in response to below desired value measurements.
  • Step 4908 since the pulse population count is set to a value (e.g., FOH) greater than the maximum value (2FH), (Step 4908), as previously described in conjunction with Figure 49, the NEGDIR subroutine is called (Step 4910) to incrementally close the throttle.
  • the engine speed will thus decrease, causing the rail voltage, and thus output cunent, to decrease.
  • pulse population delay count PP_CNT in register 4626 will be adjusted to reflect the variation of the rail voltage from its predetermined set point value (e.g., 9BH) ( Figure 51).
  • the POSDIR subroutine is called to incrementally open the throttle.
  • a predetermined time period between successive adjustments to the throttle is employed to ensure that the system has sufficient time to respond to the throttle change.
  • a dithering switching frequency that minimally exceeds the time constant of the system linkage such that the throttle assumes a statiac position in response to the dithering, is preferably employed.
  • the time elapsed since the last adjustment to the throttle setting is maintained in TJDLY JTMR in register 4602. Delay counter
  • Step 4602 is loaded with a count (e.g., 30H) indicative of the required delay each time a positive adjustment is made to throttle position (Figure 53; Step 5308), then decremented on a periodic basis (in response to each timer 0 interrupt, e.g., every 130 microseconds (Step 5040). More specifically, referring to Figure 53, when POSDIR is called, delay count TDLYJTMR is initially tested against 0 to determine if the required time has elapsed (Step 5302). If the required time has not yet elapsed, no throttle adjustment is made; a return from the subroutine is effected (Step 5304).
  • a count e.g., 30H
  • Step 5306 the lower half of the address of the step motor output, SW_LOW, in register 4632 is tested against a predetermined constant (Fopen) representative of the full open position of the throttle. If the throttle is full open, a return is effected (Step 5304).
  • Step 5408 It has been determined that negative going throttle adjustments require less response time than do positive going throttle adjustments, too many positive going adjustments of the throttle within a given penod tends to cause the engine to flood out
  • step motor 3300 is, in effect, sequenced through a succession of activation states (e g , successive full pole steps, omitting fractional steps and dithe ⁇ ng) designed to ensure that, by the end of the sequence the throttle is lodged against one of stops 3610 or 3612 ( Figure 36) More specifically, refernng now to Figure 55, a count indicative of a predetermined number of cycles, e.g , 4, is established in one of the registers, e g , A to D count register 4610 (Step 5502) A predetermined number, e g , 80H, conesponding to a predetermined actuation state of step motor 3300 (preferably conesponding to a predetermined pole) is loaded into and output from port 3 register 4644 (Step 5504) A delay is then effected to ensure that stepper motor 3300 has fully responded to the control signals (Step 5504)
  • a count indicative of a predetermined number of cycles, e.g , 4 is established in one of the registers, e
  • the cycle is repeated a predetermined number of times, e g 4, to ensure that, by the end of the routine, the throttle is lodged against one of stops 3610 or 3612 ( Figure 36)
  • the repetition count in A to D register 4610 is decremented (Step 5520), then tested to determine if the predetermined number of repetitions have been performed (Step 5512) If the predetermined number, e g , 4 of repetitions has not been completed, the process cycles back, and Steps 5504-5522 are repeated Once all of the repetitions have been performed, a return from the subroutine is effected (Step 5524)
  • control winding 504 is wound concunently on stator core 302 with a predetermined one of the phases (e g., Phase A), one of the winding groups 400
  • control winding 504 and inverter rail winding 400A with which it is wound creates relationship between the output voltage (CJRAIL) of rectifier 506
  • CJRAIL output voltage
  • the output, C_RAIL_OF rectifier 506, can be employed as the basis for the rail voltage feedback signal to the controller 3910.
  • IR compensation is preferably effected Refernng now to Figure 58, a suitable IR compensation system 5800 for introducing an appropnate scaling factor is shown.
  • the signal indicative of the rail voltage, CJRAIL from rectifier 506, is applied to the positive input (pin 12) of a conventional summing amplifier 5802
  • the negative input (pin 13) is receptive of a signal indicative of the AC cunent, lac (see Figure 44A)
  • a RAILJVOLTAGE feedback signal is determined pnmarily by CJRAIL.
  • a larger signal is subtracted from the C_RATL signal to compensate for increased affects of load
  • vanous of the conductors and connections are shown in the drawing as single lines, they are not so shown in a limiting sense, and may compnse plural connections or connectors as understood in the art.
  • vanous power connections and vanous control lines and the like vanous elements had been omitted from the drawing for the sake of clanty
  • the present invention has been descnbed in conjunction with vanous exemplary embodiments, the invention is not limited to the specific forms shown, and it is contemplated that other embodiments of the present invention may be created without departing from the spi ⁇ t of the invention Vanations in components, matenals, values, structure and other aspects of the design and anangement may be made in accordance with the present invention as expressed in the following claims
  • a relatively economical, but relatively high power and lightweight, portable generator which automatically reduces engine RPM when the system is in light or no-load condition to reduce fuel consumption and environmental noise is particularly desirable
  • a particularly economical, lightweight portable generator system 6100 compnses an engine 14, including a throttle 34, an electromechanical throttle actuator 36, a permanent magnet alternator 17, a suitable controlled multi phase (e g , 3) rectifier 4000, a DC rail 542, a suitable multi phase (e g , 3) rectifier 3920, for generating a relatively low voltage (e g , +12 V), high cunent signal Battery Boost a suitable inverter, a suitable single phase rectifier 506, for generating a relatively stable low voltage CJRail signal indicative of the level of the DC rail signal (less the losses due to internal resistance) (IR drop), a suitable stable regulated power supply, a suitable negative 5 volt supply 4600, a suitable cunent sensor 538 for generating a relatively low voltage signal indicative
  • Contiol system 6200 is suitably receptive of the DC rail signal V_Ra ⁇ l (or a signal indicative thereof), signal I_AC indicative of the AC output cunent, the C_Ra ⁇ l signal, and the Battery Boost signal and generates respective control signals Cap_S, T_R, T_L, B_R, B_L to inverter 2700, SCR to control rectifier 4000, and STPl , STP2, STP3 and STP4 to actuator 36 to control the setting of throttle 34
  • Electromechanical throttle actuator 36 suitably comprises a stepper motor 3300 and coupling
  • Stepper motor 3300 is responsive to respective control signals STPl , STP2, STP3 and STP4 from control system 6400
  • Alternator 17 suitably compnses a permanent magnet alternator 17, generally analogous to that descnbed in conjunction with Figures 1 -3, including a rotor 20 employing high energy product magnets and consequence poles, and a concunently wound multi-winding stator with first and second 3-phase groups of coils 400A, and 400, and a control winding 504 cooperating to provide particularly advantageous heat dissipation charactenstics, such as described in detail in parent ln-part application Se ⁇ al No 08/306/120, filed September 14, 1994 by Scott et al , and commonly owned herewith
  • Engine 14 drives rotor 20 at a rotational speed in accordance with the setting of throttle 34 established b ⁇ control signals Rotation of rotor 20 induces cunents in coils 400A, 400 and 504 Engine 14 and alternator 17 coopeiate to produce output voltages of relatively high frequency, the frequency of the alternator output can be on the order of 400 Hz, depending upon the engine RPM Generation of such a relatively high frequency AC voltage facilitates the use of a lightweight alternator 17
  • Controlled rectifier 4000 responsive to a control signal SCR from control system 6200, converts the high frequency three-phase AC signal of 3-phase windings 400A into a DC signal, VJRail, provided on DC rail 542
  • Controlled rectifier 4000 is analogous to rectifier 4000, previously described in conjunction with Figure 40
  • the level of the DC rail voltage, VJRail is a function of the rotational speed of rotor 20, and modulation (if any) of the SCR control signal
  • the SCR signal is held in an activated state
  • inverter 2700 selectively connects the DC rail signal to terminals LI and L2 in response to control signals (TJR, T_L, BJR, BJL) from control system 6200 and, in response to control signals (CAP_S) selectively switches a capacitor into the operative system to generate a simulated sine wave
  • Inverter 2700 is analogous to switched capacitor inverter 2710 previously descnbed in conjunction with Figure 29
  • a relatively low voltage signal, I_AC, indicative of the average AC output cunent of inverter 2710, is provided by current sensor 538
  • Cunent sensor 538 is analogous to cunent sensor 538 described in conjunction with Figure 21
  • Rectifier 3920 responsive to the high frequency three phase AC signal of 3-phase windings 400, generates a relatively low (e g , +12 V), high cunent, Batteiy Boost, voltage suitable for charging automobile battenes, at output terminals DC OUT Re ⁇ ifiei 3920 is analogous to circuit 3920 of system 3900
  • the throttle control system senses load demands on the DC OUT output, and increases engine speed to maintain the Battery Boost signal at least a predetermined minimum level Vanous signals are denved from the relatively high frequency, single phase, output of winding
  • Rectifier 506 denves, from the output of control winding 504, a relatively stable, low voltage signal, CJRail, indicative of the level of the DC rail signal, less the losses (IR drop) in windings 400A due to internal resistance
  • Control winding 504 is generally analogous to control windings 504 descnbed in conjunction with Figures 5 and 39, and rectifier 506 is analogous to rectifier 506 of system 3900
  • Regulated power supply 6102 denves respective stable, regulated, supply voltages at predetermined levels, e.g., +15, +6.9, and +.5 volts from the CJRail signal
  • Negative 5 volt supply 4600 is responsive to signals from control winding 504, and is generally analogous to the negative 5 volt supply descnbed in conjunction with Figures 39 and 44A.
  • Throttle control is employed to adjust engine speed to satisfy load requirements.
  • Engine speed is automatically reduced in light or no-load conditions to reduce fuel consumption and environmental noise, as well as mechanical wear on engine parts.
  • feedback control of engine speed is employed to maintain the DC rail voltage (and hence, average voltage of AC output) within a predetermined range of a designated nominal value, e.g., within plus or minus 10% of 120 volts
  • the DC rail voltage exceeds the upper limit of the acceptable band, e.g., 132 volts
  • control system 6200 generates appropnate control signals to actuator 36 to close the throttle, concomitantly decreasing engine RPM, and, in turn, the output voltage
  • the rail voltage drops below the lower limit of the acceptable band, e.g., 108 volts
  • the throttle is incrementally opened to increase engine speed, and thereby increase the rail voltage.
  • incandescent lamps One of the most common loads for small generators, incandescent lamps, presents one of the most severe load conditions. As previously noted, incandescent lamps manifest a resistance that is widely vanable with temperature; a cold filament presents an extremely low resistance, that increases dramatically as the filament warms.
  • Use of switched capacitor inverter 2700 to generate a quasisquare wave, simulated sine wave, and use of over cunent detection and recovery processes permit system 6100 to employ power devices rated for average cunents, as opposed to more expensive, higher rated, devices. More specifically, in system 6100, control system 6200 monitors the DC Rail voltage
  • control system 6200 Upon detection of "cunent out of limits" condition, control system 6200 generates control signals to quickly reduce engine speed to a predetermined level, e.g., to a value just slightly higher than the normal no-load idle. The RPM is then maintained at that value for a predetermined penod of time, chosen to be just long enough to permit the filament to warm up under normal operation conditions. Dunng that period, the rail voltage is modulated to vary in accordance with a predetermined algonthm, e.g., linearly from a minimum value to "full on” condition. At the end of the predetermined penod, throttle feedback control is resumed.
  • a predetermined algonthm e.g., linearly from a minimum value to "full on” condition.
  • actuator 36 and throttle 34 are conelated by appropnately initializing actuator 36, then effecting periodic self-tuning
  • step motor systems when the stepper, or coupling system is lodged against a mechanical stop, subsequent pulses cause a "bounce", resulting in a reversal of position by one or more steps Pulses applied after the reversal, will cause the stepper to advance until the stop is again encountered, whereupon the "bounce” will recur, the stepper, in effect, bumps back and forth at the mechanical stop Where a stepper motor is employed as the throttle actuator, such bumping back
  • control system 6200 suitably comprises a conventional microcontroller 6202, a suitable reference voltage generator 6300, a suitable feedback sealer circuit 6400, for generating a signal V JFB suitable "cunent out of limits” detection circuitry 6500 for detecting short circuit and over-cunent conditions, suitable "voltage out ol limits” detection circuitry 6600, for detecting over- voltage, and under-voltage conditions, a suitable throttle driver 3 14A, for generating approp ⁇ ate dnve signals to actuator 36, and suitable gating logic 4104. analogous to that descnbed in conjunction with Figures 41 and 42
  • Microcomputer 6202 suitably comprises an 1 p Zialog 86E04 microcomputer, including internal read only memory, random access memory, and two internal comparators More specifically, microprocessor 6202 is suitably configured such that pins 8, 9 and 10 are analog inputs (ports 3, bits
  • pins 8 and 9 are inputs to the respective internal comparators, with reference signal to each of the comparators being provided at pin 10
  • Pins 11 , 12 and 1 are configured as part of a positive logic output port (Port 0, bits 0, 1, 2) for providing respective control signals, (top, right and bottom) indicative of the desired switching state of inverter 2700 to gating logic 4104
  • pins 15, 16 and 17 are configured as part of a positive logic output port (port 2, bits 0, 1 , 2), and provide control signals to throttle dnver 3314A
  • Pins 1 , 2 and 3 arc similarly configured as positive logic outputs (Port 2, bits 4, 5, 6), and provide the Cap_S signal to inverter 2700, the SCR control signal to rectifier 4000, and a reset signal to cunent out of limits detection circuit 6500, respectively
  • Gates 4 and 18, are configured as negative logic input ports (port 2, bits 3 and 7), receptive of an IJLMT signal indicative of a cunent out of limits condition, and a V_LMT signal indicative of a voltage out of limits condition, respectively
  • Reference generator 6300 generates reference voltages, hi (e g , 2 8 volts) and low (e g , 2 1 volts) indicative of the upper (e g , 132 volts) and lower (e g , 108 volts) limits of the acceptable band of N_Ra ⁇ l values, but suitable for application as input signals to microprocessor 6202
  • Reference voltage generator 6300 may be any circuit capable of providing respective signals indicative of the upper and lower limits of the acceptable band of rail voltage
  • reference generator 6300 compnses first and second voltage dividers 6302 and 6304 employed to generate the respective upper and lower limit reference signals If desired, diodes (D3, D4) can be provided to ensure that the voltage applied to the microprocessor 6100 does not exceed the five volts
  • Feedback sealer circuit 6400 may be any circuit capable of adjusting signal feedback V JFB to reflect losses due to internal resistance of coils 400, and load demand dunng battery charging operations More specifically refernng to Figure 64, feedback sealer 6400 compnses an IR compensation circuit 5800A, and a battery charging load compensation circuit 6402
  • Batten charging compensation circuit 6402 causes a feedback signal V_FB to be reduced when loading causes the Battery Boost output signal to drop below a predetermined value, e g ,
  • battery charging compensation circuit comprises a Zener diode Zl , a transistor Ql , and an opto-isolator Ul Dunng normal operation
  • the Battery Boost voltage is above the predetermined level, e g , 12 5 volts So long as the Battery Boost voltage is above that level
  • Zener diode Zl is conductive, actuating transistor Ql, and inhibiting the LED of opto-isolator Ul
  • the signal indicative of the CJRail signal is determined in significant part by the ratio of the value of resistor Rl 1 to the sum of the values of resistors R12 and R4
  • Zener Zl ceases to conduct, turning off transistor Ql , and effecting actuation of the optoisolator LED
  • resistor R4 is effectively shunted from the operative circuit, so that
  • IJLMT signal applied to pin 4 of microprocessor 6502 is detected, and initiate an appropnate over cunent recovery process Likewise, if the output cunent of invertei 2700 exceeds a predetermined value, over cunent detector 4400 generates a high going signal to the clock input of latch 6504 (e g , D-type flip flop) Since the data input is tied high, the positive going transition at the clock input causes a high Q output and low Q bar The low going over cunent bar signal (Q bar) is applied to one input of AND gate 5506, driving the output IJLMT of AND gate 5506 low, and likewise initiating over cunent recovery process The Q output (over cunent) is applied to gating logic 4104, as previously descnbed
  • the engine RPM (throttle setting) is initially reduced to a predetermined value (Idle_OC), suitably a value slightly higher than the normal no-load idle
  • Idle_OC a predetermined value slightly higher than the normal no-load idle
  • modulation control preferably pulse population control, of the inverter SCRs is effected, to reduce the average DC output voltage
  • a minimum pulse population (minimum pulse duration, if pulse width modulation is employed) is adopted to minimize the voltage
  • the pulse population is increased in accordance with a predetermined algorithm (suitably linearly from minimum to maximum population) over the course of the predetermined time period
  • the predetermined time penod is suitably chosen to be the shortest penod sufficiently long to permit a cold filament to warm to a point where repeated over cun
  • Voltage out of limits detection circuitry 6600 monitors the DC rail signal V_Ra ⁇ l, and CJRail signal to detect over voltage conditions, and supply voltage insufficiencies, and responsively generates an active VJLMT signal to p 18 of microprocessor 6202
  • a stepwise closure process would take a significant time penod to traverse all of the individual steps
  • significant damage could occur to the vanous components of the circuits, e g., the inverter MOSFET's, or the load, dunng the relatively long penod
  • an actuation signal is provided to negative logic pin 18 of the microprocessoi, causing initiation of a fast close down routine
  • voltage out of limit circuit 6600 suitably compnses a first circuit
  • an active (e g , low going) signal is provided to pin 18 of microprocessor 6202, to initiate a dynamic control sequence to effect a relatively rapid decrease of the throttle setting
  • Circuit 6602 suitably comprises a reference signal generator 6606 (e g , voltage divider), a voltage divider 6608, a conventional comparator 6610, and a transistor switch Q7 6612
  • Reference voltage generator 6606 generates a reference signal indicative of the designated lower supply voltage limit Voltage divider 6608, receptive of the C_Ra ⁇ l signal, generates an analogous signal indicative of the level of the CJRail voltage
  • the signals from voltage dividers 6606 and 6608 are applied to the non-m verting and inverting inputs of comparator 661 , respectively Under normal operating conditions, the value of C_Ra ⁇ l is greater than the predetermined value Accordingly, comparator 6610 generates a logic 0 output, and transistor 6612 is non-conductive A logic high signal is therefore provided at microprocessor pin 18 Microprocessor pin 18, however, responds to negative logic, and no action is initiated When the value of CJRail drops below the predetermined limit, comparator 6610 generates a positive output
  • Voltage over limit circuit 6604 similarly compnses a reference signal generator 6614 for generating a signal indicative of the designated limiting value, a voltage divider 661 , responsive to the
  • VJRail signal for generating an analogous signal indicative of the value ol the V_Ra ⁇ l signal, a comparator 6618, and a transistor switch 6620
  • a filter capacitoi C21 , and clamping Zener diode Z8 can be provided to limit the level of voltages applied to comparator 6618, and avoid potential damage due to excessive signal levels
  • the reference signal and the signal indicative of the rail are applied to the inverting input, and non-inverting of comparator 6618 respectively
  • V_Ra ⁇ l the value of V_Ra ⁇ l is less than the designated limiting value, and comparator 6618, therefore generates a logic 0 output rendering transistor 6620 non-conductive Accordingly, a positive signal is provided at negative logic microprocessor pin 18 However, if V rail exceeds the predetermined level, comparator 6618 will generate a positive output, rendenng transistor 6620 conductive, and pulling negative logic microprocessor pin 18 low, thus initiating the dynamic control process
  • Throttle dnver 3314A may be any circuit capable of generating appropnate dnve signals (e g , STPl, STP2, STP3, STP4) to actuator 36 from control signals from pins 15-17 of microcontroller 6202
  • throttle dnver 3314A may compnse a unidirectional or bidirectional driver such as descnbed in con j unction with Figures 33A, 33B, and 34 In system 6100, however, throttle driver
  • stepper motor 3314A preferably compnses a commercially available stepper motor driver chip such as, for example, a Motorola MC3479
  • the MC3479 is designed to d ⁇ ve a two phase stepper motor in the bi-polar mode and includes four input sections, a logic decoding/sequencing section, and two driver stages for the motor coils
  • Throttle dnver 3314A is responsive to a clock control signal (CLK), a direction control signal (CW/CCW) and a resolution control signal (F/H), provided at pins 15, 16 and 17 of microprocessor 6602, respectively.
  • CLK clock control signal
  • CW/CCW direction control signal
  • F/H resolution control signal
  • the driver chip In response to each positive going transition in clock signal CLK, the driver chip incrementally steps through the actuation state sequence of the stepper motor, in the direction indicated by indication control signal CW/CCW, and provides full step or half step resolution in accordance with the value of resolution control signal F/H.
  • microcontroller 6202. In general, the operation of the system is controlled by microcontroller 6202. As previously described, microcomputer 6202 typically maintains a number variables in memory, and depending upon the particular microprocessor chip employed, separate hardware registers, fixed and/or variable functions, can be utilized in connection with the variables. Further, where the registers are organized in separate pages, conventional universal variables and page changing techniques would be employed. In other microprocessor chips, the variables would be maintained in respective locations of random access memory. In system 6100, microprocessor 6202 maintains, among others, the following variables in memory:
  • T_open_del constant indicative of the time period required by the 6218 mechanical system to respond to an incremental opening of the throttle (e.g. 30H)
  • T_close_del constant indicative of the time period required by the 6220 mechanical system to respond to an incremental closing of the throttle (e.g. 18H)
  • T_delay_tmr count indicative of the time elapsed since the last the throttle 6222 adjustment
  • Idle_OC count indicative of throttle setting for predetermined engine 6226 speed
  • Cap_en_flg an enable/disable flag for operation of the switching 6228 capacitor
  • PS* SCR Regulator Clock (count indicative of the desired delay 6230 period between SCR pulses to inverter 2700 for pulse population modulation of the rail voltage; conesponds to PP CNT of system 3900) 90
  • Psmax count indicative of the maximum delay interval between 6232 SCR pulses (Minimum Pulse Population)
  • LS_END_CNT count indicative of the designated Constant low-speed 6236 operation dunng a recovery operation scr_cntr count indicative of time elapsed since last SCR pulse dunng 6238 a voltage regulation operation step_cnt count indicative of time elapsed since last throttle change 6240 dunng accelerated (dynamic) close down
  • Microprocessor 6202 is suitably interrupt dnven, various interrupt signals are generated in response to predetermined conditions to effect predetermined processes
  • system 6100 suitably employs the following interrupts
  • POSDIR effects movement of the throttle one step in the positive direction (opens the throttle one increment)
  • THROTTLE initializes the position of the throttle to a predetermined position (e g , INITIALIZATION full open)
  • H-BRIDGE selectively generates control signals (CAP_S, T_R, T_L, BJR, BJL) to effect control of inverter 2700 (analogous to the process effected in response to IRQ4 of system 3900, previously descnbed in conjunction with Figure 50), to generate a simulated sine wave output
  • an initialization process 6700 is effected Dunng the initialization process, the vanous register pointers are set (Step 6702), internal stacks are set (Step 6704), the various counters employed are initialized (Step 6706), the vanous input/output ports, e g , conesponding to pins 1, 2, 3, 15-17 and 1 1 -13 of microprocessor 6202, are initialized (Step 6708), and the respective vanables initialized (Step 6710).
  • the initialization process is generally analogous to process 4700 of system 3900, previously descnbed in conjunction with Figure 47
  • a throttle initialization subroutine 6800 is then called to initialize the position of the throttle to a predetermined position, e.g., full open. Thereafter, the system essentially operates in a loop 6712, waiting for interrupts
  • throttle initialization routine 6800 is employed to initialize the position of the throttle to a predetermined position, e g , full open
  • the watch dog timer WDT employed in microprocessor 6202 is first refreshed, to prevent control system 6200 from being reset, due to microprocessor inactivity while the throttle initialization process is executed
  • the throttle is then opened by one increment (Step 6804) More particularly, the POSDIR subroutine is called to generate approp ⁇ ate signals at pms 15-17 of micro controller 6202 to cause the throttle to advance in the open direction (e g , counterclockwise)
  • the POSDIR routine is functionally the same as that descnbed in conjunction with Figure 53
  • a commercial stepping motor driver chip advances the stepping motor in the designated direction in response to a positive going edge of the clock signal
  • the POSDIR and NEGDIR routines would be modified accordingly
  • the POSDIR and NEGDIR routines suitable for use with such a commercial stepper motor driver are illustrated in Figures 69 and 70
  • a count is maintained in register 6210, indicative of the nominal position of the stepper motor
  • count SW is incremented in connection with execution of the POSDIR subroutines after the stepper has been incremented, count SW is checked against a value FOPEN and indicative of the full open throttle position (Step 6806) If SW is less than FOPEN, the process loops back and steps 6802, 6804 and 6806 are repeated If SW is not less than FOPEN, SW is set to FOPEN (establishing FOPEN as the maximum value) (Step 6808) and a return effected (Step 6810)
  • Step 6902 the TJDelayJTimer program count (indicative of the time elapsed since the last throttle adjustment) is checked against 0 (Step 6902) to ensure that sufficient time has elapsed since the last throttle adjustment for the mechanical system to respond If sufficient time has not elapsed, a return from the subroutine is effected (Step 6904) Assuming, however, that sufficient time has elapsed, count SW, indicative of the position of the throttle, is checked against value, FOPEN, indicative of the full open throttle position (Step 6904)
  • FOPEN may be a constant, hard programmed into the system, or may be a vanable stored, e g., in register 6216 If the throttle position count SW is not less than full open count FOPEN, SW is set equal to FOPEN (establishing FOPEN as the maximum value) (Step 6906) and a return is then effected (Step 6904) Assuming that the throttle is not
  • Throttle position count SW is then incremented (Step 6914), and a count TJDpen J) indicative of the time required for the mechanical system to respond to an incremental open command is loaded into the T J)elay J)MR (Step 6916) A return is then effected (Step 6904)
  • Vanous functions are performed on a penodic basis, in response to interrupt IRQ4 (e g , upon timer 0 timeout every 260 microseconds)
  • interrupt IRQ4 e g , upon timer 0 timeout every 260 microseconds
  • the micro controller watchdog timer is first refreshed (Step 7202)
  • An inverter and over-cunent module 7300 is then executed Over-cunent conditions, e g , status of micro controller pin 4, is then checked, and, if a current out of limits condition is indicated (e.g , by a 0 at micro controller p 4), an over cunent recovery process is executed
  • the inverter and over-cunent process module will be more fully descnbed in conjunction with Figure 73
  • a voltage regulation process module (7400) is then executed to generate the SCR control signal at pin 2 of micro controller 6202.
  • the VR module will be more fully descnbed in conjunction with Figure 74
  • the SCR signal is maintained full on during normal operation such that control rectifier 4000 provides the highest DC rail output for a given engine speed During recovery mode operation, however, after the throttle has been set to establish a relatively predetermined low speed, pulse population modulation is effected, to vary the voltage in accordance with a predetermined algonthm, e.g., increase linearly from a predetermined minimum value
  • a self idle tuning process module 7600 is then effected to compensate for any "bounce" that may have caused a deviation in conelation between the electrical 0 and mechanical 0
  • system 6100 is initialized to reflect the throttle in, e g , a full open position, and stepper motor 3300 is advanced sufficiently to b ⁇ ng the throttle into full open position
  • stepper motor 3300 is advanced sufficiently to b ⁇ ng the throttle into full open position
  • the actual position of the throttle may be offset by one or more steps from the actual full open position
  • the count, indicative of the relative position of step motor 3300 is maintained by system 6100, a zero count conesponds to a fully closed throttle Any time the position count equals 0, but the rail voltage is still in excess ol the upper acceptable limit, a misalignment is indicated, and control signals generated to close the throttle by successive steps until the voltage is reduced to within the acceptable range
  • a dynamic control module is then executed; micro controller pin 18 is tested for voltage out of limits conditions, and if so, a rapid closure of the throttle is effected
  • the dynamic control module will be described more fully in conjunction with Figure 76
  • the idle self tuning module will be more fully described in conjunction with Figure 75.
  • a throttle control process module 7700 is then executed. Briefly, the feedback signal V JFB is sampled. If the voltage is below the lower limit, the throttle is incrementally opened. If the feedback voltage V _FB is greater than the upper permissible limit, the throttle setting is closed by one increment. (Throttle control module 7700 will be more fully explained in cooperation with Figure 77.). The unused interrupts are then cleared to avoid enoneous readings due to switching noise (Step 7204) and a return from interrupt effected (Step 7206).
  • over-cunent detection and recovery is effected as part of the normal periodic operation process rather than in response to an occunence initiated interrupt.
  • the over-cunent recovery process is generally executed over the course of a number of Timer
  • the predetermined time period (TJowspeed) is suitably chosen to be relatively short but still sufficiently long to permit the application of a relatively low voltage to warm the cold filament to a point where repeated overcunent conditions will not occur. It has been determined that a time period in the range of .2 to .8 seconds, and most preferably about .5 seconds is prefened.
  • modulation control preferably pulse population control
  • modulation control of the inverter SCR's is effected, to reduce the average DC output voltage beyond the reduction caused by the reduced engine speed.
  • a minimum pulse population (minimum pulse duration, if pulse width modulation is employed) is adopted to minimize the voltage.
  • the pulse population is increased in accordance with a predetermined algorithm (suitably linearly from minimum to maximum population) over the course of the predetermined time period.
  • the SCR control signal is once again placed in full on condition and throttle feedback control resumed, and the system will be adjusted in accordance with the load.
  • a flag, OC_flag is maintained to facilitate tracking the state of the recovery process
  • the OC Jlag is initially checked against 0 to determine the state of the process (Step 7302)
  • the OC Jlag is set to 0 dunng the initialization process, and at the end of the constant low speed operation penod (l e , at T2) Accordingly, if OC Jlag is 0, either no over-cunent recovery process is on-going, or the constant low speed penod (TJowspeed) has been completed
  • Step 7304 a determination is then made as to whether an over cunent condition exists (Step 7304) More specifically, the state of micro controller pin 4 (I e , I_LMT) is tested If IJLMT is not active, indicating that no cunent out of limits condition exists, the module is exited (Step 7306) assuming, however, the an over cunent condition exists, a H-b ⁇ dge subroutine is called (Step 7305) to generate control signals (TJR, TJ-, B_R, BJ_.) to inverter 2700
  • the H-b ⁇ dge subroutine is analogous to the process effected in response to IRQ4 in system 3900 previously descnbed in conjunction with Figure 50
  • the module is then exited (Step 7306)
  • inverter 2700 is shut down, micro controller pins 1 1-13 are set to inactive Since detection of over-cunent conditions is done on a penodic, as opposed to an event initiated basis, the precise point of time within the 260 microsecond interrupt cycle when the over-cunent condition occuned is unknown It is therelore possible that by the time the over-cunent condition is detected (Step 7304) the condition could already have existed, and the components subject to the cumulative effect of the condition, for substantially an entire cycle, e g , 260 microseconds Accordingly, inverter 2700 is temporarily shut down, suitably until the next successive interrupt cycle (e g , 260 microseconds)
  • the switched capacitor of inverter 2700 be effectively removed from the circuit dunng the recovery process
  • the switched capacitor is charged to a level substantially equal to the DC line voltage, e g , in excess of 120 volts
  • the cap switch signal is rendered inactive, and an enable flag, CAPJ ⁇ LFLG is cleared to 0 (Step 7310)
  • the pulse population is minimized (Step 7312), l e , the pulse delay interval count PS* (register 6230, responding to PPJZNT of system 3900) is set to a predetermined maximum value (PS MAX)
  • PS MAX a predetermined maximum value
  • the value of PS MAX may be hard programmed as a constant, or may be maintained as a vanable in, e g , register 6232
  • the OC flag is then set to 1 (Step 7314) to indicate that the first interrupt cycle in the over cunent recovery process has been completed
  • Step 7302 When Inverter and Over-cunent module 7300 is initiated in the next interrupt cycle, the test of the OC flag (Step 7302) indicates that the flag is not equal to 0 Accordingly a determination is made as to whether the process has entered the constant speed period, TJowspeed. To this end, a low speed flag (LSJFLG) is maintained, and set to 1 only after the position count SW has reached the predetermined Idle 3C value. Accordingly, the LSJFLG is tested (Step 7318). In the second interrupt cycle, the low speed flag has not yet been set; the recovery period is still in the RPM reduction mode (occurring between TO and Tl ).
  • LSJFLG low speed flag
  • Step 7308 While inverter 2700 was inhibited during the first pass of the recovery process (Step 7308), it is desirable that an AC signal be provided during a substantial portion of the recovery process to warm up cold filament loads. Accordingly, the H bridge subroutine is called (Step 7320) to reinitiate inverter operation.
  • actuator 36 e.g., stepping motor 3300
  • a delay is effected (Step 6804) to ensure that stepper motor 3300 has fully responded to any previous control signals.
  • the delay is suitably effected by calling a conventional no-operation loop, such as, that described in conjunction with Figure 56.
  • Throttle position count SW in register 6210 is then incremented (Step 6806), and tested against a count (FOPEN) in register 6216 representative of a full open position (Step 6808).
  • the count (FOPEN) conesponding to a full open throttle position may be hard programmed as a constant, or may be maintained as a variable, e.g., in register 6214. Assuming that the throttle has not yet reached a full open position, the throttle is advanced in the open direction by one step. Throttle position count SW is set, during initialization, to a count FCLOSED indicative of a full closed position. The FCLOSED count is typically equal to 0, and may be hard programmed as a constant. However, FCLOSED can be maintained as a variable in, e.g., register 6214. More specifically, the throttle control word (TC) is set appropriately, and output at pins 15, 16 and 17 to throttle driver 3 14A. For example, the clock bit of the throttle control word is set to 0, and output at pin 15, and thereafter is set to 1 and output at pin 15, to generate a positive edge.
  • TC throttle control word
  • throttle position count SW is tested to determine whether it is greater than or equal to the predetermined value (Step 7322). If the throttle position count is not greater than or equal to (i.e., is less than) predetermined value Idle_OC, the POSDIR routine is called to open the throttle (Step 7324). If at Step 7322 it is determined that throttle position count is greater or equal to Idle_OC, SW is again tested against Idle_OC for equality (Step 7326). If SW is not equal to Idle_OC (i.e., is greater than) the NEGDIR routine is called to incrementally close the throttle
  • Step 7328 the NEGDIR subroutine minors the POSDIR routine, with throttle position count SW tested against FCLOSED, the direction bit CW/CCW loaded with indicia of the closing direction (e.g., 0), throttle position count SW decremented, and the response delay period associated with closure of the throttle (TJLXOSEJD) loaded into the delay timer.
  • the POSDIR routine minors the POSDIR routine, with throttle position count SW tested against FCLOSED, the direction bit CW/CCW loaded with indicia of the closing direction (e.g., 0), throttle position count SW decremented, and the response delay period associated with closure of the throttle (TJLXOSEJD) loaded into the delay timer.
  • Step 7316 If SW is not equal to predetermined count Idle_OC, the module is exited (Step 7316) If, however, it is determined as a result of either of Steps 7326 or 7330 that SW is equal to Idle_OC, the process has entered into the constant engine speed penod (TJowspeed) and, accordingly, flag, LSJ F LG, indicative of operation in the constant speed penod, is set to 1 (Step 7332) prior to exiting the module (Step 7316)
  • Step 7302 When Inverter and Over-cunent module 7300 is initiated dunng the next successive interrupt cycle, the OC J ⁇ lag is unchanged from Us value 1 , and accordingly, when tested (Step 7302) the process proceeds to test the constant low speed operation flag LSJ F LG (Step 7318) However, flag LSJ F LG was set to 1 in the just preceding cycle conesponding to the constant speed operation
  • the SCR control is pulse population modulated in accordance with a predetermined algonthm, e g , linearly from a predetermined minimum to a predetermined maximum attained near the end of the constant speed operation penod Accordingly, the H bridge routine is called to service inverter 2700
  • Step 7334 Pulse population modulation is affected by VR module 7400 as will be descnbed
  • a count OC JL.NT is maintained indicative of the number of cycles elapsed since the constant speed operation was initiated Count OC _CNT, is cleared dunng the initialization process, and, at the end of each constant speed operation Count OC_CNT is incremented in response to each interrupt cycle (e g , every 260 microseconds) once the constant speed operation is initiated (Step 7336) until a count LS_END_CNT indicative of the desired low speed operation duration is reached, after OC_CNT is incremented, it is tested against count LS_END_CNT (Step 7338) If OC_CNT is not equal to LS_END_CNT, l e , the constant low speed operation period has not yet ended, the module is exited (Step 7316) voltage regulation module 7400 effects pulse population modulation of the signal, and the sequence is repeated dunng the next interrupt cycle
  • OC_CNT LS END_CNT
  • the vanous flags are set or cleared to manifest completion of the cycle and ready the system for the next operation More particularly, the OC count is cleared, the OC flag is cleared, the LS_FLG is cleared, and the CAP enable flag CAP J ⁇ N J ⁇ LG is set to 1 to enable the switched capacitor of inverter 2700 (Step 7340)
  • Step 7402 An initial check is made to determined whether or not modulation is called for, the pulse population interval count PS* is tested against the minimum value PSmin (indicative of the highest pulse population) (Step 7402) Dunng the initialization process the pulse interval duration is set to PSmin, l e , for maximum pulse population The value of PS* is varied from Psmin only if an Over- cunent recovery operation is in process (Step 7312) Thus in the absence of an Over-cunent condition, PS* is not greater than Psmin, no modulation is indicated and accordingly, the SCR signal at pin 2 of micro controller 6202 is maintained full on (Step 7404) The VR module is exited (Step 7406)
  • Step 7304 dunng Inverter and Over-cunent module 7300
  • PS* is set equal to the maximum interval (PSmax) between pulses
  • the interval between successive SCR pulses is measured, employing a counter SCR_CNTR Counter SCR_CNTR (cleared dunng initialization) is incremented once dunng every 260 microsecond cycle (Step 7408)
  • the SCR JZNTR count is then tested against the value of the pulse population delay interval PS* (Step 7410) If the count SCR_CNTR is not greater than or equal to the pulse population interval PS*, the voltage regulation module is exited (Step 7406), and process repeated dunng the next successive cycle This process continues until a number of cycles greater than or equal to the pulse interval delay count PS* is reached, indicating that the next successive pulse should be generated
  • SCR_CNTR count is cleared in preparation for the next pulse to be generated (Step 7412), and the SCR control signal at pin 2 of micro controller 6202 is activated (Step 7414)
  • the SCR control pulse is then turned off after a predetermined penod It is desirable that the
  • SCR pulse be sufficiently long to ensure activation of the rectifier SCRs, but short enough so that only a single pulse is provided at rail 542 per control signal SCR and preferably just sufficient to reliably fire the SCR
  • the duration of the SCR pulse is in the range of 5-50 microseconds, and typically in the range of 20-50 microseconds, depending on the sensitivity of the SCR
  • the duration of the SCR pulses is controlled employing the interrupt activated Timerl clock of micro controller 6202 Accordingly, interrupt ERQ5 is enabled (Step 7416), and timer Tl started (Step 7418). Interrupt IRQ5 is generated upon time out of timer Tl, I e., at, about 45-50 microseconds Refernng bnefly to Figure 74A, upon receipt of interrupt IRQ5, the interrupt is disabled
  • Step 7420 the SCR is turned off (Step 7422), and a return from the interrupt is effected (Step 7424)
  • the pulse population interval count is decremented (pulse population increased) (Step 7426), then is tested against PSmin (Step 7428) If PS is not greater or less than PSmin, a return from the subroutine VR OC is effected (Step 7406) If, on the other hand, PS* is less than or equal to PSmin, indicating that the modulation process has been completed, PS* is set equal to Psmin (reflecting that PSmin is the minimum permissible value) (Step 7430), and the module exited (Step 7406)
  • system 6100 effects a self-tuning process, potentially as often as once during each 260 microsecond cycle that the system is idling Bnefly, if throttle position count SW equals the full-closed position (e.g , 0) conesponding to idle, and the rail voltage V_ra ⁇ l is still in excess of the upper acceptable limit, a misalignment is indicated
  • Control signals arc generated in successive cycles to close the throttle by successive steps (without changing the SW count) until the voltage is reduced to within the acceptable range
  • T_CLOSE_D The value indicative of the designated minimum response time to an incremental closure (T_CLOSE_D) is loaded into the throttle delay timer T_DELAY JTMR (Step 7516) and the module is exited (Step 7504) This process is repeated each 260 microsecond cycle
  • dynamic control module 7700 is initiated to effect an accelerated closure of the throttle, in response to voltage out of limits conditions, as indicated by the state of the V JLMT signal at pm 18 of micro controller 6202
  • a stepping motor requires a minimum amount of time in which to respond to a step command.
  • the step motor does not respond to subsequent commands, applied before the minimum time period has lapsed
  • the system imposes additional constraints on the frequency of successive throttle adjustments; the engine will not adequately respond to successive throttle charges that are too proximate in time For example, a longer period of time is required to respond to an incremental opening of the throttle, than required to respond to an incremental closing
  • aesthetic, or consumer perception reasons sometimes make it desirable to establish a longer required delay between throttle adjustments than is mechanically necessary
  • over-voltage conditions exist however, with the nsk of damage to components, it is often desirable to minimize or reduce the delay between adjustment steps compared to that employed dunng normal throttle control
  • V J_MT signal at pin 18 If the V J_MT signal at pin 18 is not active, dynamic control module 7700 is exited, and throttle module 7700 initiated (Step 7606)
  • Step 7606 A separate count STEP JTNT, indicative of the time elapsed since the last throttle change dunng accelerated (dynamic) close down procedures is established (register 6240) STPJC!NT is incremented dunng each 260 microsecond cycle during over voltage conditions (Step 7608), then compared against a predetermined number #STEPJDYN indicative of the minimum required elapsed time between successive throttle changes dunng an accelerated (dynamic) close down #STEPJDYN may be hard programmed as a constant, or may be maintained as a vanable in, e.g., register 6242 If STEP_CNT is greater than #STEPJDYN, I e , the minimum required time period has elapsed, and the throttle incrementally closed- STEP_
  • micro controller 6202 includes respective internal comparators associated with pins 8 and 9, respectively, each receptive of the signal at pin 10 as a reference Feedback signal VJ ⁇ B is applied to pin 10; the reference signals indicative of the upper and lower bounds of acceptable values (low) for feedback signal VJFB, are applied to pins 8 and 9, respectively Accordingly, the output of the comparators indicate whether or not VJFB is above the upper bound, or below the lower bound of acceptable values Feedback signal V_FB is sampled (Step 7702)
  • Step 7704 the output of the pin 9 comparator is tested (Step 7704) and, if V JFB is less than V J_OW, the POSDIR routine is called (Step 7706) to effect incremental opening of the throttle The module is then exited (Step 7707)
  • Step 7702 If V JFB is not less than V_LOW, I e , not below the lower bound of the acceptable range, the output of the comparator associated with pin 8 of micro controller 6202 (receptive of the signal indicative of the upper bound) (V J-II) of the acceptable range of values, is tested (Step 7708) If the output of the comparator indicates that VJFB is in excess of the upper limit, the NEGIDR subroutine is called (Step 7710) to incrementally close the throttle, and an exit effected (Step 7707)
  • Step 7707 If the test of the pm 9 comparator indicates that the V_FB is not less than V JLOW, and the test of the pin 8 comparator indicates that V J ⁇ B is not greater than the upper acceptable range V J-II, feedback signal V JFB must be within the acceptable range ot values If so, the capacitor in inverter 2700 is enabled, and if approp ⁇ ate switched on (Step 7712) An exit is then effected (Step 7707)

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Combustion & Propulsion (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Control Of Eletrric Generators (AREA)

Abstract

Un convertisseur de puissance (2700) produit, à partir d'un signal redressé (+135), un signal de sortie d'un profil de tension spécifique (2800). Le convertisseur de puissance comprend un convertisseur et un régulateur. Le convertisseur inclut un premier et un deuxième noeuds de jonction (2703, 2707) entre lesquels il reçoit le signal redressé; une première et une deuxième bornes de sortie du convertisseur (L1, L2); un premier, un deuxième, un troisième et un quatrième commutateurs (2702, 2704, 2706, 2708) permettant d'établir sélectivement des circuits de courant (3000) entre le premier noeud de jonction et la première ou la deuxième borne de sortie du convertisseur, et entre le deuxième noeud de jonction et l'autre première ou deuxième borne de sortie du convertisseur; et une capacité (2902) montée en série avec un cinquième commutateur (2908). Le cinquième commutateur est shunté par une diode (2906). La diode conduit un courant de charge pour la capacité tandis que le cinquième commutateur fait passer un courant de décharge pour la capacité. La capacité et le cinquième commutateur en série sont montés entre les premier et deuxième noeuds de jonction. Le régulateur fournit une pluralité de signaux de commande de fonctionnement aux premier, deuxième, troisième quatrième et cinquième commutateurs afin de produire, aux bornes de sortie du convertisseur, le signal de sortie ayant le profil de tension attendu. Le courant de décharge fournit une partie (T3-T4) du profil de tension attendu.
PCT/US1997/013978 1996-08-12 1997-08-12 Convertisseur de puissance fournissant une onde de sortie specifique WO1998007230A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU41473/97A AU4147397A (en) 1996-08-12 1997-08-12 Power converter providing desired output waveform
CA002263451A CA2263451A1 (fr) 1996-08-12 1997-08-12 Convertisseur de puissance fournissant une onde de sortie specifique

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/695,558 1996-08-12
US08/695,558 US5900722A (en) 1994-09-14 1996-08-12 Multimode power converter
US08/752,230 1996-11-19
US08/752,230 US5886504A (en) 1994-09-14 1996-11-19 Throttle controlled generator system

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WO1998007230A1 true WO1998007230A1 (fr) 1998-02-19

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PCT/US1997/013974 WO1998007224A1 (fr) 1996-08-12 1997-08-12 Convertisseur de puissance avec recouvrement de condition anormale

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PCT/US1997/013974 WO1998007224A1 (fr) 1996-08-12 1997-08-12 Convertisseur de puissance avec recouvrement de condition anormale

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
US20220103104A1 (en) * 2020-09-26 2022-03-31 Emerson Electric Co. Systems and methods for controlling inducer motor speed
US12278580B2 (en) 2020-09-26 2025-04-15 Copeland Comfort Control Lp Systems and methods for controlling inducer motor speed

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US6801019B2 (en) 2000-01-28 2004-10-05 Newage International Limited AC power generating system
AU2003206751A1 (en) * 2003-01-20 2004-08-13 Impex Honsberg Power supply system comprising a step-up converter
RU2582648C2 (ru) * 2015-04-20 2016-04-27 Александр Абрамович Часовской Устройство электромеханического управления

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Cited By (3)

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Publication number Priority date Publication date Assignee Title
US20220103104A1 (en) * 2020-09-26 2022-03-31 Emerson Electric Co. Systems and methods for controlling inducer motor speed
US11611302B2 (en) * 2020-09-26 2023-03-21 Emerson Electric Co. Systems and methods for controlling inducer motor speed
US12278580B2 (en) 2020-09-26 2025-04-15 Copeland Comfort Control Lp Systems and methods for controlling inducer motor speed

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AU4147197A (en) 1998-03-06
CA2263451A1 (fr) 1998-02-19
AU4147397A (en) 1998-03-06
WO1998007224A1 (fr) 1998-02-19

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