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WO1998008252A1 - Procede de croissance differentielle d'oxyde de champ - Google Patents

Procede de croissance differentielle d'oxyde de champ Download PDF

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Publication number
WO1998008252A1
WO1998008252A1 PCT/US1997/014881 US9714881W WO9808252A1 WO 1998008252 A1 WO1998008252 A1 WO 1998008252A1 US 9714881 W US9714881 W US 9714881W WO 9808252 A1 WO9808252 A1 WO 9808252A1
Authority
WO
WIPO (PCT)
Prior art keywords
window
forming
width
field oxide
thickness
Prior art date
Application number
PCT/US1997/014881
Other languages
English (en)
Inventor
Scott Luning
David Kuan-Yu Liu
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1998008252A1 publication Critical patent/WO1998008252A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

Definitions

  • the invention relates to local oxidation of silicon (LOCOS) processes and more particularly to differential field oxide growth on a single wafer.
  • LOCS local oxidation of silicon
  • active devices are formed on a semiconductor substrate.
  • PLDs programmable logic devices
  • active devices must be electrically isolated from each other.
  • One way to isolate the devices is to grow a field oxide region between devices, as shown in Fig. 1, typically through a local oxidation of silicon (LOCOS) process.
  • LOC local oxidation of silicon
  • LOCOS processes typically begin with a silicon substrate upon which is grown a thin pad oxide (typically 100A-500A) .
  • a nitride (Si ⁇ y ) layer is deposited over the pad oxide.
  • the nitride layer is patterned and parts are removed to form windows exposing the pad oxide.
  • the resulting structure is shown in the cross-section of Fig. 2A. Occasionally some or all of that portion of the pad oxide underlying the removed nitride portion is also removed exposing the substrate.
  • the wafer is then exposed to an oxidizing ambient, either a wet or dry oxidant, and oxidation of the exposed substrate and pad oxide takes place.
  • the result, shown in Fig. 2B is a field oxide region that effectively isolates neighboring devices (transistors) from one another. Note that a pad oxide is not necessary for oxidation but is beneficial in relieving stress that occurs.
  • the field oxide region not only grows vertically, up into the window formed by the patterned nitride and directly below the window into the substrate, but the oxidant also diffuses laterally, under the nitride.
  • This lateral diffusion is known as encroachment ( ⁇ W) and forms an area in the field oxide known as the "bird's beak.”
  • ⁇ W encroachment
  • Encroachment is typically undesirable as it causes a larger field oxide area than is desired, thus decreasing packing density of devices per wafer. Because as field oxide thickness increases, encroachment also increases, one way to minimize encroachment is to use the minimum field oxide thickness required.
  • Memory devices can typically be divided into core and periphery regions, shown in the block diagram of Fig. 3.
  • the core region 110 contains specialized memory cells which are used solely for information storage, while the periphery region 100 contains various logic needed to make stored information accessible, making the two regions functionally distinct.
  • Such center versus edge placement is typical, however, but not required of memory cell structure.
  • the present invention is directed toward a method for differential field oxide growth. It is desirable on some integrated circuits, and particularly memory devices, that the isolation, or field oxide, regions be of different thicknesses in the core area and the periphery area of the device. However, it is further desirable to be able to achieve differential field oxide growth using only one patterning step and one growth step.
  • the process used to achieve differential field oxide growth in one patterning step and one growth step begins with a silicon substrate upon which is formed a pad oxide layer and a masking layer. Portions of the masking layer are removed to form "windows" in the masking layer.
  • the window width in the core is smaller than the window width in the periphery. Use of the smaller window in the core takes advantage of the "field thinning effect.”
  • the window width is smaller than a particular width specific to each oxidation process, oxidation will be significantly inhibited causing a smaller field oxide thickness to be grown than if the window width were larger.
  • different field oxide thicknesses can be grown in a single growth step.
  • the process in accordance with the invention is advantageous in that it improves packing density of devices per wafer because smaller field oxide thicknesses will be used when larger field oxide thicknesses are not required.
  • Fig. 1 is a cross-sectional view of a wafer construct having isolation regions
  • Fig. 2A is a cross-sectional view of wafer construct prior to a conventional LOCOS process
  • Fig. 2B is a cross-sectional view of the wafer construct immediately subsequent to oxidation in a conventional LOCOS process
  • Fig. 3 is a representational block diagram of a memory device
  • Fig. 4A shows a cross-sectional view of a wafer construct following the first step of one method for developing a wafer construct having differential field oxide thicknesses
  • Fig. 4B is a cross-sectional view of a wafer construct following the second step in one method of forming a wafer construct having differential field oxide thicknesses;
  • Fig. 5 is a generic characteristic curve of an oxidation process, showing nitride spacing to field oxide thickness;
  • Fig. 6 is a cross-sectional view of a wafer construct resulting from one embodiment of the present invention.
  • Fig. 7 is shows the characteristic curves of nitride spacing to field oxide thickness for a dry oxidation process and for a wet oxidation process
  • Fig. 8A shows a cross-sectional view of a wafer construct using spacers and trenching resulting from one embodiment of the present invention immediately prior to oxidation;
  • Fig. 8B is a cross-sectional view of the wafer construct resulting from the process according to one embodiment of the present invention.
  • the isolation regions in the core 110 can be significantly smaller in thickness (e.g., 2500A) than the isolation regions in the periphery 100 (e.g., 4000A) .
  • One way to achieve dual field oxide thicknesses is to grow the field oxide in two steps: first, as shown in Fig. 4A, patterning the nitride in the periphery to form windows with width W p and growing a partial thickness in the periphery while the core remains completely covered with nitride; and second, as shown in Fig. 4B, patterning the core to form windows with width W r equal to width p and growing the field oxide in the core to t c while the field oxide in the periphery continues growing to its final thickness of t p .
  • this method accomplishes the goal of having dual field oxide thicknesses, it requires two patterning steps and two field oxide growths .
  • the nitride spacing to field oxide thickness curve will generally appear as shown in Fig. 5 for most oxidation processes.
  • the characteristic curve of the oxidation process generically shown in Fig. 5.
  • window width w By tracing a line horizontally from a thickness t to the curve and then from the curve vertically down, a determination of window width w can be made for thickness t.
  • the nitride is then etched to pattern the surface with the various window widths determined from the characteristic curve, e.g. , W p and W c , as shown in Fig. 6. Note that the portion of the pad oxide 130 underlying the removed nitride portions may also be completely or partially removed in this etch step in one embodiment of the invention.
  • Oxidation of the exposed regions can then take place growing oxides to a thickness t p in the periphery and t c in the core. If W r is found from the curve of Fig. 5 in the area where the curve "rolls off, " and W p is taken from that part of the curve that is relatively flat, then, once oxidized, the resulting t c will be smaller than the resulting t , as shown in Fig. 6. Thus, only one patterning step and one field oxide growth is required.
  • Fig. 7 shows curves for a dry oxide process at 1125°C as well as a wet oxide process at 1000°C. Note that the "rolloff" shown on these curves has conventionally been thought of as undesirable and most LOCOS processes avoid “windows” falling in the "rolloff” region.
  • the wet oxidation process at 1000°C shown by curve 710 significant reductions in field oxide thickness occur when nitride spacing is below a width of one micron.
  • curve 720 significant reductions occur in field oxide thickness at a window spacing of 0.4 microns and below.
  • the dry oxidation process used in one embodiment of the invention is a multi-step oxidation process, in which a first oxidation step is performed at a temperature of approximately 1000°C in an atmosphere comprising approximately 0.1-10% HC1 and 90-99.9% 0 2 for a period of approximately 30 to 120 minutes. This first oxidation step forms a thin oxide layer over nitride 120 to protect the nitride from reacting with
  • HCl during the later oxidation steps.
  • the reaction of nitride 120 with HCl is dependent on temperature and does not occur below approximately 1050°C.
  • the purpose of adding HCl to the oxidizing atmosphere for the first oxidation step is to clean the surface to be oxidized by removing, for example, metallic contamination.
  • a second oxidation step is performed at a temperature of approximately 1125"C in an atmosphere comprising approximately 0.1-10% HCl and 90-99.9% 0 2 for a period of approximately 4 to 10 hours.
  • concentrations of HCl and 0 2 in the oxidizing environment may be optimized by those of ordinary skill in the art.
  • HCl is added to the oxidizing environment in the second oxidation step to prevent stacking faults. It is believed that 0 2 is injected into the crystalline lattice of silicon substrate 135 and that this interstitial 0 2 causes mismatches in the lattice which lead to stacking faults. The HCl neutralizes the interstitial 0 2 , thereby preventing stacking faults.
  • Both oxidation steps include a stabilization period in an inert or oxidizing atmosphere.
  • the atmosphere for the stabilization period of the first oxidation step comprises 10-40% 0 2 and 60-90% Argon and the atmosphere for the stabilization period of the second oxidation step comprises approximately 100% Argon.
  • the atmosphere for the stabilization period of the second oxidation step comprises approximately 100% Argon.
  • spacers are used to decrease the window size in the nitride.
  • the nitride layer would be patterned and etched in the core region.
  • a spacer forming material typically nitride
  • the nitride layer could then be patterned and etched in the periphery to form windows equal in width to those formed in the core prior to spacer formation.
  • Field oxide growth could then occur in a single growth step. While this embodiment adds extra steps compared to other embodiments of the invention, such spacers could be useful in lithographically limited situations.
  • Figs. 8A and 8B show an embodiment of the invention using both spacer formation and substrate trenching.
  • Fig. 8A shows the wafer structure prior to oxidation having spacers 175 positioned within window 170 and abutting nitride layer 120 and having a trench 180 etched within substrate 135.
  • Fig. 8B shows the structure subsequent to oxidation with field oxide region 160.
  • Nitride spacers 125 on the sides of the original nitride stack may further improve encroachment ⁇ W by approximately the width of the spacer 175.
  • Trenching 180, while trading back some of the ⁇ W gained with the spacers, may be used to improve resulting planarity.
  • the characteristic nitride spacing to field oxide thickness curve will vary between embodiments.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

Procédé LOCOS destiné à former une épaisseur différentielle d'oxyde de champ sur une tranche lors d'une seule opération de formation de motifs et d'une seule opération de croissance. Lorsque l'on forme les motifs sur la couche de masquage, on forme au moins deux largeurs de fenêtre dans ladite couche, mettant ainsi à nu le substrat sous-jacent et l'oxyde de plage de connexion. Lorsque l'une des largeurs de fenêtre est suffisamment petite, l'oxydation du substrat est inhibée, ce qui entraîne une réduction de la croissance et donc une réduction de l'épaisseur d'oxyde de champ dans ladite fenêtre, par rapport aux fenêtres plus grandes formées dans la même couche de masquage, ce qui crée des épaisseurs différentielles d'oxyde de champ lors d'une seule opération de croissance.
PCT/US1997/014881 1996-08-22 1997-08-22 Procede de croissance differentielle d'oxyde de champ WO1998008252A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70276696A 1996-08-22 1996-08-22
US08/702,766 1996-08-22

Publications (1)

Publication Number Publication Date
WO1998008252A1 true WO1998008252A1 (fr) 1998-02-26

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Country Status (1)

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WO (1) WO1998008252A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107527857A (zh) * 2016-06-22 2017-12-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987093A (en) * 1987-04-15 1991-01-22 Texas Instruments Incorporated Through-field implant isolated devices and method
EP0476988A1 (fr) * 1990-09-18 1992-03-25 Sharp Kabushiki Kaisha Procédé pour la fabrication d'une région d'isolation d'un dispositif à semi-conducteur
JPH0582516A (ja) * 1991-09-24 1993-04-02 Sony Corp 半導体装置
US5372951A (en) * 1993-10-01 1994-12-13 Advanced Micro Devices, Inc. Method of making a semiconductor having selectively enhanced field oxide areas
US5466623A (en) * 1987-07-01 1995-11-14 Mitsubishi Denki Kabushiki Kaisha Method of making semiconductor integrated circuit having isolation oxide regions with different thickness
JPH0855845A (ja) * 1994-08-11 1996-02-27 Fujitsu Ltd 半導体装置の製造方法
JPH08172087A (ja) * 1994-06-16 1996-07-02 Lg Semicon Co Ltd 半導体素子の分離膜の構造及びその形成方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987093A (en) * 1987-04-15 1991-01-22 Texas Instruments Incorporated Through-field implant isolated devices and method
US5466623A (en) * 1987-07-01 1995-11-14 Mitsubishi Denki Kabushiki Kaisha Method of making semiconductor integrated circuit having isolation oxide regions with different thickness
EP0476988A1 (fr) * 1990-09-18 1992-03-25 Sharp Kabushiki Kaisha Procédé pour la fabrication d'une région d'isolation d'un dispositif à semi-conducteur
JPH0582516A (ja) * 1991-09-24 1993-04-02 Sony Corp 半導体装置
US5372951A (en) * 1993-10-01 1994-12-13 Advanced Micro Devices, Inc. Method of making a semiconductor having selectively enhanced field oxide areas
JPH08172087A (ja) * 1994-06-16 1996-07-02 Lg Semicon Co Ltd 半導体素子の分離膜の構造及びその形成方法
US5646052A (en) * 1994-06-16 1997-07-08 Goldstar Electron Co., Ltd. Isolation region structure of semiconductor device and method for making
JPH0855845A (ja) * 1994-08-11 1996-02-27 Fujitsu Ltd 半導体装置の製造方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BELLUTTI P ET AL: "DW-LOCOS: A CONVENIENT VLSI ISOLATION TECHNIQUE", SEMICONDUCTOR SCIENCE AND TECHNOLOGY, vol. 10, no. 12, 1 December 1995 (1995-12-01), pages 1700 - 1705, XP000545070 *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 415 (E - 1407) 3 August 1993 (1993-08-03) *
PATENT ABSTRACTS OF JAPAN vol. 096, no. 006 28 June 1996 (1996-06-28) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107527857A (zh) * 2016-06-22 2017-12-29 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN107527857B (zh) * 2016-06-22 2020-06-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置

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