WO1998009329A1 - Dispositif a semi-conducteur scelle par resine, et son procede de production - Google Patents
Dispositif a semi-conducteur scelle par resine, et son procede de production Download PDFInfo
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- WO1998009329A1 WO1998009329A1 PCT/JP1996/002418 JP9602418W WO9809329A1 WO 1998009329 A1 WO1998009329 A1 WO 1998009329A1 JP 9602418 W JP9602418 W JP 9602418W WO 9809329 A1 WO9809329 A1 WO 9809329A1
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- resin
- die pad
- semiconductor chip
- semiconductor device
- chip
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- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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Definitions
- the present invention relates to a resin-encapsulated semiconductor device, and more particularly to a resin-encapsulated semiconductor device in which a resin encapsulant for encapsulating a semiconductor chip mounted on a die pad is formed by transfer molding. It relates to technology that is effective when applied to semiconductor devices. Background art
- a resin-sealed semiconductor device there is a resin-sealed semiconductor device in which a semiconductor chip mounted on a chip mounting surface of a die pad is sealed with a resin-sealed body.
- a semiconductor chip is mounted on a chip mounting surface of a die pad supported on a frame of a lead frame via a support lead, and thereafter, the semiconductor chip is disposed on a main surface of the semiconductor chip.
- the external terminal (bonding pad) is electrically connected to a part of the inner lead of the lead supported by the frame of the lead frame with a bonding wire, and then the inner lead of the support lead, die pad, semiconductor chip, and lead is connected.
- a part and a bonding wire and the like are sealed with a resin sealing body, and thereafter, the support lead and the outer part of the lead are cut from the frame of the lead frame, and then the outer part of the lead is formed into a predetermined shape. It is formed by molding into
- the lead frame is formed of, for example, iron (Fe) -nickel (Ni) -based alloy or copper (Cu) or a copper-based alloy.
- the resin sealing The body is made of, for example, an epoxy resin.
- the resin sealing body is formed by a transfer mold method suitable for mass production. The transfer molding method uses a mold having a pot, a runner, an inflow gate, a cavity, and the like, and is resin-encapsulated with a resin injected into the cavity through the runner and the inflow gate from the pot. It is a method of forming the body.
- the die pad is formed with an outer dimension larger than the outer dimension of the semiconductor chip, moisture contained in the resin of the resin-sealed body easily accumulates on the back surface of the die pad. . For this reason, the moisture accumulated on the back surface of the die pad is used for the heat during the temperature cycle test, which is an environmental test after the completion of the resin-encapsulated semiconductor device, and the resin-encapsulated semiconductor device is mounted on the mounting surface of the mounting board. There is a problem that the resin expands and vaporizes due to the heat generated during mounting, causing cracks (resin cracks) in the resin sealing body.
- the present inventors have studied the resin-sealed semiconductor device having a die pad formed with an outer size smaller than the outer size of the semiconductor chip, and found the following problems.
- the length of the support lead for supporting the die pad becomes longer. Vertical fluctuations of the die pad caused by the flow of resin injected under pressure into the cavity become severe.
- the thickness of the resin seal is large, Since the thickness of the resin on the main surface of the chip and the thickness of the resin on the back surface of the semiconductor chip are large, there is no problem that the semiconductor chip, bonding wires, die pads, etc. are exposed from the resin sealing body. When the thickness of the resin sealing body is 1 mm or less, the thickness of the resin on the main surface of the semiconductor chip and the thickness of the resin on the back surface of the semiconductor chip become thin. Causes the semiconductor chip, bonding wire, die pad, etc. to be exposed.
- a resin-encapsulated semiconductor device having a die pad formed with an external dimension smaller than the external dimension of the semiconductor chip the thickness of the resin-encapsulated body cannot be reduced. I can't.
- a resin-encapsulated semiconductor device mounted on a small and lightweight device such as an IC card ( ⁇ integrated circuit card)
- an LQFP (ow profile) having a resin encapsulant thickness of 1.4 [mm] is used.
- a Q_uad Hlat F ⁇ ackag e) structure and a TQFP ⁇ hin Q_uad Fllat package) structure with a resin encapsulant thickness of about 1 [mm] have been developed. There is a demand for the development of a resin-encapsulated semiconductor device with a smaller thickness.
- An object of the present invention is to provide a technique capable of reducing the thickness of a resin-encapsulated semiconductor device.
- Another object of the present invention is to provide a technique capable of increasing the yield in the manufacturing process of a resin-sealed semiconductor device.
- a semiconductor chip (2) a semiconductor chip, a die pad on which the semiconductor chip is mounted, a support lead for supporting the die pad, and a resin sealing body for sealing the semiconductor chip, wherein the die pad is the semiconductor
- a method for manufacturing a resin-encapsulated semiconductor device wherein the external dimensions are smaller than the external dimensions of a chip, and the resin-encapsulated body is formed by a transfer molding method. Forming the resin-sealed body while supporting the back surface of the molded body with the inner wall surface of the cavity of the mold.
- the back surface of the die pad can be supported by the inner wall surface of the cavity of the molding die or an ejector pin. Therefore, the vertical fluctuation of the die pad caused by the flow of the resin injected into the cavity of the mold can be suppressed.
- the thickness of the resin sealing body is set to 1 [mm] or less, it is possible to prevent a problem that a semiconductor chip, a bonding wire, and the like are exposed from the resin sealing body. Thus, the thickness of the resin-encapsulated semiconductor device can be reduced.
- the length of the moisture intrusion path from the exposed area of the die pad to the main surface of the semiconductor chip can be lengthened by an amount corresponding to the distance from the die pad to the side surface of the semiconductor chip. Even with a structure that is exposed from one surface of the sealing body, the moisture resistance of the resin-sealed semiconductor device can be ensured.
- the vertical fluctuation of the die pad caused by the flow of the resin injected under pressure into the cavity of the mold can be suppressed.
- the flow of the resin and the flow of the resin on the back surface of the semiconductor chip are improved.
- FIG. 1 is a plan view of a resin-sealed semiconductor device according to a first embodiment of the present invention in a state where an upper portion of a resin-sealed body is removed.
- FIG. 2 is a cross-sectional view taken along a line AA shown in FIG.
- FIG. 3 is a sectional view taken along the line BB shown in FIG.
- FIG. 4 is an enlarged sectional view of a main part of FIG.
- FIG. 5 is a plan view of a lead frame used in a manufacturing process of the resin-encapsulated semiconductor device.
- FIG. 6 is a fragmentary cross-sectional view for explaining the method for manufacturing the resin-encapsulated semiconductor device.
- FIG. 7 is a fragmentary cross-sectional view for describing the method for manufacturing the resin-encapsulated semiconductor device.
- FIG. 8 is a plan view of another lead frame used in the manufacturing process of the resin-sealed semiconductor device.
- FIG. 9 is a cross-sectional view showing a modification of the resin-encapsulated semiconductor device.
- FIG. 10 is a cross-sectional view of the resin-encapsulated semiconductor device according to Embodiment 2 of the present invention. It is a top view in the state where it was removed.
- FIG. 11 is a cross-sectional view taken along a line C-C shown in FIG. 10
- FIG. 12 is a cross-sectional view taken along a line D-D shown in FIG.
- FIG. 13 is an enlarged sectional view of a main part of FIG.
- FIG. 14 is a plan view of a lead frame used in a manufacturing process of the resin-sealed semiconductor device.
- FIG. 15 is a fragmentary cross-sectional view for explaining the method for manufacturing the resin-encapsulated semiconductor device.
- FIG. 16 is a fragmentary cross-sectional view for explaining the method for manufacturing the resin-encapsulated semiconductor device.
- FIG. 17 is a plan view of the resin-sealed semiconductor device according to the third embodiment of the present invention in a state where an upper portion of a resin-sealed body is removed.
- FIG. 18 is a cross-sectional view taken along line EE shown in FIG. 17, and FIG. 19 is a cross-sectional view taken along line FF shown in FIG.
- FIG. 20 is a plan view of a lead frame used in a manufacturing process of the resin-sealed semiconductor device.
- FIG. 21 is a plan view of another lead frame used in the manufacturing process of the resin-sealed semiconductor device.
- a semiconductor chip 2 is mounted on a chip mounting surface of a die pad 3A.
- the planar shape of the semiconductor chip 2 is, for example, a square shape having an outer dimension of 9 [mm] ⁇ 9 [mm].
- the semiconductor chip 2 has a structure mainly composed of, for example, a semiconductor substrate made of single crystal silicon and a wiring layer formed on the main surface thereof.
- the semiconductor chip 2 includes, for example, a logic circuit system or a mixed circuit system in which a logic circuit system and a storage circuit system are mixed. Further, on the main surface of the semiconductor chip 2, a plurality of external terminals (bonding pads) 2A are arranged along each side of the main surface. Each of the plurality of external terminals 2A is formed in the uppermost wiring layer of the wiring layers of the semiconductor chip 2, and is formed of, for example, an aluminum (A 1) film or an aluminum alloy film.
- each inner part 3C1 of the plurality of leads 3C is electrically connected to each of the plurality of external terminals 2A arranged on the main surface of the semiconductor chip 2 via bonding wires 5. ing.
- bonding wire 5 for example, a gold (Au) wire is used.
- Au gold
- bonding wire 5 for example, an insulating resin is applied to the surface of an aluminum (A1) wire, a copper (Cu) wire, or a metal wire.
- a covered wire or the like may be used.
- the bonding wire 5 is connected by, for example, a bonding method using ultrasonic vibration in combination with thermocompression bonding.
- the die pad 3A is integrated with four support leads 3B.
- Each of the four support leads 3B is mounted on the frame of the lead frame in the state of the lead frame. I support A.
- Each of the four support leads 3B is arranged at a position where an X-shape is formed at the intersection of the die pad 3A.
- the width dimension of the support lead 3B is set to, for example, 0.4 [mm].
- the semiconductor chip 2, the die pad 3A, the support lead 3B, the inner part 3C1 of the lead 3C1, the bonding wire 5, and the like are sealed with a resin sealing body 1 formed by a transfer molding method.
- the resin sealing body 1 is made of, for example, a biphenyl-based resin or an ortho-cresol novolac-based resin to which a phenol-based curing agent, silicone and filler are added for the purpose of reducing stress. Is formed.
- the transfer molding method uses a mold with a pot, runner, inflow gate, and cavity, and is resin-encapsulated with resin that is injected into the cavity from the pot through the runner and the inflow gate. It is a method of forming a body.
- the planar shape of the resin sealing body 1 is, for example, a square shape having an outer dimension of 14 [mm] X 14 [mm].
- Outer sides 3C2 of the leads 3C are arranged outside each side of the resin sealing body 1.
- Each outer portion 3C2 of the plurality of leads 3C is arranged along each side of the resin sealing body 1, and is formed, for example, in a gull wing shape. That is, the resin-encapsulated semiconductor device of the present embodiment has a QFP (Quad Flat Package) structure.
- the planar shape of the die path 3A is, for example, a circular shape having an outer dimension of 3 [mm] ⁇ . That is, the die pad 3 of the present embodiment is formed with an outer dimension smaller than the outer dimension of the semiconductor chip 2.
- the die pad 3A does not exist outside the outer periphery of the semiconductor chip 2 and the middle part of the bonding wire 5 hangs down. However, since the die pad 3A and the bonding wire 5 do not come into contact with each other, the semiconductor chips 2 having different external dimensions can be mounted.
- the resin-sealed semiconductor device of the present embodiment has a structure in which the entire region on the back surface of the die pad 3A is exposed from the lower surface of the resin-sealed body 1. Exposure of the entire area of the rear surface of die pad 3A is achieved by supporting the rear surface of die pad 3A with the inner wall surface of the mold die cavity when resin molding 1 is formed by transfer molding. You.
- the central region of the back surface facing the main surface of the semiconductor chip 1 is bonded and fixed to the chip tower mounting surface of the die pad 3A with an adhesive 4 interposed therebetween, and the peripheral region of the back surface is formed of the resin sealing body 1. Covered with resin.
- the adhesive 4 is made of, for example, an epoxy silver (Ag) paste material.
- the adhesive 4 is applied to the chip tower mounting surface of the die pad 3A by a multi-point application method in the process of manufacturing the resin-encapsulated semiconductor device.
- the support lead 3B has a lead portion 3B1 sealed with a resin sealing body 1 and a surface (back) from the lower surface which is one surface of the resin sealing body 1. And the exposed lead portion 3B2.
- the lead portion 3B1 is located at the same position as the inner part 3C1 of the lead 3C shown in FIG. 2 in the thickness direction (vertical direction), and the lead portion 3B2 is In the direction (vertical direction), it is located at the same position as the position of the die pad 3A. That is, in the resin-encapsulated semiconductor device of the present embodiment, the chip mounting surface of the die pad 3A is lowered in the plate thickness direction from the upper surface (bonding surface) of the inner part 3C1 of the lead 3C. As shown in FIG.
- the thickness dimension A of the semiconductor chip 2 is set to, for example, 0.2 [mm].
- the thickness B of the resin sealing body 1 is set to, for example, 0.5 [mm].
- the thickness B 1 of the resin on the main surface of the semiconductor chip 2 is set to, for example, 0.16 [mm]
- the resin on the back surface of the semiconductor chip 2 is set to 0.16 [mm].
- the thickness dimension B2 is set to, for example, 0.14 [mm].
- the thickness C of the die pad 3A is set to, for example, 0.13 [mm].
- the height D of the resin-encapsulated semiconductor device is set to, for example, 0.6 to 0.6. 7 [mm] is set.
- the resin-encapsulated semiconductor device having the above-described configuration is the same as that shown in FIG. It is formed by a manufacturing process using frame 3.
- a die pad 3A, four support leads 3B, a plurality of leads 3C, and the like are arranged in an area defined by a frame 3E.
- the die pad 3A is supported by the frame 3E via four support leads 3B.
- Each of the plurality of leads 3C is supported by a frame 3E, and is connected to each other by a dam (bar) 3D.
- Each of the die pad 3A, the support lead 3B, and the lead 3C is integrated with the frame 3E.
- the lead 3C includes an inner part 3C1 sealed with the resin sealing body 1, and an outer part 3C2 molded into a predetermined shape.
- the support lead 3B has a lead portion 3B1 located at the same position as the inner portion 3C1 of the lead 3C in the plate thickness direction, and a lead portion 3B inner portion 3C in the plate thickness direction. And a lead portion 3B2 located at a position lower than C1.
- the lead frame 3 is formed of, for example, an iron (Fe) -nickel (Ni) -based alloy, copper (Cu), or a copper-based alloy.
- the lead frame 3 is formed by subjecting a flat plate material to etching or pressing, forming a predetermined pattern, and then pressing the supporting lead 3B.
- the length of the support lead 3B becomes longer as the outer dimensions of the die pad 3A become smaller, the length of the die pad 3A is easily changed in the vertical direction. Further, since the width of the support lead 3B becomes narrower as the number of pins is increased, the die pad 3A is liable to fluctuate in the vertical direction. In addition, the thickness of the support lead 3B is reduced as the thickness of the resin sealing body 1 is reduced, so that the die pad 3A is liable to change in the vertical direction.
- a method for manufacturing the resin-encapsulated semiconductor device will be described. First, a lead frame 3 shown in FIG. 5 is prepared.
- an adhesive 4 is applied to the chip mounting surface of the die pad 3A of the lead frame 3 by a multi-point coating method.
- the semiconductor chip 2 is mounted on the chip tower surface of the die pad 3A with the adhesive 4 interposed therebetween.
- the semiconductor chip 2 is bonded and fixed to the chip mounting surface of the die pad 3A with an adhesive 4 therebetween.
- the external terminals 2 A of the semiconductor chip 2 and the inner portions 3 C 1 of the leads 3 C of the lead frame 3 are electrically connected by bonding wires 5.
- the lead frame 3 is placed between the upper mold 1 OA and the lower mold 10 B of the mold 10, and the mold 10 is formed.
- the inner part 3C1 of the semiconductor chip 2, die pad 3A, support lead 3B, lead 3C, and bonder In addition to placing the mounting wire 5 etc., the back surface of the die pad 3 A is brought into contact with the inner wall surface 11 A of the cavity 11, and the inner surface 11 A of the cavity 11 is used to contact the back surface of the die pad 3 A.
- the inner part 3C1 of the semiconductor chip 2 die pad 3A
- support lead 3B lead 3C
- bonder In addition to placing the mounting wire 5 etc., the back surface of the die pad 3 A is brought into contact with the inner wall surface 11 A of the cavity 11, and the inner surface 11 A of the cavity 11 is used to contact the back surface of the die pad 3 A.
- the lower surface (back surface) of the lead portion 3B2 of the support lead 3B also comes into contact with the inner wall surface 11A of the cavity 11 and is supported by the inner wall surface 11A of the cavity 11.
- the back surface of the die pad 3A is pressed against the inner wall surface 11A of the cavity 11 by the elastic force of the support lead 3B.
- the lead portion 3B2 of the support lead 3B is pressed in the same manner.
- the mold 10 has a cavity (not shown), a runner (not shown), and an inflow gate 12 in addition to the cavity 11.
- the inflow gate 1 2 fills the cavity 11 with resin through the upper and lower surfaces of the lead frame 3. It has a structure that
- a resin is pressure-injected into the cavity 11 from the pot of the mold 10 through the runner and the inflow gate 12, and the back surface of the die pad 3 A is exposed to the inner wall surface 11 A of the cavity 11.
- the resin sealing body 1 is formed while supporting with.
- the flow is caused by the flow of the resin injected into the cavity 11 of the mold 10 by pressure. Vertical fluctuation of the die pad 3A is suppressed.
- the upward and downward fluctuations of the die pad caused by the flow of the resin injected under pressure into the cavity of the molding die are suppressed, so that the flow of the resin on the main surface of the semiconductor chip 2 and the flow of the semiconductor chip The flow of the resin on the back surface of 2 is improved. Also, since the back surface of the die pad 3A and the back surface of the lead portion 3B2 of the support lead 3B are in contact with the inner wall surface 11A of the cavity 11, these back surfaces are resin-sealed. It is exposed from the lower surface which is one surface of the body 1.
- the back surface of the die pad 3A and the back surface of the lead portion 3B1 of the support lead 3B are pressed against the inner wall surface 11A of the cavity 11 by the elastic force of the support lead 3B.
- the resin does not flow around the back surface of 3A and the back surface of the lead 3B1 of the support lead 3B.
- the semiconductor chip 2, the lead portion 3B1 of the support lead 3B, and the inner part 3 of the lead 3C, excluding the die portion 3A and the lead portion 3B2 of the support lead 3B, are used.
- C 1 and the bonding wires 5 are sealed with the resin sealing body 1.
- the support lead 3B and the lead 3C are cut from the frame 3E of the lead frame 3, and then, the outer portion 3C2 of the lead 3C is formed into a gulling shape, whereby the first The resin-encapsulated semiconductor device shown in FIGS. 2, 3 and 3 is almost completed.
- the following operational effects can be obtained.
- the die pad 3A is formed with an outer dimension smaller than the outer dimension of the semiconductor chip 2, and the resin sealing body 1 is formed by a transfer molding method.
- the resin sealing body 1 is formed by a transfer molding method. Dino, when forming. Since the back surface of the pad 3 A can be supported by the inner wall surface 11 A of the mold 11 of the mold 11, the flow of the resin injected into the cavity 11 of the mold 10 is pressurized.
- the fluctuation of the die pad 3A in the vertical direction caused by this can be suppressed.
- the thickness of the resin sealing body 1 is set to 1 [mm] or less, the problem that the semiconductor chip 2 and the bonding wires 5 are exposed from the resin sealing body 1 can be prevented.
- the thickness of the semiconductor device can be reduced.
- a part of the rear surface of the semiconductor chip 2 is fixed to the chip mounting surface of the die pad 3A with an adhesive 4 interposed therebetween, and the other region of the rear surface of the semiconductor chip is By covering with the resin of the sealing body 1, moisture that reaches the main surface of the semiconductor chip 2 from the exposed area of the die pad 3 A by an amount corresponding to the distance from the die pad 3 A to the side surface of the semiconductor chip 2. Since the path of the path can be lengthened, the moisture resistance of the resin-sealed-type semiconductor device is ensured even if the back surface of the die pad 3A is configured to be exposed from one surface of the resin-sealed body 1. can do.
- the die pad 3A is formed with an outer dimension smaller than the outer dimension of the semiconductor chip 2
- the resin sealing body 1 is formed by a transfer molding method.
- the manufacturing method of the above comprising a step of forming the resin sealing body 1 while supporting the back surface of the die pad 3A on the inner wall surface 11A of the cavity 11 of the mold 10 Since the vertical fluctuation of the die pad caused by the flow of the resin pressurized into the cavity 11 of the mold 10 can be suppressed, the flow of the resin on the main surface of the semiconductor chip 2 can be suppressed. And resin on the back of semiconductor chip 2 Flow is improved. As a result, the occurrence of voids in the resin-sealed body 1 can be prevented, so that the yield in the manufacturing process of the resin-sealed semiconductor device can be increased.
- the resin-sealed semiconductor device may be formed by a manufacturing process using the lead frame 3 shown in FIG.
- the inner part 3C1 of the lead 3C and the inner part 3C1 of the other lead 3C are connected to each other with the insulating film 3F, and the inner part of the lead 3C is also connected.
- 3C 1 and the lead portion 3B 1 of the support lead 3B are connected to each other by an insulating film 3F.
- the resin-encapsulated semiconductor device may have a structure in which the back surface of the die pad 3A is located outside one surface of the resin encapsulant 1. In this case, the thickness of the resin sealing body 1 can be reduced by an amount corresponding to the distance between the back surface of the die pad 3A and one surface of the resin sealing body 1.
- the resin-encapsulated semiconductor device has a structure in which the back surface of the lead portion 3B2 of the support lead 3B is positioned outside one surface of the resin-encapsulated body 1. May be configured.
- the thickness of the support lead 3B can be increased by an amount corresponding to the distance between the back surface of the lead portion 3B2 of the support lead 3B and one surface of the resin sealing body 1. Since the mechanical strength of 3B can be increased, when the resin sealing body 1 is formed by the trans-famould method, the vertical fluctuation of the die pad 3A can be suppressed.
- a semiconductor chip 2 is mounted on a chip stimulating surface of a die pad 3A.
- the planar shape of the semiconductor chip 2 is, for example, a square shape having an outer dimension of 9 [mm] ⁇ 9 [mm].
- a plurality of external terminals (bonding pads) 2A are arranged along each side of the main surface.
- each inner part 3 C 1 of the plurality of leads 3 C is electrically connected to each of the plurality of external terminals 2 A arranged on the main surface of the semiconductor chip 2 via a bonding wire 5. It is connected.
- the die pad 3A is integrated with four support leads 3B. Each of the four support leads 3B is in a state of a lead frame.
- the die pad 3A is mounted on a frame of the lead frame. I support it.
- Each of the four support leads 3B is arranged at a position where an X-shape is formed at the intersection of the die pad 3A.
- the semiconductor chip 2, the die pad 3A, the inner part 3C1 of the lead 3C, the bonding wire, and the like are sealed by a resin sealing body 1 formed by a transfer molding method.
- the planar shape of the resin sealing body 1 is, for example, a square shape having an outer dimension of 14 [mm] ⁇ 14 [mm].
- Outer sides 3C2 of the leads 3C are arranged outside each side of the resin sealing body 1.
- Each outer portion 3C2 of the plurality of leads 3C is arranged along each side of the resin sealing body 1, and is formed, for example, in a gull wing shape.
- the planar shape of the die pad 3A is X-shaped.
- the dipack 3A is formed with an outer dimension smaller than the outer dimension of the semiconductor chip 2, and is formed with a plane area smaller than the plane area of the semiconductor chip 2.
- the die pad 3A is formed, for example, with an X-shaped outer dimension having an outermost plane area of 5 [mm] X 5 [mm].
- the back surface of the die pad 3 A facing the chip tower surface is located inside the lower surface which is one surface of the resin sealing body 1.
- the central region on the back surface of the die pad 3A is exposed from the lower surface of the resin sealing body 1, and the peripheral region on the back surface of the die pad 3A is covered with the resin of the resin sealing body 1. That is, the resin-encapsulated semiconductor device of the present embodiment has The area is configured to be exposed from the lower surface of the resin sealing body 1. Exposure of the central region of the back surface of the dipad 3A is achieved by supporting the back surface of the die pad 3A with the ejector pins of the mold when the resin sealing body 1 is formed by the transfer molding method. .
- the central region of the back surface facing the main surface of the semiconductor chip 2 is bonded and fixed to the chip tower mounting surface of the die pad 3A with an adhesive 4 interposed therebetween, and the peripheral region of the back surface is formed of the resin sealing body 1. Covered with resin.
- the support lead 3B is composed of a lead 3B1 sealed with a resin sealing body 1 and a front surface (back surface) from a lower surface which is one surface of the resin sealing body 1. And the exposed lead portion 3B2.
- the lead portion 3B1 is located at the same position as the inner part 3C1 of the lead 3C shown in FIG. 11 in the plate thickness direction (vertical direction), and the lead portion 3B2 is In the thickness direction (vertical direction), it is located at the same position as the position of the die pad 3A. That is, in the resin-encapsulated semiconductor device of the present embodiment, the chip mounting surface of the dipad 3A is lowered in the plate thickness direction from the upper surface (bonding surface) of the inner part 3C1 of the lead 3C.
- the structure as shown in the first 3 Figure t is configured with a thickness dimension a of the semiconductor chip 2 is set to, for example, 0. 2 [mm].
- the thickness dimension B of the resin sealing body 1 is set to, for example, 0.5 [mm].
- the thickness B 1 of the resin on the main surface of the semiconductor chip 2 is set to, for example, 0.15 [mm]
- the thickness of the resin on the back surface of the semiconductor chip 2 is set.
- the dimension B2 is set to, for example, 0.15 [mm].
- the thickness C of the die pad 3A is set to, for example, 0.11 [mm].
- the height D of the resin-sealed semiconductor device is set to, for example, 0.6 to 0.7 [mm].
- the resin-encapsulated semiconductor device thus configured is formed by a manufacturing process using a lead frame 3 shown in FIG.
- a method for manufacturing the resin-encapsulated semiconductor device will be described. First, a lead frame 3 shown in FIG. 14 is prepared.
- an adhesive 4 is applied to the chip mounting surface of the die pad 3A of the lead frame 3 by a multi-point coating method.
- the semiconductor chip 2 is mounted on the chip mounting surface of the die pad 3A with the adhesive 4 interposed therebetween.
- the semiconductor chip 2 is bonded and fixed to the chip mounting surface of the die pad 3A via the adhesive 4.
- the external terminals 2 A of the semiconductor chip 2 and the inner portions 3 C 1 of the leads 3 C of the lead frame 3 are electrically connected by bonding wires 5.
- the lead frame 3 was placed between the upper mold 10 A and the lower mold 10 B of the mold 10, and Inside the cavity 11 formed by the upper mold 10 A and the lower mold 10 B of the mold 10, the semiconductor chip 2, the die pad 3 A, the support lead 3 B, and the inner part of the lead 3 C 3 C 1
- the center area of the back surface of the die pad 3A is brought into contact with the tip surface of the ejector pin 13 and the ejector pin 13 supports the center area of the back surface of the die pad 3A.
- the back surface of the die pad 3A is pressed against the tip surface of the ejector pin 13 by the elastic force of the holding lead 3B.
- the inflow gate 12 of the mold 10 is configured to fill the cavity 11 with resin through the upper and lower surfaces of the lead frame 3.
- the ejector pins 13 are for removing the resin sealing body 1 from the cavity 11 after forming the resin sealing mold 1.
- resin is injected under pressure into the cavity 11 from the pot of the mold 10 through the runner and the inflow gate 12, and the resin is sealed while supporting the back surface of the die pad 3 A with the ejector pins 13.
- the back surface of the die pad 3A is supported by the inner wall surface 11A of the cavity 11, so that the die pad 3A is pressurized and injected into the cavity 11 of the molding die 10.
- the upward / downward fluctuation of the die pad 3A caused by the flow of the resin is suppressed.
- the central area of the rear surface of the die pad 3A is in contact with the tip surface of the indicator pin 13, the central area of the rear surface of the die pad 3 A is from the lower surface which is one surface of the resin sealing body 1. Will be exposed.
- the center area of the rear surface of the die pad 3A is pressed by the elastic force of the support lead 3B against the distal end surface of the L-cut pin 13 so that the center area of the rear surface of the die pad 3A is No resin will flow into the area.
- the semiconductor chip 2, the die pad 3A, the support lead 3B, the inner part 3C1 of the lead 3C1, the bonding wire 5, etc. are sealed with the resin sealing body 1, and the die pad
- the central region of the back surface of 3A and the back surface of the lead portion 3B2 of the support lead 3B are exposed from the lower surface which is one surface of the resin sealing body 1.
- the support lead 3B and the lead 3C are cut from the frame 3E of the lead frame 3, and then the outer portion 3C2 of the lead 3C is formed into a gulling shape, thereby sealing the resin.
- the semiconductor device is almost completed.
- a semiconductor chip 2 a die pad 3A on which the semiconductor chip 2 is mounted, a support lead 3B holding the die pad 3A, and a resin sealing for sealing the semiconductor chip 2.
- a resin-sealed semiconductor having a body 1, wherein the die pad 3 A is formed with an outer dimension smaller than the outer dimension of the semiconductor chip 2, and wherein the resin-sealed body 1 is formed by a transfer molding method
- An apparatus wherein a central region of a back surface of the die pad 3A opposite to a chip tower surface is configured to be exposed from one surface of the resin sealing body 1, whereby the resin sealing body 1 is formed.
- the center area on the back surface of the die pad 3A can be supported by the ejector pins 13 of the mold 10 so that the mold 11 can be supported in the cavity 11 of the mold 10.
- the flow of resin injected under pressure It is possible to suppress the vertical variation of that Daipa' de 3 A.
- the thickness of the resin sealing body 1 is set to 1 [mm] or less, a problem in which the semiconductor chip 2 and the bonding wires 5 are exposed from the resin sealing body 1 can be prevented.
- the thickness of the stop semiconductor device can be reduced.
- the moisture intrusion path can be further lengthened.
- a method for manufacturing the device comprising the step of forming the resin sealing body 1 while supporting the back surface of the die pad 3A with the ejector pins 13 of the mold 10 to obtain the mold 10 Since the vertical fluctuation of the die pad caused by the flow of the resin injected under pressure into the cavity 1 can be suppressed, the flow of the resin on the main surface of the semiconductor chip 2 and the back surface of the semiconductor chip 2 can be suppressed. Good flow of resin It made. As a result, it is possible to prevent the occurrence of voids that occur in the resin-sealed body 1, thereby increasing the yield in the manufacturing process of the resin-sealed semiconductor device.
- a protrusion is provided on the inner wall surface 11A of the cavity 11 of the mold die 10, and the protrusion supports the central region of the back surface of the die pad 3A. May be.
- the semiconductor chip 2 is mounted on the chip tower of the die pad 3A.
- the semiconductor chip 2 has a structure mainly composed of, for example, a semiconductor substrate made of single crystal silicon and a wiring layer formed on the main surface thereof.
- the semiconductor chip 2 in this case has a thermal expansion coefficient of about 3 ⁇ 10 [1 / ° C1].
- the planar shape of the semiconductor chip 2 is, for example, 9 [mm] X 9 [mm] It is formed in a square shape having the external dimensions of.
- a plurality of external terminals (bonding pads) 2A arranged along each side of the main surface are arranged.
- each inner part 3 C 1 of the plurality of leads 3 is electrically connected to each of a plurality of external terminals 2 A arranged on the main surface of the semiconductor chip 2 via bonding wires 5. ing.
- Each of the four support leads 3B supports the die pad 3A on the lead frame in the state of the lead frame.
- Each of the four support leads 3B is arranged at a position where the X-shaped shape is formed.
- the semiconductor chip 2, the die pad 3A, the support lead 3B, the inner part 3C1 of the lead 3C1, the bonding wire 5, and the like are sealed with a resin sealing body 1 formed by a transfer molding method.
- the resin sealing body 1 is formed of, for example, a biphenyl-based resin or an ortho-cresol novolac-based resin to which a phenol-based curing agent, silicone, filler, and the like are added for the purpose of reducing stress.
- Resin sealing body 1 in this case has a 1 3 X 1 0- 6 [1 / in] about the thermal expansion coefficient.
- the planar shape of the resin sealing body 1 is, for example, a square shape having an outer dimension of 14 [mm] X 14 [mm].
- Outer sides 3C2 of the leads 3C are arranged outside each side of the resin sealing body 1.
- the respective outer portions 3C2 of the plurality of leads 3C are arranged along each side of the resin sealing body 1 and formed, for example, in a gull-wing shape.
- the planar shape of the die pad 3A is X-shaped. Dino. 'The source 3A is composed of four parts 3A1, and the width of each of the four parts 3A1 is set to, for example, 1 [mm].
- the die pad 3 A is formed with a plane area smaller than the plane area of the semiconductor chip 2.
- the resin-sealed semiconductor device of the present embodiment has a structure in which the entire region on the back surface of the die pad 3A is exposed from the lower surface of the resin-sealed body 1. Exposing the entire area of the back surface of the die pad 3A is to support the back surface of the die pad 3A with the inner wall surface of the mold mold cavity when the resin sealing body 1 is formed by the transfer molding method. Is achieved. As shown in FIG.
- the support lead 3B includes a lead portion 3B1 and a lead portion 3B2.
- the lead portion 3B1 is located at the same position as the inner part 3C1 of the lead 3C shown in FIG. 18 in the thickness direction, and the lead portion 3B2 is the die pad in the thickness direction. Is located in the same position as C3A. That is, in the resin-encapsulated semiconductor device of the present embodiment, the chip tower mounting surface of the die pad 3A is lowered in the plate thickness direction from the upper surface (bonding surface) of the inner part 3C1 of the lead 3C. It has a structured structure.
- the adhesive 4 is, for example, an epoxy silver (Ag) paste material. Is formed.
- the adhesive 4 is applied to the chip tower mounting surface of the die pad 3A by a multi-point application method.
- the diagonal region on the back surface of the semiconductor chip 1 is bonded and fixed with the adhesive 4 applied to the entire region of the chip pad mounting surface of the die pad 3A.
- the resin-encapsulated semiconductor device thus configured is formed by a manufacturing process using a lead frame 3 shown in FIG.
- the lead frame 3 is made of, for example, copper (Cu) having a thermal expansion coefficient of about 17 ⁇ 10, [1 / ° C].
- a resin-sealed semiconductor device in which the semiconductor chip 2 is mounted on the chip mounting surface of the X-shaped die pad 3 A and the semiconductor chip 2 is sealed with the resin sealing body 1.
- the semiconductor chip 2 is bonded and fixed with an adhesive 4 applied to the entire area of the chip mounting surface of the die pad 3A, so that the coefficient of thermal expansion between the die pad 3A and the semiconductor chip 2 is increased.
- X-shape made of copper (Cu) which has a large difference in thermal expansion coefficient from the semiconductor chip 2 because it can disperse the thermal stress caused by the difference in thermal expansion and prevent the semiconductor chip 2 from being damaged by the thermal stress.
- the semiconductor chip 2 can be mounted on the die pad 3A.
- the resin-sealed semiconductor device may be formed by a manufacturing process using the lead frame 3 shown in FIG. In this case, the same effect as that of the present embodiment can be obtained.
- the thickness of the resin-encapsulated semiconductor device can be reduced.
- the yield of the resin-encapsulated semiconductor device can be improved.
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Abstract
L'invention concerne un dispositif à semi-conducteur scellé par résine, comprenant une puce de semi-conducteur, une pastille de connexion sur laquelle est montée ladite puce, des conducteurs de support qui soutiennent ladite pastille de connexion, et un élément de résine qui scelle la puce de semi-conducteur. La pastille de connexion est plus petite que la puce de semi-conducteur, et l'élément de scellement en résine est formé selon un procédé de moulage par transfert. La surface intérieure de la pastille de connexion, qui se trouve sur le côté opposé à la surface de montage de la puce, fait face à la surface inférieure de l'élément de scellement en résine. Pour cette raison, lorsque l'élément de scellement en résine est formé selon un procédé de moulage par transfert, la surface inférieure de la pastille de connexion peut être supportée sur une surface intérieure d'une cavité d'un moule en métal ou d'une broche d'injecteur. Cela empêche le déplacement vertical de la pastille de connexion par le flux de résine injecté sous pression dans la cavité du moule métallique.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/JP1996/002418 WO1998009329A1 (fr) | 1996-08-29 | 1996-08-29 | Dispositif a semi-conducteur scelle par resine, et son procede de production |
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Application Number | Priority Date | Filing Date | Title |
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PCT/JP1996/002418 WO1998009329A1 (fr) | 1996-08-29 | 1996-08-29 | Dispositif a semi-conducteur scelle par resine, et son procede de production |
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WO1998009329A1 true WO1998009329A1 (fr) | 1998-03-05 |
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PCT/JP1996/002418 WO1998009329A1 (fr) | 1996-08-29 | 1996-08-29 | Dispositif a semi-conducteur scelle par resine, et son procede de production |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63204753A (ja) * | 1987-02-20 | 1988-08-24 | Nitto Electric Ind Co Ltd | 半導体装置 |
JPH03263359A (ja) * | 1990-03-13 | 1991-11-22 | Nec Corp | モールドフラットパッケージ |
JPH04184944A (ja) * | 1990-11-20 | 1992-07-01 | Citizen Watch Co Ltd | Icの樹脂封止方法 |
JPH0555410A (ja) * | 1991-08-28 | 1993-03-05 | Hitachi Ltd | 半導体装置 |
JPH0637209A (ja) * | 1992-07-14 | 1994-02-10 | Kyocera Corp | 半導体装置 |
JPH06209054A (ja) * | 1993-01-08 | 1994-07-26 | Mitsubishi Electric Corp | 半導体装置 |
JPH06268146A (ja) * | 1993-03-15 | 1994-09-22 | Toshiba Corp | 半導体装置 |
JPH0722451A (ja) * | 1993-07-07 | 1995-01-24 | Hitachi Ltd | 半導体製造装置 |
-
1996
- 1996-08-29 WO PCT/JP1996/002418 patent/WO1998009329A1/fr active Application Filing
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63204753A (ja) * | 1987-02-20 | 1988-08-24 | Nitto Electric Ind Co Ltd | 半導体装置 |
JPH03263359A (ja) * | 1990-03-13 | 1991-11-22 | Nec Corp | モールドフラットパッケージ |
JPH04184944A (ja) * | 1990-11-20 | 1992-07-01 | Citizen Watch Co Ltd | Icの樹脂封止方法 |
JPH0555410A (ja) * | 1991-08-28 | 1993-03-05 | Hitachi Ltd | 半導体装置 |
JPH0637209A (ja) * | 1992-07-14 | 1994-02-10 | Kyocera Corp | 半導体装置 |
JPH06209054A (ja) * | 1993-01-08 | 1994-07-26 | Mitsubishi Electric Corp | 半導体装置 |
JPH06268146A (ja) * | 1993-03-15 | 1994-09-22 | Toshiba Corp | 半導体装置 |
JPH0722451A (ja) * | 1993-07-07 | 1995-01-24 | Hitachi Ltd | 半導体製造装置 |
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