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WO1998010519A1 - Boucle de verrouillage de phase a faible gigue - Google Patents

Boucle de verrouillage de phase a faible gigue Download PDF

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Publication number
WO1998010519A1
WO1998010519A1 PCT/DE1997/001908 DE9701908W WO9810519A1 WO 1998010519 A1 WO1998010519 A1 WO 1998010519A1 DE 9701908 W DE9701908 W DE 9701908W WO 9810519 A1 WO9810519 A1 WO 9810519A1
Authority
WO
WIPO (PCT)
Prior art keywords
oscillator
phase
frequency
controller
controlled
Prior art date
Application number
PCT/DE1997/001908
Other languages
German (de)
English (en)
Inventor
Volkmar Rebmann
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1998010519A1 publication Critical patent/WO1998010519A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0997—Controlling the number of delay elements connected in series in the ring oscillator

Definitions

  • the invention relates to a phase-locked loop according to the features of the preamble of patent claim 1.
  • Phase locked loops are used to generate an output signal that is phase locked to a reference frequency signal.
  • the basic structure of phase-locked loops is described, for example, in the reference Tietze, Schenk, “Semiconductor circuit technology”, 9th edition, 1991, pages 954 to 967.
  • the controller implemented there is designed as a PI controller, in particular as an RC
  • the charge pump delivers pulses of positive or negative current pulses depending on the comparison result of the phase detector
  • the proportional part which ensures the stability of the overall system
  • the pulsed activation of the loop filter from the charge pump, together with the proportional control part means that the output signal of the loop filter has corresponding control impulses by means of which the controllable n oscillator output vibration is corrected in frequency. These control pulses generate frequency and phase interference in the output signal of the oscillator, so-called frequency and phase jitter.
  • the control pulses and the phase jitter generated thereby are also present in the steady state, since the oscillation frequency of the controlled oscillator changes due to supply voltage fluctuations and leak effects, for example in the capacitor of the loop filter. If the phase locked loop is operated as a frequency multiplier with a Divider in the feedback circuit, the oscillator oscillates freely during the number of oscillations set by the divider ratio. The frequency and phase deviation of the oscillator accumulates during this free-running time, the adjustment effect due to the control pulses is correspondingly large.
  • Oscillators are usually implemented as integrated circuits.
  • the transmission characteristics of the transistors are subject to the so-called 1 / f noise, which is caused by the unavoidable defects in the atomic lattice of the semiconductor crystal.
  • the 1 / noise is considerable in particular in the case of implementations with CMOS transistors. It is effective up to orders of magnitude close to the desired control accuracy of the phase locked loop. Especially in the
  • Video technology requires phase locked loops that oscillate at around 100 MHz.
  • the 1 / f noise then extends into the range of 1 MHz, so that the required tuning accuracy of the control loop, which is in the range of kHz, can no longer be achieved.
  • the effect of the phase and frequency jitter on the one hand and the effect of the 1 / f noise on the other hand is dependent on the loop gain of the phase locked loop.
  • the loop gain through which the control bandwidth is determined, is proportional to the proportional portion of the loop filter.
  • a high loop gain is necessary.
  • the jitter effects are also proportional to the loop gain.
  • the l / f noise effects are inversely proportional to the loop gain. Consequently, changing the loop gain reduces one of the effects but increases the other.
  • the object of the invention is to provide a phase locked loop which enables an output signal with as little jitter as possible at high operating frequencies.
  • the phase locked loop should be realizable as an integrated circuit in CMOS circuit technology.
  • the invention is based on the principle of suppressing the control pulses when the oscillator supplying the output signal is activated effectively. This oscillator is therefore only controlled with the integral part of the controller.
  • measures are proposed in order to obtain the highest possible amplification and a correspondingly high bandwidth of the control range of the phase-locked loop without increasing the phase jitter.
  • the phase-locked loop has an unchanged good stability behavior.
  • the oscillator located in the feedback branch is designed as a ring oscillator with a variable feedback length that is shortened or lengthened by the control pulses. This gives the control loop a sufficiently high control gain. Due to component fluctuations and the 1 / f current noise, the frequencies of the output signals of the two oscillators may differ. Readjustment is therefore provided, by means of which the frequency difference between the two oscillators is corrected.
  • a further I or PI controller is provided, which is connected on the input side to the outputs of the two oscillators.
  • the phase difference between the oscillators, which is generated by shortening or lengthening the ring oscillator due to the control by the proportional control component, is determined by a delay element. maintained despite the frequency readjustment between the two oscillators.
  • Figure 1 shows an embodiment of a phase locked loop
  • Figure 2 shows an implementation for the oscillator in the feedback branch.
  • the phase-locked loop according to FIG. 1 contains an input connection 1, to which a reference signal VI with a reference frequency is fed.
  • a phase detector 2 the phase difference is determined between the reference signal VI and a feedback signal VF to be explained later.
  • the phase detector 2 Depending on the phase difference, the phase detector 2 generates pulse-like output signals PU, PD.
  • a pulse PU is generated when the feedback signal VF lags the reference signal VI.
  • a corresponding correction of the signal VF is initiated by the pulse PU. Otherwise, when the feedback signal VF leads the reference signal VI, the pulse PD is generated and the signal VF is corrected accordingly.
  • An integral controller is formed by a charge pump 3 and an integrator connected downstream of it on the output side.
  • the latter is a capacitor 4, which is charged or discharged by current pulses from the charge pump.
  • the capacitor 4 In the case of a pulse PU, the capacitor 4 is charged by a current pulse + Ip, in the case of a pulse PD the capacitor 4 is discharged by a current pulse -Ip.
  • the control signal VC which can be tapped at the connection 5 of the capacitor has an integral character with respect to the phase difference between the signals VI, VF.
  • a voltage-controlled oscillator (VCO) 61 is controlled with respect to its oscillation frequency by the control signal VC at the connection 5, and with respect to its phase by the pulses PD, PU.
  • At the output 7 of the oscillator 61 there is a signal whose frequency is synchronized with the frequency of the input signal VI in the steady state. If the circuit is used as a frequency is operated multiple times, there is a divider 9 in the feedback path, by means of whose divider ratio 1: N the multiplication ratio N is set.
  • the oscillator 61 consists of a runtime chain 80 made up of delay elements connected in series, for example inverters, the output of which is fed back to the input.
  • the runtime chain is supplied with a controllable current source 81 for control via the connection 5 with the signal VC.
  • the length of the delay chain can be shortened or lengthened compared to the middle tap 83 by means of corresponding switches 82 or 84.
  • the output signal of the oscillator 61 is shifted by a negative or a positive time period with respect to a central position of a clock edge of its output signal.
  • the switches 82, 84 are controlled by the proportional control signals PU and PD, the switch 85 is controlled when none of the signals PU, PD has a pulse. During the pulse pause of the signals PU, PD, the switch 85 is closed and the mean feedback length is set. This results in phase jumps dependent on the pulse duration in the output signal of the oscillator 61.
  • the special design of the oscillator 61 shown in FIG. 4 responds very quickly to the control pulses, so that the control loop formed has a high loop gain for a large capture range of the oscillator.
  • a further oscillator 62 is also provided, which is also controlled by the integral signal VC.
  • the oscillator 62 has a corresponding one in comparison to the oscillator 61
  • oscillator 62 Since the oscillators 61, 62 are controlled by the same signal VC, they oscillate at essentially the same frequency. Compared to oscillator 61, however, oscillator 62 has no phase jitter, since it is only controlled by the integral component, but not by the proportional component of the control loop becomes. The output signal VO is therefore present at the output of the oscillator 62 as a low-jitter signal.
  • a further phase detector and charge pump device 63 is therefore provided with an element 64 which generates an I component, by means of which the oscillator 61 is adjusted.
  • the oscillator 62 can also be adjusted.
  • a delay element 65 is provided, via which the output signal of the oscillator 61 is coupled into one of the phase detector inputs of the device 63.
  • the delay time of the timing element 65 can preferably be set by the device 63 via an integral element 66.
  • the output signal VO is fed into the other phase detector input of the device 63 either directly or via another - not shown - adjustable delay element.
  • the switch 67 is expediently switched on during a first half of the period of the feedback signal VF generated by the divider factor N in the divider 9, and the switch 68 during the second period.
  • the delay element 65 is designed in accordance with the ring oscillator 61 with a controllable current source which supplies the inverter chain , but without feedback.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Dans une boucle de verrouillage de phase, pour éviter la gigue de phase, est monté un oscillateur (62) commandé en fréquence, conditionnant le signal de sortie (VO), qui n'est mis en marche uniquement par la composante intégrale (4) d'un régulateur PI. Un oscillateur (61) placé dans la branche de rétroaction de la boucle de régulation est mise en marche par la composante intégrale et proportionnelle (4, PU, PD) de la boucle de régulation. Dans le mode de réalisation selon l'invention, cet oscillateur (61) est réalisé sous la forme d'un oscillateur annulaire dont la longueur de rétroaction peut être modifiée par la composante proportionnelle (PU, PD). Entre les oscillateurs (61, 62) un système de correction de fréquence (63...68) sert à la synchronisation de fréquence. Cette boucle de verrouillage de phase présente une largeur de bande élevée avec une grande exactitude de fréquence et peut être réalisée également pour des fréquences de travail élevées, dans la technologie CMOS.
PCT/DE1997/001908 1996-09-04 1997-09-01 Boucle de verrouillage de phase a faible gigue WO1998010519A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19635897 1996-09-04
DE19635897.3 1996-09-04

Publications (1)

Publication Number Publication Date
WO1998010519A1 true WO1998010519A1 (fr) 1998-03-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1997/001908 WO1998010519A1 (fr) 1996-09-04 1997-09-01 Boucle de verrouillage de phase a faible gigue

Country Status (1)

Country Link
WO (1) WO1998010519A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000018008A3 (fr) * 1998-09-17 2000-05-25 Siemens Ag Circuit pour la recuperation d'un signal de donnees et la regeneration d'un signal d'horloge

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1531632A (en) * 1976-05-28 1978-11-08 Westinghouse Brake & Signal Phase-locked loop arrangements
EP0342626A2 (fr) * 1988-05-17 1989-11-23 Kabushiki Kaisha Toshiba Circuit oscillateur commandé par tension
US5241700A (en) * 1990-05-07 1993-08-31 Dassault Electronique Receiver of an electromagnetic signal with a known nominal frequency, liable to be affected by an unknown variation, in particular by the doppler shift
EP0654907A1 (fr) * 1993-11-23 1995-05-24 Matra Mhs Circuit de récupération d'horloge à oscillateurs appariés
US5491439A (en) * 1994-08-31 1996-02-13 International Business Machines Corporation Method and apparatus for reducing jitter in a phase locked loop circuit
JPH08186490A (ja) * 1994-11-04 1996-07-16 Fujitsu Ltd 位相同期回路及びデータ再生装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1531632A (en) * 1976-05-28 1978-11-08 Westinghouse Brake & Signal Phase-locked loop arrangements
EP0342626A2 (fr) * 1988-05-17 1989-11-23 Kabushiki Kaisha Toshiba Circuit oscillateur commandé par tension
US5241700A (en) * 1990-05-07 1993-08-31 Dassault Electronique Receiver of an electromagnetic signal with a known nominal frequency, liable to be affected by an unknown variation, in particular by the doppler shift
EP0654907A1 (fr) * 1993-11-23 1995-05-24 Matra Mhs Circuit de récupération d'horloge à oscillateurs appariés
US5491439A (en) * 1994-08-31 1996-02-13 International Business Machines Corporation Method and apparatus for reducing jitter in a phase locked loop circuit
JPH08186490A (ja) * 1994-11-04 1996-07-16 Fujitsu Ltd 位相同期回路及びデータ再生装置
US5657359A (en) * 1994-11-04 1997-08-12 Fujitsu, Limited Phase synchronizer and data reproducing apparatus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 096, no. 011 29 November 1996 (1996-11-29) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000018008A3 (fr) * 1998-09-17 2000-05-25 Siemens Ag Circuit pour la recuperation d'un signal de donnees et la regeneration d'un signal d'horloge
US6433599B2 (en) 1998-09-17 2002-08-13 Infineon Technologies Ag Circuit for data signal recovery and clock signal regeneration

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