WO1998018257A1

WO1998018257A1 - Ccd camera device

Info

Publication number: WO1998018257A1
Application number: PCT/JP1996/003041
Authority: WO
Inventors: Satoshi Takase; Takashi Takahashi; Tomoki Osada; Teruaki Odaka; Hiroaki Takagishi
Original assignee: Hitachi, Ltd.; Hitachi Microcomputer System Ltd.; Hitachi Device Engineering, Co., Ltd.
Priority date: 1996-10-21
Filing date: 1996-10-21
Publication date: 1998-04-30

Abstract

A CCD camera, in which video signals are obtained by operating a CCD image pickup element having about 270,000 picture elements at a horizontal scanning frequency of 9 MHz, and the video signals are converted to digital signals for signal processing in a video signal processor, paired pixel signals from which are combined with a false pixel signal derived from their average. The resulting 3-pixel signals are synchronized with clock pulses at 13.5 MHz to obtain luminance signals and color difference signals conformable to Rec 601, ITU-R standard.

Description

Details

CCD camera device technical field

The present invention relates to a CCD (Charge Transfer Device) camera device, and particularly to a video signal suitable for a digital video signal compliant with the ITU-RRec601 standard using a 270,000-pixel CCD image sensor compliant with the NTSC system. The present invention relates to technology that is effective when used in a CCD camera device that forms an image. Background art

A wide variety of functions have been developed for CCD imaging devices such as video cameras due to the spread of digital signal processing, but since they can output digital video signals, image input devices such as personal computers and videophones It is also applied to conference systems. Against this background, a 270,000-pixel color CCD image sensor, which is generally inexpensively distributed as a CCD image sensor for video cameras, is used as an object by utilizing its electronic zoom processing. An imaging device has been proposed which has a ratio equal to that of the NTSC system and forms a digital signal applicable to a computer system. JP-A-6-334926 discloses an example of such an imaging device.

In the ITU-R Rec 601 standard, the sampling frequency is 13.5 MHz. The digital video signal output from the NTSC video camera is 14.3 MHz. For this reason, when the digital signal formed by the NTSC system is simply input to a computer, that is, as shown in (A) of FIG. When the pixel signal formed in the area is output at 14.3 MHz in conformity with the NTSC system and is input directly to a personal computer, there is no information on the screen as shown in (B) of the figure. The part is displayed, and the aspect ratio of the screen (aspect ratio) shifts. Therefore, according to the above publication, the aspect ratio (aspect ratio) is adjusted by using an electronic zoom system in order to display the entire screen at the same aspect ratio as shown in FIG. ), There is a problem that the circuit scale for performing such correction increases, the system configuration becomes complicated, and the cost is inevitable.

Accordingly, the present invention provides a CCD camera device which uses a CCD solid-state image sensor of 27,000 pixels for a video camera, and is realized by a simple configuration to be used for an image input device such as a personal computer. It is an object. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

According to the present invention, a CCD image sensor of about 270,000 pixels is operated with a 9 MHz horizontal scanning pulse to obtain a video signal, and the video signal is converted into a digital signal to be processed by a video signal processing circuit. At the same time, a pair of pixel signals output from the signal processing circuit are used, and converted into three pixels including a pseudo pixel signal composed of the average value, and synchronized with a 13.5 MHz clock pulse. Then, a luminance signal and a color difference signal conforming to the ITU-RRec601 standard are obtained. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic block diagram showing an embodiment of a CCD camera device according to the present invention. It is a lip chart,

FIG. 2 is a connection diagram between the CCD camera device according to the present invention and a personal convenience store,

FIG. 3 is an output waveform diagram of a CCD image sensor for explaining the present invention;

FIG. 4 is a timing chart for explaining the pixel interpolation processing according to the present invention;

FIG. 5 is a timing chart of a read operation of the CCD image sensor for explaining the present invention;

FIG. 6 is a block diagram showing an embodiment of a video signal processing LSI used in the present invention.

FIG. 7 is a block diagram showing an application example of the CCD camera device according to the present invention.

FIG. 8 is a display screen diagram of a personal computer for explaining the premise of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of an embodiment of a CCD camera device according to the present invention. In the figure, 1 is a lens mechanism, 2 is a CCD image sensor, 3 is an analog / digital (hereinafter referred to as AZD) conversion circuit, and 4 is a video signal processing LSI (large-scale semiconductor integrated circuit). Although not particularly limited, the video signal processing LSI includes the following circuit blocks. 5 is a video signal processing block, 6 is a signal change block, 7 is a CCD drive circuit, 8 is a frequency divider circuit, and 9 is a clock. It is a pulse generation circuit. Reference numeral 10 denotes a crystal oscillator used in an oscillation circuit that generates a reference signal included in the clock generation circuit.

The lens mechanism includes an aperture and a focusing mechanism in addition to a lens, and a shutter mechanism for a still camera. For the above-mentioned aperture adjustment and focusing, a motor and its driving circuit and control circuit are also included.

The CCD image sensor 2 is composed of a power CCD image sensor of about 270,000 pixels. Although the pixel configuration is not particularly limited, 512 pixels are provided in the horizontal direction and 494 pixels are provided in the vertical direction, and a total of about 270,000 pixels are formed in a matrix. The CCD image sensor 2 employs a well-known in-line transfer method, in which photoelectric conversion charges formed by photodiodes constituting about 27,000 pixels are simultaneously read out to a vertical CCD, and The electric charge read out to the vertical CCD is transferred to the horizontal CCD for one horizontal scan, and a pixel signal for one line is output from the horizontal CCD in synchronization with the horizontal scan clock by an amplifier provided in the output unit. It is converted to a signal and output. When the charge transfer of one line is completed as described above, the transfer operation for one pixel is performed in the vertical CCD, and the signal charge of the next line is transferred to the horizontal CCD. Thereafter, the photoelectric conversion charges are sequentially read out in the same manner as described above. During the reading of the signal charge, the photodiode generates the signal charge to be read next.

Although not particularly limited, the signal charge of the photodiode has a function of being swept out to the substrate side, and by appropriately performing such a reset operation, adjustment of the photoelectric conversion time of the photodiode, in other words, exposure Time adjustment (electronic iris) is enabled.

The pixel signal read from the CCD image sensor 2 is converted into a digital signal by the A / D conversion circuit 3. This AZD conversion circuit 3 The generated digital signal is input to a video signal processing block included in the video signal processing LSI.

In this embodiment, the CCD image sensor reads out the pixel signals by a 9 MHz horizontal scanning clock signal. In other words, although the CCD image sensor 2 is designed in conformity with the NTSC or PAL system, it is suitable for a horizontal interface that is compatible with an interface for computer input as described later. It is operated by a clock signal. For example, a low frequency such as the above 9 MHz is used irrespective of the CCD image sensor based on the NTSC system in which the frequency f 0 of the horizontal scanning pulse is about 9.5 MHz.

There is an ITU-R Rec 601 standard as an interface for computers, and the sampling frequency in such a standard is 13.5 MHz. This 13.5 MHz frequency is not found in the NTSC and PAL systems. The frequency at 13.5 MHz is 858 times the number of 525 scanning lines in the NTSC system and 864 times the horizontal frequency of 625 scanning lines in the PAL system.In both cases, the frequency is an integer multiple of the horizontal frequency. Can be used. This has the advantage that a common design is possible because the horizontal effective period can be set to the same value for 720 samples in both types.

In the present invention, in order to simplify adaptation to the above interface, the horizontal clock frequency is used even though the CCD image pickup device used conforms to the NTSC system (or PAL system). Is set to 9 MHz. Then, the signal is converted to 13.5 MHz by the signal conversion circuit and output. For this reason, the clock generating circuit 9 forms a 27 Mz reference frequency signal, and forms a 9 MHz horizontal clock pulse using the frequency dividing circuit included in the CCD driving circuit 7. In the CCD drive circuit, Vertical pulse, transfer gate pulse based on horizontal clock pulse

In addition, various clock pulses necessary for reading pixel signals from the CCD image sensor 2 are generated as reset pulses.

The pixel signal read as described above is input to the AZD conversion circuit 3 and digitized as a signal having a sampling frequency of 9 MHz and a quantization bit number of 9 bits or 10 bits. . The pixel signal digitized by the A / D conversion circuit 3 is input to a video signal processing block 5 included in a video signal processing LSI 4, where the luminance signal is subjected to processing such as gamma, enhancer, and color processing. The signal undergoes RGB matrix, gamma and color difference conversion processing. The digital signal processed by the video signal processing block 5 has a sampling frequency of 9 MHz according to the read signal from the CCD image sensor 2 described above.

The signal conversion circuit 6 converts the signal into a 13.5 MHz digital signal by a clock signal supplied from the frequency dividing circuit 8 so as to conform to the above-mentioned interface for a computer. That is, the frequency dividing circuit 8 divides the 27 MHz reference frequency signal formed by the clock generating circuit 9 into two to form the above 13.5 MHz clock pulse, and Transmit to conversion circuit 6. The signal conversion circuit 6 generates a pseudo-pixel signal having an average value (A + B) Z 2 from a pair of continuous pixels A and B using the above-described clock signal. A pseudo pixel signal is added to one pixel to convert it into three pixels, which are output in synchronization with the above 13.5 MHz clock signal. In this case, the ratio of the luminance signal Y, the color difference signals R-Υ, and Β-Υ is set to 4: 2: 2 so as to conform to the above-mentioned in-plane connection and output.

FIG. 2 is a connection diagram of the CCD camera device according to the present invention and a personal computer. In the embodiment of FIG. It is connected to a dedicated connector via evening and cable. In this case, the user can freely shoot the CCD camera device at the subject and capture the image. In the embodiment shown in FIG. 1B, a CCD camera device is integrally mounted on the upper part of the display device of the personal convenience display. In this configuration, the image capturing function is added as a function of the personal computer, and it is suitable for videophone use via a personal computer network.

The image data captured by the above CCD camera device can be processed and stored in a personal computer in the same way as character data and graphic data, and can be processed remotely via a communication device such as a modem. Data transfer to the ground can be realized.

FIG. 4 shows an output waveform diagram of a CCD image sensor for explaining the present invention. The frequency of the horizontal scanning pulse of the CCD image sensor based on the NTSC system is 9.5 MHz as described above. In other words, the CCD solid-state imaging device formed in accordance with the NTSC system is designed so that all pixels can be read at the above 9.5 MHz, as shown in FIG. When such a CCD solid-state imaging device is driven at a lower frequency than the above design value such as 9 MHz in the present invention as described above, as shown in FIG. Pixels that cannot be read remain. For this reason, in the CCD camera device of the present invention, in the effective pixel area of the image sensor as shown in FIG. 8A, the unread portion is invalidated.

In the CCD image sensor, if signal charges are read out by the horizontal scanning clock signal only in the display period in the one horizontal scanning period, the unread charges will be read out at the next scanning start. May cause malfunction. Therefore, in FIG. During the horizontal retrace period of the level, the above-mentioned unread signal charges are swept out. For this reason, although not particularly limited, the horizontal scanning clock supplied to the CCD image sensor is changed from the above 9 MHz to a reference frequency signal of 27 MHz so that the signal can be swept out at high speed. .

This is because the unread charges also exist in the vertical CCD, and the vertical scan pulse supplied to the vertical CCD is converted to the horizontal scan pulse and the reference frequency signal using the vertical blanking period. By switching, the signal charge is swept out at high speed, and the output from the first pixel of the first line is output from the beginning of the next field.

As described above, in the driving method according to the present invention, the entire effective pixel area of the CCD image pickup device is not output, but only the pixel signal read by the above-mentioned self is displayed on one screen of the monitor, and the position of the subject is determined by such a display screen. To choose It is not particularly problematic in actual view.

FIG. 4 is a timing chart for explaining the pixel interpolation processing according to the present invention. When using a CCD solid-state image sensor with approximately 27,000 pixels in accordance with the NTSC system and reading it with a 9 MHz horizontal scanning pulse as described above, the processing time per pixel is 1 Since it is 11 ns (nanosecond), the processing time of two adjacent pixels, that is, pixel A and pixel B, is 222 ns. On the other hand, when the sampling frequency of the interface is 13.5 MHz, the processing time per pixel is 74 ns. In other words, the processing time for two pixels read at 9 MHz is equal to the processing time for three pixels at 13.5 MHz.

In the present invention, the signal conversion is performed in the signal conversion circuit. In other words, take in two pixels, convert them to three pixels, and output them serially with three pixels within the processing time of the two pixels. Things.

That is, as shown in FIG. 4, while pixel A and pixel B are fetched and pixel A is being output, the above fetched pixel A and pixel B are added, the result is set to 12 and the average value is calculated. The pseudo pixel (A + B) Z 2 is output subsequently to the pixel A, and finally the pixel B is output. The output time of each of the three pixels A— (A + B) 2 −B is set to 74 ns as described above. That is, the pixel signal read at 9 MHz from the CCD image sensor is converted to a 13.5 MHz pixel signal and output. However, for the above-described signal conversion, a time of 222 ns for capturing two pixels is required, and the timing at which the pixel signal is output is delayed by this amount. Therefore, to compensate for such a delay in the timing, the timing of the horizontal synchronizing pulse is also delayed by the above time and output. Thereby, it is possible to prevent the display screen from being shifted on the screen by the signal conversion processing.

FIG. 5 shows a timing diagram of a read operation of the CCD image sensor for explaining the present invention. As described above, the 270000-pixel CCD solid-state imaging device is designed so that reading is performed at 9.5 (9.53496) MHz. In other words, optical black is read out on the basis of the horizontal synchronization pulse as shown in (A) of the figure, the pixel signal from the effective pixel is read out, and finally the dummy bit and the optical bit are read out. It is designed so that the cull black is read and the horizontal period is set. If this is driven by the horizontal scanning pulse of 9 MHz as described above, as shown in Fig. 13 (B), the cycle of one clock pulse will be changed as the frequency is lowered as it is, as it is, as it is in the same setting. Since the length becomes longer, the position of the optical black that defines the black level becomes slower with respect to the horizontal synchronization signal. The signal transfer time of one pixel also becomes longer as described above, Considering the insertion of dots and optical black, the transfer time of the above horizontal CCD is shortened, and the readout time of the effective pixel signal is reduced. Therefore, although not particularly limited, the time from the horizontal synchronization pulse to the start of the optical black readout for the CCD drive circuit 7 in FIG. 1 described above becomes a number matching the above 9 MHz horizontal pulse. Set as follows. As a result, as indicated by the arrow in FIG. 11B, the reading of optical black is started at the same position as in the case of FIG.

FIG. 6 is a block diagram showing an embodiment of a video signal processing LSI used in the present invention. The analog pixel signal output from the CCD solid-state imaging device is A / D converted as described above and input as a digital signal. This digital signal is subjected to AGC processing in a digital AGC circuit 11.

After the AGC processing as described above, the color signal system is input to the RGB matrix 12, where the matrix operation is performed, and the white balance detection circuit 13 is used to auto-white the faithful reproduction of white. Detects data for control of the balance, outputs the data from the terminal T2, and takes it into an externally provided controller to control the auto white balance. The luminance signal system is subjected to enhancer processing by an enhancer 15 via a filter 14, and is subjected to 7 correction processing by a gamma processing circuit 16.

The timing generation circuit 19 forms various timing signals supplied to the CCD image sensor as described above and a timing signal supplied to the A / D conversion circuit. Then, the reference signal is frequency-divided and supplied to the signal conversion circuit shown as a clock conversion circuit 17. The clock conversion circuit 17 outputs, for example, the above two pixels for each of the color signal and the luminance signal. (Register or flip-flop) that captures the data, an arithmetic circuit that forms a pseudo pixel signal of the average value of two pixels, and a simple circuit such as a shift register that synchronizes with the above 13.5 MHz and outputs it. . The arithmetic circuit can obtain a 1/2 arithmetic result by, for example, shifting the output digital signal of the adder circuit right by one bit (down by one digit) and holding the result in a register or the like. For this reason, the clock conversion circuit 17 as the above-mentioned signal conversion circuit can realize the above-mentioned signal conversion processing with a simple circuit composed of a register and an addition circuit. For example, a partial design of an existing video signal processing LSI can be realized. You just need to change it. The encoder 18 makes the luminance signal and the color difference signal have a ratio of 4: 2: 2.

FIG. 7 is a block diagram showing an application example of the CCD camera device according to the present invention. This embodiment is directed to a digital still camera system using an IC card. The digital still camera system consists of an optical system, a central processing unit CPU, a motor drive circuit, an aperture, a shutter, an image sensor, a signal processing circuit, and an AZD conversion circuit. The subject is received by the optical system, the aperture and the shutter are controlled by a motor drive circuit controlled by the central processing unit CPU, and the subject is imaged on the image sensor via the aperture and the shirt. You. An image signal formed by the image sensor is read out, input to an analog / digital conversion circuit A / DC, and taken into a signal processing / conversion circuit as a digital signal. The digital signal is input to a signal processing circuit controlled by the central processing unit CPU or the like, and the above-described video signal processing and signal conversion processing are performed. The signal thus formed is stored in, but not limited to, an IC chip with a built-in aperture electric RAM. By applying the IC card with a built-in ferroelectric RAM of the present invention to a digital 'still' camera, The digital, still, camera, and system can be made smaller, lighter, thinner, consume less power, and can read and write large amounts of information at high speed, improving the processing capacity of the entire system. Then, when reading it out and inputting it to a computer, the signal is compliant with ITU-R Rec 601, as described above, so it is only necessary to read it out at 13.5 MHz above. Becomes

The operational effects obtained from the above embodiment are as follows.

(1) A CCD image sensor of about 270,000 pixels is operated with a 9 MHz horizontal scanning pulse to obtain a video signal, and the video signal is converted into a digital signal and processed by a video signal processing circuit. Synchronized to a 13.5 MHz clock pulse by a circuit with a simple configuration that uses a pair of pixel signals output from the signal processing circuit and converts it to 3 pixels including a pseudo pixel signal consisting of the average value This makes it possible to obtain a luminance signal and a chrominance signal conforming to the ITU-R Rec 601 standard.

(2) Using a 27 MHz reference frequency and dividing it by 3 and dividing it by 2 with a very simple configuration, the above 9 MHz horizontal scanning pulse is divided by 2 and the above 13. The effect is obtained that a sampling frequency of 5 MHz can be obtained.

(3) The pseudo pixel signal formed by the signal conversion circuit is inserted between the pair of continuously output pixel signals and output, thereby performing frequency conversion of the pixel signal. The effect of being able to obtain a video signal closer to the original image by signal interpolation is obtained.

(4) By using the video signal processing circuit for a video camera as it is as the video signal processing circuit, it is possible to obtain an effect that only the signal conversion needs to be added. Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, the reference frequency signal is an integer multiple of 13.5 MHz (N times), which is divided into 1ZN to form the above 13.5 MHz sampling pulse, which is divided into 2 / 3N. To form the above 9 MHz horizontal scanning pulse. When the display device of the personal computer is not a CRT display device but a flat display such as a TFT, a function to omit the は correction function in the video signal processing circuit is added. You can do it. Industrial applicability

As described above, the present invention can be widely used in various CCD camera devices directed to personal computers, videophone systems, and the like, using a CCD image sensor having about 270,000 pixels.

Claims

The scope of the claims

1. A CCD image sensor of about 270,000 pixels is operated by a 9 MHz horizontal scanning pulse to obtain a video signal, and the video signal is converted into a digital signal, and the video signal is processed by a video signal processing circuit. Using a pair of pixel signals output from the signal processing circuit, convert to 3 pixels including pseudo pixel signals and synchronize with 13.5 MHz clock pulse to comply with ITU-R Rec 601 standard A CCD camera device for obtaining a luminance signal and a color difference signal.

2. Generate a reference clock signal having a frequency of 13.5 MHz or an integer multiple thereof, and form a first clock pulse of 9 MHz and a second clock pulse of 13.5 MHz based on the reference clock signal. Clock generation circuit

A CCD image sensor of approximately 270,000 pixels that receives the 9 MHz first clock pulse and outputs an image signal in synchronization with the first clock pulse;

An AZD conversion circuit that receives an image signal read from the CCD image sensor and converts it into a digitized signal;

A video signal processing circuit for receiving the image signal formed by the A / D conversion circuit,

A function of converting a pair of pixel signals continuously output from the video signal processing circuit into three pixels including a pseudo pixel signal composed of an average value thereof and synchronizing with the second clock pulse. A CCD camera device, comprising: a signal conversion circuit.

3. The frequency of the reference clock signal is set to 27 MHz. The first clock pulse is converted to 9 MHz by dividing the reference clock signal by 3, and the second clock pulse is converted to 9 MHz. Is the above reference clock 3. The CCD camera device according to claim 2, wherein the frequency is divided by 2 and converted to 13.5 MHz.

4. The pseudo pixel signal formed by the signal conversion circuit is inserted between the pair of continuously output pixel signals and output. The described CCD camera device.

5. The above video signal processing circuit uses the video signal processing circuit for video camera as it is, and provides gamma correction and enhancer processing functions for luminance signals, and RGB matrix, gamma correction and color difference conversion processing functions for color signals. 3. The CCD force camera device according to claim 2, wherein the CCD force camera device includes:

6. The video signal processing circuit uses the video signal processing circuit for the video camera as it is, and provides gamma correction and enhancer processing functions for luminance signals, and RGB matrix, gamma correction and color difference conversion processing functions for color signals. 4. The CCD force camera device according to claim 3, wherein the CCD force camera device includes:

7. The CCD camera device according to claim 2, wherein the signal conversion circuit outputs a luminance signal and a color difference signal in accordance with the ITU-RRec601 standard. .