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WO1998032175A1 - Dispositif semi-conducteur a metallisation et couche barriere comportant au moins du titane, du tungstene ou de l'azote et son procede de fabrication - Google Patents

Dispositif semi-conducteur a metallisation et couche barriere comportant au moins du titane, du tungstene ou de l'azote et son procede de fabrication Download PDF

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Publication number
WO1998032175A1
WO1998032175A1 PCT/IB1998/000030 IB9800030W WO9832175A1 WO 1998032175 A1 WO1998032175 A1 WO 1998032175A1 IB 9800030 W IB9800030 W IB 9800030W WO 9832175 A1 WO9832175 A1 WO 9832175A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
aluminum
silicon oxide
metallization
silicon
Prior art date
Application number
PCT/IB1998/000030
Other languages
English (en)
Inventor
Henricus G. F. Maas
Ronald Dekker
Wilhelmus T. A. J. Van Den Einden
Original Assignee
Koninklijke Philips Electronics N.V.
Philips Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V., Philips Ab filed Critical Koninklijke Philips Electronics N.V.
Priority to EP98900027A priority Critical patent/EP0917737A1/fr
Priority to KR1019980707310A priority patent/KR20000064615A/ko
Priority to JP10529172A priority patent/JP2000507052A/ja
Publication of WO1998032175A1 publication Critical patent/WO1998032175A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Semiconductor device provided with a metallization with a barrier layer comprising at least titanium, tungsten, or nitrogen, and method of manufacturing same.
  • the invention relates to a semiconductor device with a silicon substrate in which semiconductor elements are formed with semiconductor zones adjoining a surface of the substrate, which surface is provided with a layer of silicon oxide having contact windows within which the semiconductor zones are exposed, while on the layer of silicon oxide a metallization is formed in a layer system with a barrier layer comprising at least titanium, tungsten, or nitrogen and with a layer of conductive material lying on the barrier layer, which metallization is connected to the semiconductor zones.
  • the invention also relates to a method of manufacturing such a device.
  • the semiconductor elements may be, for example, bipolar transistors or MOS transistors.
  • the semiconductor zones adjoining the substrate surface then are emitter, base, and collector zones of the bipolar transistors or source and drain zones of the MOS transistors.
  • the semiconductor device may comprise a few to very many of such semiconductor elements.
  • the device is called integrated circuit in the latter case.
  • Said metallization then forms a first wiring layer on which in practice one or several further wiring layers are provided. These may be constructed in a similar layer system as the first wiring layer, with a barrier layer comprising titanium, tungsten, or nitrogen and with a layer of conductive material lying on the barrier layer.
  • a passivating layer is finally applied, usually a layer of silicon oxide or silicon nitride which is deposited in a PECVD process (Plasma Enhanced Chemical Vapor Deposition).
  • the barrier layer may be a layer of titanium nitride (TiN) or of a titanium-tungsten alloy (TiW) comprising 10 to 30 at. % titanium. Some 15 to 40 at. % nitrogen may also be added to the titanium-tungsten alloy (TiW(N)).
  • the layer of conductive material lying on the barrier layer may be an aluminum layer or a tungsten layer.
  • the barrier layer prevents the aluminum from reacting with the silicon exposed in the contact window, in the latter case the barrier layer protects the exposed silicon during the deposition of the tungsten.
  • the invention has for its object to counteract the above disadvantages by ensuring that the surface states can be passivated also in the case in which a barrier layer impermeable to hydrogen is used.
  • the semiconductor device is for this purpose characterized in that a layer of aluminum is provided on the silicon oxide layer below the metallization. It is found that the aluminum layer when heated reacts with the hydroxyl groups present at the surface of the silicon oxide layer, whereby aluminum oxide and atomic hydrogen are formed. This atomic hydrogen diffuses through the silicon oxide layer and passivates said surface states.
  • the bipolar transistors show a gain factor which is not dependent on the value of the collector current, while the MOS transistors all have the same threshold voltage in one and the same semiconductor device.
  • the surface of the silicon substrate is first provided with semiconductor elements formed with semiconductor zones adjoining a surface of the substrate, and is subsequently provided with a silicon oxide layer in which contact windows are formed within which the semiconductor zones are exposed, whereupon a layer system with a barrier layer comprising at least titanium, tungsten, or nitrogen and a superimposed layer of conductive material are deposited on the silicon oxide layer, and a metallization system connected to the semiconductor zones is subsequently formed in said layer system.
  • a layer of aluminium or of aluminium comprising a small quantity of silicon is provided on the silicon oxide layer below the metallization. This may be done in that the aluminum or aluminium-silicon layer is provided on the silicon oxide layer before the contact windows are formed. These contact windows are then etched into the aluminum layer and into the silicon oxide layer. The subsequent metallization layers are then deposited on the aluminum layer and in the contact windows. Preferably, however, the aluminum layer is not provided until after the contact windows have been formed in the silicon oxide layer. All layers in which the metallization is formed can then be deposited in one process step at a reduced pressure. The aluminum layer in that case is also provided on the silicon which lies exposed within the contact windows.
  • the aluminum layer is preferably 5 to 50 nm thick.
  • problems which may arise from the dissolution of silicon in aluminum are strongly counteracted. If silicon is dissolved in an aluminum layer deposited thereon, pits may arise in the silicon which are filled with aluminum from the layer. When thicker layers are used, these pits may become so deep that they short-circuit the pn junctions present in the silicon.
  • the use of the small thickness mentioned above reduces the quantity of aluminum in which silicon can be dissolved.
  • the quantity of aluminum in which silicon can be dissolved is further limited, and the formation of said pits is accordingly further counteracted, when the aluminum layer is so deposited that deposition of aluminum on the walls of the windows is counteracted. This may be readily achieved in a deposition process which shows a small step coverage during deposition of such thin layers. This is indeed the case in usual vapor and sputter deposition processes.
  • Fig. 1 shows a bipolar transistor provided with a metallization according to the invention diagrammatically and in cross-section
  • Fig. 2 shows a MOS transistor provided with a metallization according to the invention diagrammatically and in cross-section
  • Figs. 3 to 5 show a few stages in the manufacture of a semiconductor device by a first embodiment of the method according to the invention, diagrammatically and in cross-section,
  • Figs. 6 and 7 show a few stages in the manufacture of a semiconductor device by a second embodiment of the method according to the invention, diagrammatically and in cross-section
  • Fig. 8 shows a semiconductor device provided with a further embodiment of a metallization according to the invention diagrammatically and in cross-section.
  • Fig. 1 diagrammatically and in cross-section shows a bipolar transistor formed in a silicon substrate 1.
  • This substrate comprises semiconductor zones 2, 3, in this case a base zone 2 and an emitter zone 3 which adjoin a surface 4 of the substrate 1.
  • the substrate further comprises a collector zone 5 which is contacted by means of a buried zone 6 in a usual manner.
  • the surface 4 is provided with a silicon oxide layer 7 with contact windows 8 within which the semiconductor zones 2, 3 are exposed.
  • a metallization 9 connected to the semiconductor zones 2, 3 is formed on the silicon oxide layer 7.
  • This metallization is formed in a layer system 10 with a barrier layer 11 and a layer 12 of conductive material, in this case aluminum to which a few percents of silicon and copper were added, which lies on the barrier layer 11.
  • Fig. 2 diagrammatically and in cross-section shows a MOS transistor which is formed in a silicon substrate 20.
  • This substrate comprises semiconductor zones 21, 22, in this case a source zone 21 and a drain zone 22.
  • the substrate between these zones forms the channel region 24 of the MOS transistor.
  • the MOS transistor lies enclosed between field insulation regions 23.
  • the zones 21, 22 adjoin a surface 25 of the substrate 20.
  • Above the channel region 24 there is a gate electrode 27 lying on a gate oxide 26.
  • the surface 25 is provided with a silicon oxide layer 7 with contact windows 8 within which the semiconductor zones 21, 22 are exposed, similar to the case of the bipolar transistor.
  • a metallization 9 connected to the semiconductor zones 21, 22 is formed on the silicon oxide layer 7.
  • This metallization is formed in a layer system 10 with a barrier layer 11 and a layer 12 of conductive material, in this case aluminum to which a few percents of silicon and copper were added, which lies on the barrier layer 11.
  • the barrier layer 11 may be a layer of titanium nitride (TiN) or of a titanium-tungsten alloy (TiW) which comprises 10 to 30 at. % of titanium. An additional 15 to 40 at. % of nitrogen may have been added to the titanium-tungsten alloy (TiW(N)) .
  • the semiconductor device may comprise very many such semiconductor elements.
  • the metallization 9 then forms a first wiring layer on which one or several further wiring layers are provided in practice. These layers may each be constructed in a layer system of the same kind as the first wiring layer, with a barrier layer and a layer of conductive material lying on the barrier layer. After all wiring layers have been provided, finally, a passivating layer is provided, usually a silicon oxide or silicon nitride layer deposited in a PECVD process (Plasma Enhanced Chemical Vapor Deposition).
  • An aluminum layer 13 is formed on the silicon oxide layer 7 below the metallization 9. Upon heating, the aluminum layer 9 reacts with hydroxyl groups which are always present at the surface of the silicon oxide layer 7, whereby aluminum oxide and atomic hydrogen are formed. This atomic hydrogen diffuses through the silicon oxide layer 7 and passivates surface states which may be present at the surface 4, 25 of the silicon substrate. These surface states may give rise to leakage currents between base and emitter in bipolar transistors. This base leakage current has the result that a comparatively strong base current still flows in the case of small collector currents. The surface states can also capture charge during operation of the MOS transistors, so that the threshold voltage in a MOS transistor cannot be influenced by such a charge.
  • barrier layer 11 which comprises at least titanium, tungsten, or nitrogen, were not used.
  • This hydrogen is released upon heating from the passivating layer deposited in a plasma enhanced chemical vapor deposition process. Since said barrier layer is impermeable to hydrogen, however, this hydrogen cannot reach said surface states, or only with difficulty. Passivation accordingly does not take place, or not completely.
  • the use of the aluminum layer 13 achieves that the bipolar transistors show a gain factor which is not dependent on the value of the collector current, and that the MOS transistors all show the same threshold voltage in one and the same semiconductor device.
  • the surface 4 of the silicon substrate 1 is provided with a silicon oxide layer 7 after semiconductor elements have been formed in this substrate, with semiconductor zones 2 adjoining the surface 4.
  • An aluminum layer 13 is then deposited on the silicon oxide layer 7.
  • a photoresist mask 30 is formed thereon, which leaves the aluminum layer uncovered at the areas of the contact windows 8 to be formed. These contact windows 8 are subsequently formed in the aluminum layer 13 and in the silicon oxide layer 7. The semiconductor zones 2 are exposed within these windows 8.
  • a layer system 10 comprising a barrier layer 11 and a superimposed layer of conductive material 12 is deposited on the silicon oxide layer 7, in which layer system subsequently a metallization 9 connected to the semiconductor zones 2 is formed.
  • An aluminum layer 13 is then provided on the silicon oxide layer 7 below the metallization 9, in this embodiment in that the aluminum layer 13 is provided on the silicon oxide layer 7 before the contact windows 8 are formed.
  • the contact windows 8 are etched into the aluminum layer 13 and into the silicon oxide layer 7.
  • the subsequent layers of the metallization 10 are then deposited on the aluminum layer 13 and in the contact windows 8.
  • the aluminum layer 13 is not provided until after the contact windows 8 have been formed in the silicon oxide layer 7.
  • the deposition of all layers 13, 11 , 12 in which the metallization 9 is formed can then take place at a reduced pressure in one process step.
  • the aluminum layer 13 is thus also present on the silicon exposed at the surface 4 within the contact windows 8.
  • the aluminum layer 13 preferably has a thickness of 5 to 50 nm.
  • problems which may arise owing to the dissolution of silicon in aluminum are strongly counteracted.
  • silicon is dissolved in an aluminum layer deposited thereon, pits may arise in the silicon which are filled with aluminum from the layer. When thicker layers are used, these pits may become so deep that they short-circuit pn junctions present in the silicon.
  • the use of the small thickness mentioned above reduces the quantity of aluminum in which silicon can become dissolved.
  • the aluminum layer 13 is preferably so deposited that deposition of aluminum on the walls 31 of the windows 8 is counteracted. This may be readily achieved in a deposition process which shows a small step coverage in the deposition of such thin layers. This is indeed the case in usual vapor and sputter deposition processes. The quantity of aluminum in which silicon can be dissolved is further reduced thereby, so that the formation of said pits is further counteracted.
  • Fig. 8 finally shows a semiconductor device provided with a further embodiment of a metallization according to the invention diagrammatically and in cross- section.
  • the layer of conductive material 12 lying on the barrier layer 11 was an aluminum layer in the preceding examples, but it may alternatively be a tungsten layer.
  • the barrier layer prevents the aluminum from reacting with the silicon exposed in the contact window, in the latter case the barrier layer protects the exposed silicon during the deposition of the tungsten.
  • an aluminum layer 13 and a barrier layer 11 are deposited after the formation of the contact windows 8.
  • the contact window is filled with tungsten 32 in that a thick layer of this material is deposited and this thick layer is subsequently subjected to an etching treatment until the barrier layer 13 on the silicon oxide layer 7 has become exposed again. Then the conductive aluminum layer 12 is deposited, and finally the metallization 9 is formed.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention porte sur un dispositif semi-conducteur à substrat (1, 20) de silicium dans lequel les éléments semi-conducteurs sont formés avec des zones (2, 3, 21, 22) de semi-conducteurs contiguës à l'une des surfaces (4, 25) du substrat. La surface est munie d'une couche (7) d'oxyde de silicium avec des fenêtres de contact (8) par lesquelles les zones de semi-conducteurs sont exposées. Sur la couche d'oxyde de silicium, on forme une métallisation (9) reliée aux zones de semi-conducteurs dans un système de couches (10) comportant une couche barrière (11) comportant au moins du titane, du tungstène ou de l'azote, et une couche (12) d'un matériau conducteur (12). Une couche d'aluminium (13) est placée sur la couche d'oxyde de silicium (7) sous la métallisation (9). Malgré la présence de la couche barrière, les états de surface pouvant se présenter à la surface du substrat de silicium sont passivés par l'hydrogène libéré par la réaction entre la couche d'aluminium (13) et les groupes hydroxyles de la couche d'oxyde de silicium.
PCT/IB1998/000030 1997-01-16 1998-01-12 Dispositif semi-conducteur a metallisation et couche barriere comportant au moins du titane, du tungstene ou de l'azote et son procede de fabrication WO1998032175A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP98900027A EP0917737A1 (fr) 1997-01-16 1998-01-12 Dispositif semi-conducteur a metallisation et couche barriere comportant au moins du titane, du tungstene ou de l'azote et son procede de fabrication
KR1019980707310A KR20000064615A (ko) 1997-01-16 1998-01-12 반도체 디바이스 및 반도체 디바이스 제조 방법
JP10529172A JP2000507052A (ja) 1997-01-16 1998-01-12 少なくともチタン、タングステン又は窒素を有する金属化層が設けられた半導体装置及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP97200100.2 1997-01-16
EP97200100 1997-01-16

Publications (1)

Publication Number Publication Date
WO1998032175A1 true WO1998032175A1 (fr) 1998-07-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1998/000030 WO1998032175A1 (fr) 1997-01-16 1998-01-12 Dispositif semi-conducteur a metallisation et couche barriere comportant au moins du titane, du tungstene ou de l'azote et son procede de fabrication

Country Status (4)

Country Link
EP (1) EP0917737A1 (fr)
JP (1) JP2000507052A (fr)
KR (1) KR20000064615A (fr)
WO (1) WO1998032175A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1081752A1 (fr) * 1999-09-03 2001-03-07 Chartered Semiconductor Manufacturing Pte Ltd. Méthode pour former des interconnexions en cuivre par ajout d'une couche d'aluminium dans la barrière de diffusion
KR20010092679A (ko) * 2000-03-23 2001-10-26 포만 제프리 엘 반도체 디바이스 및 그 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3848260A (en) * 1971-11-15 1974-11-12 Nippon Electric Co Electrode structure for a semiconductor device having a shallow junction and method for fabricating same
US3860948A (en) * 1964-02-13 1975-01-14 Hitachi Ltd Method for manufacturing semiconductor devices having oxide films and the semiconductor devices manufactured thereby
DE3414781A1 (de) * 1983-04-25 1984-10-25 Mitsubishi Denki K.K., Tokio/Tokyo Vielschicht-verbindungsstruktur einer halbleitereinrichtung
US5366925A (en) * 1993-09-27 1994-11-22 United Microelectronics Corporation Local oxidation of silicon by using aluminum spiking technology

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3860948A (en) * 1964-02-13 1975-01-14 Hitachi Ltd Method for manufacturing semiconductor devices having oxide films and the semiconductor devices manufactured thereby
US3848260A (en) * 1971-11-15 1974-11-12 Nippon Electric Co Electrode structure for a semiconductor device having a shallow junction and method for fabricating same
DE3414781A1 (de) * 1983-04-25 1984-10-25 Mitsubishi Denki K.K., Tokio/Tokyo Vielschicht-verbindungsstruktur einer halbleitereinrichtung
US5366925A (en) * 1993-09-27 1994-11-22 United Microelectronics Corporation Local oxidation of silicon by using aluminum spiking technology

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1081752A1 (fr) * 1999-09-03 2001-03-07 Chartered Semiconductor Manufacturing Pte Ltd. Méthode pour former des interconnexions en cuivre par ajout d'une couche d'aluminium dans la barrière de diffusion
KR20010092679A (ko) * 2000-03-23 2001-10-26 포만 제프리 엘 반도체 디바이스 및 그 제조 방법
GB2365215A (en) * 2000-03-23 2002-02-13 Ibm Composite diffusion barrier for protecting copper interconnects in low dielectric constant materials from oxidation

Also Published As

Publication number Publication date
KR20000064615A (ko) 2000-11-06
EP0917737A1 (fr) 1999-05-26
JP2000507052A (ja) 2000-06-06

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