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WO1999048140A1 - Procede de fixation de microplaquettes empilees - Google Patents

Procede de fixation de microplaquettes empilees Download PDF

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Publication number
WO1999048140A1
WO1999048140A1 PCT/US1998/005424 US9805424W WO9948140A1 WO 1999048140 A1 WO1999048140 A1 WO 1999048140A1 US 9805424 W US9805424 W US 9805424W WO 9948140 A1 WO9948140 A1 WO 9948140A1
Authority
WO
WIPO (PCT)
Prior art keywords
pads
chips
bonding
carried out
circuit board
Prior art date
Application number
PCT/US1998/005424
Other languages
English (en)
Inventor
Anthony F. Bernhardt
Vincent Malba
Original Assignee
The Regents Of The University Of California
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Regents Of The University Of California filed Critical The Regents Of The University Of California
Priority to PCT/US1998/005424 priority Critical patent/WO1999048140A1/fr
Publication of WO1999048140A1 publication Critical patent/WO1999048140A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06579—TAB carriers; beam leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to stacking integrated circuit (IC) chips, particularly to stacking IC chips having surface pads rerouted to form pads on the side of the chips, and more particularly to attaching the side pads of such stacked chips to one another and/or to a circuit board via metal lines on a flexible plastic tape by an anisotropically conducting adhesive.
  • IC integrated circuit
  • the present invention utilizes the pad rerouting approach of the above-referenced applications, whereby the chips can be stacked on top of each other after the pad reroute, and then connects the stacked chips to each other and/or to a circuit board using a flexible plastic tape having metal lines and an anisotropically conducting adhesive (ACA).
  • the pads on the side of a chip are connected to metal lines on the flexible plastic tape (flex) by the ACA.
  • Metal lines on the flex are likewise connected to pads of other chips in the stack and/or to the circuit board.
  • the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; and the chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar.
  • An object of the present invention is to provide an attachment method for stacked IC chips.
  • a further object of the invention is to provide a method for attaching stacked IC chips having side-located pads.
  • a further object of the invention is to provide a laser patterned process to reroute pads of IC chips to the side surfaces of the chips.
  • a further object of the invention is to provide a method of connecting stacked chips to each other and/or to a circuit board.
  • Another object of the invention is to provide an attachment method for stacked IC chips utilizing metal lines on a flexible plastic tape and an anisotropically conducting adhesive.
  • Another object of the invention is to provide a method for interconnecting pads on stacked IC chips which involves rerouting the - 3 - pads to form pads on the side of the chips, stacking the chips, and connecting the pads of each chip to another chip and/or to a circuit board without solder bonding.
  • Another object of the invention is to provide stagger data and enable pads on various chips in the stack to permit connection by a single metal line to the board.
  • Another object of the invention is to provide a method for attaching pads of a stack of DRAM chips having corresponding address lines so as to form an address bus, thereby reducing the number of connections required to be made to a circuit board.
  • Another object of the invention involves attaching pads of stacked chips using metal lines on a flexible plastic tape by an ACA at a temperature substantially lower than solder bonding.
  • Another object of the invention is to provide an attachment method for stacked IC chips wherein the chips can be bonded all at once to a flexible tape using an ACA, and wherein the flexible tape accommodates dimension variation in the alignment of chips in a stack.
  • the present invention involves an attachment method for stacked IC chips.
  • the method of this invention utilizes rerouted chip pads which are formed on the side of the chip, stacking of the chips after pad reroute, and connecting the pads of each chip to pads on another chip and/or to a circuit board without solder bonding.
  • the pads on the side of a chip are connected to metal lines on a flexible plastic tape by an ACA, and metal lines on the flexible tape are likewise connected to pads on other chips and/or to a circuit board.
  • the flexible tape accommodates dimensional variation in the alignment of chips in the stack. Bonding of the ACA is accomplished at low temperatures and is otherwise simpler and less expensive than solder bonding.
  • the chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips such as DRAM chips.
  • the invention is particularly applicable to the attachment of stacked DRAM memory chips having pads to corresponding address lines on the various chips, wherein these pads are connected to the same metal line of the flexible tape to form and address bus, thereby adding the advantage of reducing the number of connections required to be made to - 4 - the circuit board due to bussing.
  • the method of this invention has applications in high density memory systems; e.g., supercomputers and hand-held electronics, such as personal digital assistants and cellular phones, as well as for other solid-state memory systems, such as used in telemetry packages.
  • Figure 1 illustrates the conventional method for attaching side-located chip pads to a substrate.
  • Figure 2 illustrates an embodiment produced by the method of the present invention of attaching side-located chip pads to a substrate.
  • Figure 3 illustrates another embodiment produced by the method of the invention of attaching side-located chip pads to a substrate.
  • Figure 4 illustrates another embodiment produced by the method of the present invention involving a stack of chips having side- located pads.
  • Figures 5A-5E illustrate operational steps involved in rerouting the surface pads of an IC chip to form side-located pads on the chip.
  • Figures 6A, 6B, and 6C illustrate assembly steps in accordance with the present invention for attaching a stack of IC chips having side-located pads to a circuit board.
  • the present invention is directed to an attachment method for stacked IC chips.
  • the present invention is particularly applicable in the 3-D packaging of integrated circuits utilized, for example, as integrated memory components in a high performance multichip module system.
  • the invention is particularly applicable in the dynamic random access memory (DRAM) stack fabrication and attachment process, as well as for high density 3-D packaging for electronics Basically, the method involves rerouting of the input/output (I/O) pads of IC chips or die to form new pads on one of the long sidewalls of the bares chip or die.
  • I/O input/output
  • the chips or die are stacked and bonded using a flexible tape and anisotropically conducting adhesive (ACA) and pads are arranged so that, in the case of DRAM chips, data lines and some control lines in a stack are staggered while address, power, ground, and some control lines are positioned identically.
  • ACA anisotropically conducting adhesive
  • This architecture permits bonding of the stack to a single-sided flexible tape using ACA.
  • the flexible tape is bonded to a circuit board using ACA to complete the assembly.
  • the rerouting of the pads may be carried out by either process of the above-referenced copending applications, or by a laser patterned process which uses a laser to expose an electrophoretic photoresist which is conformally plated onto a thin metal seed layer that covers the various surfaces. After resist exposure and development, copper, nickel, or gold is plated onto the seed layer through the resist mark. Finally, the residual resist and seed layer are removed, leaving conformally plated metal traces.
  • the laser lithography reroute process is described in greater detail hereinafter.
  • solder bonding is difficult to accommodate mechanical stresses generated by the differences in thermal expansion coefficient between the substrate and the chip stack (cube). Also, in the case of memory chips, far more pads are required on the substrate than are required by the interconnect method of the present invention, as described hereinafter with respect to Figures 2 and 3.
  • the basic principle of the present invention is to attach a flex cable or a flexible plastic tape having one or more metal lines thereon to the side-located (rerouted) pads of the chips of a stack (cube) using an ACA, and then connect the end of flex cable or flexible plastic tape to a pad on the circuit board, preferably also - 6 - using ACA.
  • ACA is commercially available and is exemplified by "ZAF," made by 3M.
  • the metal lines or lines on the flex tape may be, for example, Cu, Ni, or Au.
  • ACA is easier and cheaper to use than solder, with a typical cure temperature of 150°C compared to the 300°C solder reflow temperature, and there is none of the pad preparation, solder dissolution of pad metal, solder contact, embrittlement, and other problems associated with solder bonding. Also, unlike solder bonding, ACA does not have to be patterned, and ACA between adjacent pads does not cause a short circuit like a solder bond.
  • the flex cable or flexible plastic tape having metal lines thereon is commercially available, and is exemplified by Dynaflex manufactured by Sheldahl; and acts to relieve any stress due to bonding with the ACA since it is thin and flexible. For example, the tape has a thickness of lO ⁇ m to 75 ⁇ m, and the ACA provides a sufficient bond with a thickness of lO ⁇ m to 50 ⁇ m.
  • Figures 2 and 3 also illustrate bonding a memory chip stack or cube wherein the flex cable acts as a "bus" for addresses and control lines on the chips (i.e., I/O pads), which are bussed or connected to the same conductor on the flex cable and only one connection is made from the flex cable to the circuit board or substrate for each bussed line instead of one per chip, thus simplifying the fabrication of the circuit board or substrate.
  • the flex cable acts as a "bus" for addresses and control lines on the chips (i.e., I/O pads), which are bussed or connected to the same conductor on the flex cable and only one connection is made from the flex cable to the circuit board or substrate for each bussed line instead of one per chip, thus simplifying the fabrication of the circuit board or substrate.
  • a flex cable or flexible plastic tape generally indicated at 20 having an insulator (plastic) layer 21 and at least one metal line or layer 22 thereon is connected to a plurality of chips 23 having rerouted or side-located pads 24 by bonds 25 to an ACA layer.
  • the flexible tape 20 is bent at a 180° angle to enable the metal line 21 to be connected to a pad 26 on a substrate 27 via an ACA bond 28.
  • each of chips 23 are connected to a single pad 26 on substrate 27, for reasons discussed above.
  • FIG. 3 embodiment is similar to Figure 2 except it uses a flexible plastic tape having two metal lines or layers connected via an opening in the plastic or insulation layer, and thus similar components will be given similar reference numbers.
  • a flexible plastic tape or flex cable 30 composed of metal lines or layers 31 and 32 separated by an insulator (plastic) layer 33 having at least one opening 34 therein, whereby metal layers 31 and 32 are connected by a metal plug 35.
  • the metal line or layer 32 need not extend the full length of the insulator layer 33.
  • Metal line or layer 31 is secured to pads 24' of chips 23' by ACA bonds 25', as in the Figure 2 embodiment, while metal line or layer 32 is secured to a pad 26' of a substrate 27' by an ACA bond 28'.
  • One advantage of the Figure 3 embodiment is the elimination of the bend in the flexible plastic tape.
  • the metal lines 31 and 32 may be constructed to form a structure that is compliant under thermal stresses and designed to accommodate mechanical expansion and contraction. In essence, the problems of mechanical and electrical attachment are separated by the method of the present invention.
  • Attachment of the flexible plastic tape or flex cable (20 or 30) to the pads (24 or 24') of the stack of chips (23 or 23') of Figures 2 and 3 can be done all at once using heat and pressure to set the ACA (ZAF, for example). Then the flex cable (20 or 30) and the pads (26 or 26') of the substrate (27 or 27') can be connected in the same way. For example, a temperature of 140 to 180 °C and a pressure of 50 to 110 psi for a time period of 10 to 60 seconds provide an adequate ACA bond. A less desirable method of interconnection is to connect the flex cable to the pads of each chip of the stack (cube) by the ACA (ZAF) under each chip separately. The bonding operation is described in greater detail hereinafter with respect to Figures 6A-6C.
  • a two-metal line or level flex cable as shown in Figure 3, can be used for some minor routing of lines, as well as simple bussing, and three or more metal levels or lines allows extensive routing.
  • the solder solution doesn't work but the flex cable or flexible plastic tube with one or more metal lines or levels does.
  • Figure 4 illustrates chip-to-circuit board interconnection of a cube of stacked chips having rerouted or side-located pads extending to different sides of the chips.
  • a stack of chips 40 are stacked on a substrate or circuit board 41.
  • the pads 42 and 43, respectively, of each chip 40 are connected to pads 44 and 45 of the circuit board 41 via a pair of curved, flexible plastic tape members or flex cables 46 and 47, each having a metal line or layer and a plastic (insulator) layer, by bonds 48 and 49 to an ACA layer, respectively.
  • 6A-6C illustrate an application of the invention for the fabrication of a DRAM cube using a laser patterned 3-D interconnect process, as described in the above-referenced Provisional Application No. 60/041,262, filed March 19, 1997, and which was based on UCRL-JC-125631, "Fabrication of a DRAM Cube Using a Novel Laser Patterned 3-D Interconnect Process," V. Malba et al, presented at the Sixth International Conference on Multichip Modules, April 2-4, 1997, Denver, Colorado. Thus, Provisional Application No. 60/041,262 and UCRL-JC-125631 are incorporated herein by reference thereto.
  • the attachment method involving Figures 5A-5E and Figures 6A-6C involves a 3-D direct write laser lithography process used to reroute pads on DRAM die or chips to new pads on one of the long side-walls of the die.
  • Maskless laser direct writing overcomes the two- dimensional nature of photolithography: a focused laser beam simply forms a point or image in space which can be made to coincide with the surface of the part. Also, laser direct writing permits irradiation of vertical and horizontal die surfaces.
  • Electrodeposited photoresist which is an aqueous micellar solution of resist with minimal organic solvent and low solids content, can be electrochemically coated onto conductive surfaces with complicated topologies. With a positive EDPR, the laser- exposed areas are developed away, leaving openings in the resist through which copper, nickel, and gold can be plated. After plating, the resist is stripped, and the seed layer is removed. This process is simpler than earlier processes, in that the present process avoids the sidewall polishing and metallization steps, and the pad bumping and TAB attachment, as well as the corresponding wire bonding step.
  • the stacked die (cube) are bonded to single-sided flexible plastic, tape or flex cable using ACA, such as described above relative to Figures 2-4.
  • a relatively low metal line or layer count or level flex cable can be used because most of the I/O on a DRAM are intended to be bussed with corresponding I/O on other DRAMs. In particular, address, ground, - 9 - power, and some control lines are bussed on each cube; the data lines and other control lines are not bussed.
  • the stack can be tested on the flex cable before it is connected to the next level of packaging. After test, the flex cable is bonded to a circuit board, such as an FR-4 PCB with the same ACA.
  • the flex cable or flexible plastic tape and ACA easily accommodate mechanical strain, and die/ adhesive non-uniformity is unimportant for these pad-to-line connections. Furthermore, edges of the die in a stack do not have to be precisely coplanar because of the flexibility of the flex cable or tape and the method used to land it to the stack, as described hereinafter.
  • the light source of the direct write apparatus for example, an argon-ion laser operating in the multiline UV range of 338 to 364 nm.
  • the laser can be diverted along either of two beam paths, one normal to the surface, and the other at a 30° angle to the surface.
  • An acousto-optic modulator (AOM) is used in the apparatus to change the laser power, and as a fast electronic shutter.
  • the incident laser power is 6-20 mW, with a beam size of 6 ⁇ m x 35 ⁇ m (a cylindrical lens is used to focus the beam to a line, and an aperture is employed which allows the long dimension of the beam to vary from 5 to 65 ⁇ m).
  • UV microscope objectives are used in the apparatus to focus the laser beam after the cylindrical lens. These objectives are fixed, and a z-axis translation stage is used to focus the beam by moving the sample with respect to the objectives.
  • the apparatus includes a mirror mounted on a computer controlled stepper motor which is moved into the beam path to direct the beam through the angled or normal objectives.
  • a monitoring lamp directed through the normal objective by means of a beam splitter onto both the substrate surface and into a camera allows the operator to both register the die with respect to the substrate and to watch the laser rastering on the surface.
  • the laser metallization operation using the laser direct write apparatus is now set forth with reference to Figures 5A-5E.
  • the individual die are temporarily bonded to a silicon wafer carrier, allowing - 10 - the die to be processed in a batch for greater efficiency.
  • a conformal dielectric coating is applied in order to passivate the sidewalls of the die, as shown in Figure 5A, wherein a die or substrate indicated at 50 is coated with the dielectric coating, not shown.
  • Two dielectric processes have been used for this passivation step.
  • One process uses a vapor deposited polyimide coating which is easily ablated from the bond pads before metallization.
  • a second process uses PFCVD silicon oxide.
  • the SiOg process is both reliable and cost effective when applied to die with bond pads in the center of the die, because a shadow masking technique can be used to keep the bond pads clear of SiOg during deposition, eliminating the necessity of another processing step to open the vias.
  • the VDP polyimide process is preferred.
  • a metal seed multilayer 51 (see Figure 5A) is deposited everywhere on the die, and positive EDPR (resist) is electroplated onto the seed layer 51, as shown at 52 in Figure 5A.
  • the EDPR 52 is then exposed, as indicated at 53 in Figure 5B, with the computer controlled laser patterning apparatus, and the EDPR (resist) 52 is developed, as indicated by the via 54 in Figure 5C.
  • Copper (Cu) is then electroplated in the developed areas (via 54) throughout the mask plating, forming the metal interconnects, and nickel (Ni) and gold (Au) are electroplated on top of the copper to form the interconnect, as indicated at 55 in Figure 5D.
  • the EDPR 52 is stripped to reveal the metal seed layer 51 below, which is then etched away, as shown in Figure 5E (the seed layer is ⁇ 4 percent of the interconnect 55 thickness, so the thickness of the interconnect lines are not substantially reduced by the seed layer 51 removal).
  • the resultant metal traces 55 are rugged and reliable. They can be produced in thicknesses ranging from 2 ⁇ m to 10 ⁇ m, depending on the electrical requirements. An SEM of a metal trace at the edge of a 1 MG DRAM die showed no substantial thinning or defects in the trace having a thickness of 5 ⁇ m and width of 25 ⁇ m at the edge of the die.
  • the - 11 - above-referenced and incorporated document UCRL-JC-125631 illustrates in Figure 4 thereof a 16 Mb DRAM with pads near the median of the die which have been rerouted to the edge of the die, using the above- described laser patterning operation, and with the pads formed on the sidewall being 150 ⁇ m wide with a pitch of 350 ⁇ m. It should be noted that the reroute pattern is not identical for all die in a stack.
  • Figure 5 of above-referenced UCRL-JC- 125631 illustrates a stack of nine 16 Mb DRAMs showing the various side-wall pad configurations required for the memory architecture described in the document, with the top die being simply a silicon substrate for mounting a decoupling capacitor.
  • the laser writing operation easily accommodates the variation in the patterns to be written on the various die since only a change in the CAD file which drives the system is required. Cost benefits accrue from the reduction in the complexity of the next level of packaging.
  • the die are removed from the carrier and stacked using a polyimide film adhesive. Die are aligned with respect to one another using a simple mechanical fixture.
  • the alignment tolerances are not as severe for the flexible plastic tape or flex cable attachment process as they are for solder bump attach. A modest misalignment caused by variations in the thickness of the die and the stacking adhesive could produce a substantial runout error if solar bumps are used.
  • For the flex cable bonding process of the present invention there is no requirement for equal spacing between the die because pads are bonded to lines, not to individual pads.
  • the orthogonal alignment tolerances are also fairly modest because the size and pitch of the sidewall pads are much larger than are needed for the ACA (bonding) to be effective. Pads with pitch > 0.004 inches can be successfully bonded.
  • the pads on the stacks are bonded to the flex cable or tape in a single-step process.
  • This single-step process is schematically illustrated in Figure 6A, although the preferred single step uses a diaphragm bond.
  • the pads of the stack of die or chips 60 are bonded to a flexible plastic tape 61 of the type illustrated in Figures 2 and 3 via a layer 62 of ACA by a bonder 63, the die or chips 60 are supported on a removable member 64 located on a - 12 - support 65.
  • the preferred diaphragm bonder approximately 60 psi pressure is applied to the tape/ACA/stack through a thin aluminum diaphragm which seals one side of a nitrogen pressurized chamber. The entire assembly is heated to 140°C for a 30-second duration of the bonding.
  • the diaphragm bonder is preferred for stack-to-tape connection because the conformality of the nitrogen pressurized diaphragm provides equal force to the face of each die, assuring good contact to each die even if some are slightly misaligned.
  • the flexible tape 61 is bonded to a circuit board 66 via a layer 67 of ACA using a hot-bar thermode bonder 68.
  • the circuit board 66 is heated to 60°C and the thermode is held at 150°C.
  • a pressure of 100 psi is applied for 30 seconds.
  • the flex tape 61 is folded over and bonded to itself with an adhesive 69, such as Hardman D-85, as shown in Figure 6C.
  • the footprint of the stack plus the flex tape is little more than the footprint of the stack itself.
  • the present invention provides a new method for packaging integrated circuits in three dimensions.
  • the method may, for example, utilize a laser direct writing scheme to reroute I/O pads on DRAM chips to new pads on one of the long sides of the die, or it may be utilized to bond die to circuit boards wherein the pad reroute has been carried out by other techniques.
  • the principle bonding feature of the present invention is in the use of a flex cable or tape having a metal layer thereon which is bonded to the pads of the die and/or circuit board using ACA. This bonding approach enables bonding a number of pads on a stack of die or chips in a single operation, with the bonded pads being connectable to a single pad on the circuit board, thus simplifying fabrication.
  • While the invention is particularly applicable in the bonding of a stack of DRAM chips or die, it can be used in the fabrication of a solid-state memory or in high-density memory systems, such as supercomputers and hand-held electronics, such as personal digital assistants and cellular phones.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention se rapporte à un procédé de fixation de microplaquettes empilées comportant des circuits intégrés(IC). Ledit procédé consiste à relier des microplaquettes empilées, telles que des puces de mémoire DRAM, les unes aux autres et/ou à une carte. On déplace des plages de connexion des puces individuelles de manière à former des plages sur le côté d'une puce, puis on empile les puces les unes au dessus des autres, ce qui permet de réaliser les interconnexions souhaitées avec d'autres puces ou une carte par l'intermédiaire des plages de connexion disposées latéralement. On relie ces plages de connexion sur le côté de la puce à des lignes métalliques sur une bande en plastique flexible (flex) à l'aide d'un adhésif anisotropiquement conducteur (ACA). On relie par ailleurs les lignes métalliques sur la bande flex à d'autres plages de connexion sur des puces et/ou des plages de connexion d'une carte. Dans le cas d'un empilement de puces DRAM, il est possible de connecter les plages de connexion correspondant aux lignes d'adresses de diverses puces à la même ligne métallique sur la bande flex de manière à former un bus d'adresses. Ce procédé présente divers avantages : il est possible de réduire le nombre de connexions à effectuer sur la carte en raison du regroupement en bus ; la bande flex peut s'adapter à une variation dimensionnelle de l'alignement des puces dans la pile ; la liaison de l'adhésif ACA peut être effectuée à basse température et elle est en outre plus simple et plus économique qu'une liaison par soudure ; les puces peuvent être liées à l'adhésif ACA toutes à la fois si leurs cotés sont sensiblement coplanaires, comme cela est le cas lorsque la pile est constituée de puces identiques telles que des puces DRAM.
PCT/US1998/005424 1998-03-19 1998-03-19 Procede de fixation de microplaquettes empilees WO1999048140A1 (fr)

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PCT/US1998/005424 WO1999048140A1 (fr) 1998-03-19 1998-03-19 Procede de fixation de microplaquettes empilees

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Application Number Priority Date Filing Date Title
PCT/US1998/005424 WO1999048140A1 (fr) 1998-03-19 1998-03-19 Procede de fixation de microplaquettes empilees

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EP1317001A1 (fr) * 2001-11-30 2003-06-04 Infineon Technologies AG Dispositif à semi-conducteur
US6620651B2 (en) 2001-10-23 2003-09-16 National Starch And Chemical Investment Holding Corporation Adhesive wafers for die attach application
US7595550B2 (en) * 2001-10-26 2009-09-29 Entorian Technologies, Lp Flex-based circuit module
CN114126248A (zh) * 2022-01-21 2022-03-01 深圳原驰三维技术有限公司 一种印刷线路板焊盘、线路缺陷修复方法

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6620651B2 (en) 2001-10-23 2003-09-16 National Starch And Chemical Investment Holding Corporation Adhesive wafers for die attach application
US7595550B2 (en) * 2001-10-26 2009-09-29 Entorian Technologies, Lp Flex-based circuit module
EP1317001A1 (fr) * 2001-11-30 2003-06-04 Infineon Technologies AG Dispositif à semi-conducteur
CN114126248A (zh) * 2022-01-21 2022-03-01 深圳原驰三维技术有限公司 一种印刷线路板焊盘、线路缺陷修复方法

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