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WO1999003041A1 - Procede de commande de memoire - Google Patents

Procede de commande de memoire Download PDF

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Publication number
WO1999003041A1
WO1999003041A1 PCT/JP1998/003057 JP9803057W WO9903041A1 WO 1999003041 A1 WO1999003041 A1 WO 1999003041A1 JP 9803057 W JP9803057 W JP 9803057W WO 9903041 A1 WO9903041 A1 WO 9903041A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
error
correction
check
correction function
Prior art date
Application number
PCT/JP1998/003057
Other languages
English (en)
Japanese (ja)
Inventor
Jiro Kinoshita
Kazunari Aoyama
Norihide Sato
Original Assignee
Fanuc Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Ltd filed Critical Fanuc Ltd
Publication of WO1999003041A1 publication Critical patent/WO1999003041A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Definitions

  • the present invention relates to a method of controlling a non-volatile memory provided in a control device for controlling an industrial machine such as a CNC (Computer Numerical Control Device) or a port bot controller.
  • a CNC Computer Numerical Control Device
  • a port bot controller a method of controlling a non-volatile memory provided in a control device for controlling an industrial machine such as a CNC (Computer Numerical Control Device) or a port bot controller.
  • a controller which is usually loaded from a ROM or the like every time the power is turned on is used.
  • Data that can be lost when the power supply of the power supply such as a program or a calculated value is turned off is stored in volatile memory such as DRAM, and the data is stored even after the power supply of the user program or parameter is turned off.
  • the data that needs to be retained is stored in a non-volatile memory such as an SRAM whose power is backed up by a battery.
  • the SRAM backed up by the storage device stores data even when the power of the device is turned off, and the stored data is stored when the device is restarted. Is being read.
  • non-volatile memory Even if there is no failure in the device itself, a stochastic error called a soft error occurs due to static electricity or radiation even if there is no failure in the device itself. . Therefore, if the control device performs a parity check or the like and an error occurs in the content of the data, the data is erroneous. This has been detected and the system has been shut down. In conventional control devices, when an error is detected in nonvolatile memory, In this case, since the system is stopped, there is a possibility that the work or the drive device may be damaged in some cases.
  • the present invention solves the above-mentioned problem of the conventional memory control method of a control device, and is capable of non-volatile storage without stopping the system. It is an object of the present invention to provide a memory control method capable of detecting and correcting erroneous memory.
  • the memory control method of the present invention provides a memory control unit for controlling a non-volatile memory provided in a control device for controlling the movement of a machine movable unit, wherein the memory control unit has an error check Z correction function, A step of inspecting data read from the non-volatile memory using an error inspection / correction function to correct an error, and a step of transferring the corrected data to a control device.
  • the memory control method further includes the step of writing to the corrected data non-volatile memory and correcting the data in the non-volatile memory.
  • FIG. 1 is a block diagram for explaining a memory control method of the present invention.
  • FIG. 2 is a block diagram for explaining the outline of the SRAM module.
  • FIG. 3 is a schematic block diagram of a controller for performing memory control according to the present invention.
  • FIG. 4 is a schematic block diagram of a control device for performing memory control according to the present invention.
  • FIG. 5 is a diagram for explaining a data write operation
  • FIG. 6 is a diagram for explaining a first data read operation
  • FIG. 7 is a diagram for explaining a second data read operation.
  • FIG. 8 is a diagram for explaining a third data read operation.
  • FIG. 9 is a diagram for explaining the operation of checking the stored data of all the SRAMs.
  • FIG. 10 is a diagram for explaining an operation of performing an error check Z correction function itself.
  • FIG. 1 is a block diagram for explaining a memory control method according to the present invention.
  • a control device including a servo device 5 such as a CNC device will be described as an example.
  • a CPU 2 controls controlled devices and peripheral devices such as a servo device 5, an input device 8, and a display device 9 via a control device 1 and controls the devices.
  • These data and programs are stored in various storage devices such as DRAM 3, FROM 4, and SRAM.
  • the SRAM is a non-volatile memory that is backed up by the battery 7, and is included in the SRAM configuring the SRAM module 6 by a plurality of SRAMs.
  • data such as programs and data and data for error inspection / correction are stored.
  • the SRM module 6 is operated by the SRAM control unit 10 in the control device 1.
  • the SRAM control unit 10 is stored in the non-volatile memory (SRAM module 6). It reads out certain data and performs error detection on the data read out by the error check and correction function. If there is an error in the read data, the erroneous data is corrected to form corrected data.
  • the CPU 2 of the control device performs a normal operation by receiving the correction data from the SRAM control unit 10. Also, the SRAM control unit 10 transmits the correction data to the nonvolatile memory (SRAM module 6) simultaneously with the transfer of the correction data to the CPU 2. By writing, the data in the nonvolatile memory (SRAM module 6) can be corrected.
  • the writing to the non-volatile memory can be selectively performed, and the data corrected by the error checking and correcting function can be transferred to only the control device.
  • the control device can operate normally as long as the error check / correction function is effective.
  • FIG. 2 is a block diagram for explaining the outline of the SRAM module.
  • the SRAM module 6 includes a plurality of SRAMs 1 (61), SRAMs 2 (62), to SRAM n (6n).
  • SRAM 1 (61) and SRAM 2 (62) are programmed.
  • RAM n data is stored, and SRAM n (6 n) stores error check / correction check data. Note that the data content stored in the SRAM can be set arbitrarily.
  • Read and write control of each SRAM The operation is performed by an address from the SRAM control unit 10 and a RAM control signal.
  • the error correction Z correction function provided in the SRAM control unit 10 is used to read data from the SRAM 1 (61) and SRAM 2 (62) and to perform inspection and correction from SRAM n (6n).
  • the check data is read out, and an error check / correction is performed using the check Z correction check data.
  • ECC function Error Checking and Correction
  • the check data for error correction Z correction is stored in the SRAM n (6n) in the SRAM module 6, and is read at the time of error correction. .
  • the correction status data such as the number of corrections, the address of the correction data, or the content of the correction data is counted.
  • the data can be stored in a storage means, and thereby, it is possible to detect an error characteristic of the nonvolatile memory such as an error occurrence frequency, an error occurrence location, and an error type. And can be done.
  • the number of corrections in the correction status data can be stored in the counter when the correction data is transferred to the control device.
  • the data in the non-volatile memory and the error check / correction check data can be written independently, and the error check / correction function performs the error check / correction.
  • Read data for The function check of the error check and correction function can be performed by the detection. For example, by intentionally forming erroneous data, writing the erroneous data to a non-volatile memory, and performing an error detection and correction function on the data. , Error check, check of Z correction function can be performed.
  • FIG. 3 is an example of a configuration in which the error check / correction function of the ECC function and the parity check function is selected under the control of the CPU.
  • the block diagram shown in FIG. 4 is a configuration example in which the above selection is identified by ID data written in nonvolatile memory. Both figures show only the SRAM control unit and the SRAM module shown in FIG. 2 described above.
  • the SRAM control section 10 includes a data input section 71 for inputting and outputting data, a data output section 72, and a data for writing to the SRAM module 6.
  • Data writing unit 31 and check code writing unit 32 Retention data writing unit 33, data reading unit 41 for reading from SRAM module 6, check code reading unit 42, and parity data reading Section 43, a check code forming section 11 for performing an error checking / correcting function, an error checking section 12, an error correcting section 13 and a NORITY data forming section 21. And no.
  • the error detection section 22 and the error detection section A counter 14 for storing the correction status by the check correction function, a selection control section 51 for selecting the ECC function and the parity check function, and an SRAM module 6 It has an address control unit 73 for writing and reading data and a RAM control control unit 74 for each function.
  • the SRAM module 6 when the SRAM module 6 is used as the non-volatile memory, the SRAM module 6 includes the data SRAMs 61 and 62 and the check code and the data. Equipped with SRAM 63 for retention data. Although three SRAMs are shown in the configuration of FIG. 3, the number of SRAMs to be installed can be arbitrarily set, and any of the SRAMs can be used for check code and parity. The setting as to whether or not it is used for tee data can also be made arbitrarily.
  • the ECC function includes the check code forming section 11, the error checking section 12 and the error correcting section 13, and the check code writing section 32 and the check code writing section 32. It is configured by a quick code reading unit 42.
  • the check code is formed by the check code forming section 11 at the time of writing data, and is written to the SRAM 63 by the check code writing section 32.
  • the data is read out by the check code reading section 42, and the error detection section 12 and the error correction section 13 perform error detection and correction.
  • the parity check function includes a parity data forming unit 21 and a parity detecting unit 22, and a parity data writing unit 33 and a NORD.
  • the parity data is formed by the parity data forming unit 21 when data is written, and is written to the SRAM 63 by the parity data writing unit 33.
  • the parity data read unit 43 reads the data
  • the parity check unit 22 reads the data. Perform a recheck
  • the correction data corrected by the error correction unit 13 is transferred to the CPU 2 via the data output unit 72 at the same time as the correction status is sent to the counter 14. You can memorize it.
  • the correction data is written into the SRAM via the data writing section 31 to correct the erroneous data.
  • the configuration shown in FIG. 4 has the ECC function and parity check. The selection of the function is identified by the ID data written in the non-volatile memory, and the configuration is the same as that of FIG. 3 except for the configuration for this selection. is there . Therefore, only the identification configuration based on the ID data will be described below, and the description of the other common configurations will be omitted.
  • SRAM module 6, SRAM 6 1 for data, 6 2 your Yobichi E-click code, in addition to the SRAM 6 3 of Nono 0 literals y de over for data, for ID It has a memory of 64.
  • the memory memory 64 data for identifying whether the SRAM module 6 has selected the ECC function or the parity check function is stored.
  • the contents of the buffer memory 64 are read out by a buffer reading section 44 in the SRAM control section 10 and are selected. It is sent to the control unit 51.
  • the selection control unit 51 identifies which of the ECC function and the parity check function is selected according to the contents of the no-fault memory 64, and selects the SRAM control unit 1 Activates the error check function selected in 0.
  • the contents of the buffer memory 64 can be rewritten by a control signal (not shown) from the SRAM control unit 10, and the ECC function and parity can be rewritten. You can switch the check function.
  • FIG. 5 is a diagram for explaining a data write operation
  • FIGS. 6, 7, and 8 are diagrams for explaining a data read operation
  • FIG. 9 is an SRAM module.
  • FIG. 10 is a diagram for explaining an operation of checking the storage data of all SRAMs in the file
  • FIG. 10 is a diagram for explaining an operation of performing an error check / correction function itself. .
  • the configuration of FIG. 3 performs the ECC function
  • the corresponding signals in each figure are indicated by broken lines.
  • the data introduced from the data input section 71 is written into the SRAMs 61 and 62 by the data writing section 31 at the same time as the check code.
  • the data forming unit 11 supports input data A check code is formed, and the check code writing section is created.
  • the data captured by the data input section 71 is stored in the data SRAMs 61 and 62 in the SRAM module 6, and the corresponding check code is Stored in the check code SRAM 63 in the SRAM module 6.
  • the first data read operation is an operation in which the data corrected by the error check / correction function is transferred to the CPU and at the same time the data in the SRAM is also corrected.
  • the data read operation is an operation that only transfers the data corrected by the error detection and correction function to the CPU, and the third data read operation is an error. This is an operation to display only error detection by the inspection correction function.
  • the first data read operation will be described with reference to FIG.
  • the RAM controller control section 74 receives a read command from the CPU 2 power supply, the RAM controller control section 74 reads from the address control section 73. A control signal is sent to the SRAM module 6 together with the address to be output, and a normal read operation is performed. At this time, the address control unit 73 also transmits an address for reading the check code.
  • the data reading section 41 reads the data specified from the SRAM modules 6 1 and 6 2 for the data of the SRAM module 6 and sends the data to the error checking section 12. Further, the check code reading section 42 reads the check code corresponding to the data read from the check code SRAM 63 of the SRAM module 6. The data is read out and sent to the error checking unit 12.
  • the error detection unit 12 performs an error check on the data using the transferred data and the check code. If there is no error, the read data is transferred from the data output unit 72 to the CPU 2 side. If there is an error, the data is corrected in the error correction section 13, the corrected data is transferred from the data output section 72 to the CPU 2, and at the same time, the data writing section 31 is operated. The correction data is written to the data SRAMs 61 and 62 via the CPU. By this writing, the erroneous data in the SRAM is rewritten to the corrected data, and the correction is performed.
  • the data corrected by the error check / correction function can be transferred to the CPU 2 and the data in the SRAM can be corrected at the same time.
  • the correction data is transferred to the CPU 2, the number of corrections and the data contents before and after correction are corrected in the power counter 14.
  • the correction status data indicating the correct status is stored.
  • the correction status data stored in the counter section 14 is read out by a reading means (not shown). It is possible to understand the contents.
  • the operation of reading the second data will be described with reference to FIG.
  • the second data read operation is an operation in which only the operation of transferring the corrected data to the CPU in the first data read operation described in FIG. 6 is performed. In this operation, the data of the SRAM is not corrected. Since the operation is the same as that of the first data read operation except that the correction data is written to the SRAM, the detailed description is omitted here.
  • the erroneous data is corrected and transferred to the CPU side 2 as long as the error check and correction function functions effectively, so that the SRAM data remains uncorrected. Even so, the control device can operate normally.
  • the third data read operation will be described with reference to FIG.
  • the third data read operation is an operation of performing only data error detection in the first data read operation described with reference to FIG. 6, and in this operation. Do not correct the data. Since the operation of reading the first and second data is the same as that of the first and second data except for the correction of the data and the transfer of the corrected data, the detailed description here is omitted.
  • the error detection unit 1 2 detects the transferred data Check the data for errors by using the check code. If there is no error, the read data is transferred to the data output unit 72 side 112 side. If there is an error, the fact that the error has been detected is displayed on the display unit 75, and the system is stopped.
  • This operation can be used for inspecting defective products of the SRAM module and the SRAM module, and can be applied to, for example, a shipping test of a control device.
  • the RAM controller 74 receives a command from the CPU 2 to check the data stored in all the SRAMs. Addresses for reading data from all SRAMs are sent in order, and a control signal is sent to the SRAM module 6 to read data from all SRAMs. At this time, the address control unit 73 also transmits an address for reading the check code.
  • the data reading section 41 reads specified data from the data SRAMs 61 and 62 of the SRAM module 6 and sends the data to the error checking section 12.
  • the check code reading section 42 is a check code corresponding to read data from the SRAM 63 for the check code of the SRAM module 6. Is read out and sent to the error inspection unit 12.
  • the error detector 12 uses the transferred data and check code. And check the data for errors. If there is no error, the display means 75 or the like indicates that there is no data error. If there is an error, the error correction section 13 corrects the data, and the counter section 14 stores the content of the error, such as the location of the data error. .
  • the error inspection result stored in the counter section 14 can be displayed on the display means 75. According to this inspection result, even if the counter value is small, if the same address or data has been corrected several times, the SRAM has a hard failure. It will show you some possibilities.
  • an inspection data forming unit 15 and an inspection check code forming unit 16 are provided.
  • the test data forming section 15 is a section for forming test data to be written to the SRAM
  • the check code forming section 16 is a section for forming a check code for the test. It intentionally forms erroneous data or check code.
  • the test data forming unit 15 and the check code forming unit 16 are shown independently, and the test data is formed on the CPU 2 side. It is also possible to adopt a configuration in which a check code for inspection is formed in the check code forming section 11.
  • the formed inspection data and the inspection check code are written into the SRAM by the above-mentioned writing operation, and the third
  • the error check / correction function itself can be checked. For example, by intentionally forming erroneous data, writing the erroneous data to non-volatile memory, and performing an error checking and correcting function on this data. Check the error inspection / correction function.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Numerical Control (AREA)

Abstract

Dispositif de commande de mémoire qui permet de détecter et de corriger des erreurs dans une mémoire rémanente sans arrêter le système. Une partie de commande de mémoire destinée à commander la mémoire rémanente dans une unité de commande est dotée d'une fonction de détection/correction d'erreurs destinée à corriger les erreurs détectées dans des données, à transférer les données corrigées à l'unité de commande et à écrire les données corrigées dans la mémoire rémanente.
PCT/JP1998/003057 1997-07-07 1998-07-07 Procede de commande de memoire WO1999003041A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP9195207A JPH1125005A (ja) 1997-07-07 1997-07-07 メモリ制御方法
JP9/195207 1997-07-07

Publications (1)

Publication Number Publication Date
WO1999003041A1 true WO1999003041A1 (fr) 1999-01-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1998/003057 WO1999003041A1 (fr) 1997-07-07 1998-07-07 Procede de commande de memoire

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JP (1) JPH1125005A (fr)
WO (1) WO1999003041A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112540568A (zh) * 2019-09-20 2021-03-23 发那科株式会社 工业机械的数值控制装置

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5099342B2 (ja) * 2007-12-14 2012-12-19 オムロン株式会社 Ｐｌｃ用の部品実装基板
JP7016332B2 (ja) 2019-07-05 2022-02-04 華邦電子股▲ふん▼有限公司 半導体メモリ装置
WO2024176329A1 (fr) * 2023-02-21 2024-08-29 ファナック株式会社 Circuit de correction d'erreurs, dispositif de commande et procédé

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694596A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Memory control system
JPS62210547A (ja) * 1986-03-12 1987-09-16 Hitachi Ltd エラ−検出回路の診断方法
JPH0329006A (ja) * 1989-06-27 1991-02-07 Matsushita Electric Works Ltd 位置決め制御装置のデータチェック方法
JPH0474347U (fr) * 1990-11-08 1992-06-29
JPH0611043U (ja) * 1992-07-08 1994-02-10 横河電機株式会社 メモリ制御回路
JPH0652065A (ja) * 1992-08-03 1994-02-25 Fujitsu Ltd メモリ制御回路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694596A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Memory control system
JPS62210547A (ja) * 1986-03-12 1987-09-16 Hitachi Ltd エラ−検出回路の診断方法
JPH0329006A (ja) * 1989-06-27 1991-02-07 Matsushita Electric Works Ltd 位置決め制御装置のデータチェック方法
JPH0474347U (fr) * 1990-11-08 1992-06-29
JPH0611043U (ja) * 1992-07-08 1994-02-10 横河電機株式会社 メモリ制御回路
JPH0652065A (ja) * 1992-08-03 1994-02-25 Fujitsu Ltd メモリ制御回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112540568A (zh) * 2019-09-20 2021-03-23 发那科株式会社 工业机械的数值控制装置

Also Published As

Publication number Publication date
JPH1125005A (ja) 1999-01-29

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