[go: up one dir, main page]

WO1999027537A1 - Generation de tension sur puce pour circuits integres faible puissance - Google Patents

Generation de tension sur puce pour circuits integres faible puissance Download PDF

Info

Publication number
WO1999027537A1
WO1999027537A1 PCT/US1997/021513 US9721513W WO9927537A1 WO 1999027537 A1 WO1999027537 A1 WO 1999027537A1 US 9721513 W US9721513 W US 9721513W WO 9927537 A1 WO9927537 A1 WO 9927537A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
word line
node
output
supply
Prior art date
Application number
PCT/US1997/021513
Other languages
English (en)
Inventor
Weitong Chuang
Chun-Hsiung Hung
Kuen-Long Chang
Original Assignee
Macronix International Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co., Ltd. filed Critical Macronix International Co., Ltd.
Priority to US09/029,945 priority Critical patent/US6002630A/en
Priority to PCT/US1997/021513 priority patent/WO1999027537A1/fr
Publication of WO1999027537A1 publication Critical patent/WO1999027537A1/fr

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor

Definitions

  • the present invention relates to on chip voltage generation techniques for producing a voltage on chip which is outside the range of a power supply voltage supplied to the chip; and more particularly to the generation of word line voltages on low power memory devices like flash memory, where the power supply voltage may be less than the read potential required for sensing data in the memory.
  • Integrated circuits have in the past been manufactured in order to work with a power supply voltage of about 5 volts, within a specified range of +/-
  • On chip circuits however are often designed to operate at higher voltages for some purposes.
  • word lines which supply a gate potential to memory cells are often designed to operate at a read potential of 4 volts or more.
  • the low power supply voltage is insufficient to supply directly an on chip voltage high enough to drive the word lines.
  • This problem is dealt with by including charge pumps or other voltage supply boosters on the integrated circuits in order to supply the higher working voltages on chip. See for example United States Patent No. 5,511,026 entitled BOOSTED AND REGULATED GATE POWER SUPPLY WITH REFERENCE TRACKING FOR MULTI-DENSITY AND LOW VOLTAGE SUPPLY MEMORIES.
  • the '026 patent describes an integrated circuit memory having charge pumps configured to supply word line voltages at a level higher than the supply potential. Furthermore, the '026 patent describes the use of on chip charge pumps to provide a plurality of word line voltages for multilevel/memory devices, so that a greater working margin is provided between the memory cell states, than would be normally available using a standard supply potential.
  • One problem associated with the prior art approaches to on chip charge pumps for these purposes arises from the nature of the supply potential to vary over a significant range. For example, when the supply potential ranges from about 2.7 to about 3.6 volts, the amount of voltage boost necessary to produce an on chip 4 volt potential varies from 1.3 to 0.4 volts.
  • a single boost circuit to handle both extremes of the specified range of the supply potential with a 0.2 volt safety margin would require a 1.5 volt boost.
  • the resulting output of the boost circuit would vary from about 4.2 volts when the supply potential is 2.7, to 5.1 volts when the supply potential is 3.6.
  • the power consumed by the boost circuit is wasted.
  • the on chip voltage is often boosted to a level that may be too high. For example, if the target level is specified at a range from 4.0 to 5.0 volts, the boost ratio for a supply potential ranging from 2.7 to 3.6 volts should be set at about 1.5 volts.
  • the present invention provides an on chip voltage generation circuit suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts).
  • a low power supply voltage e.g., 2.7 to 3.6 volts.
  • it can be characterized as an integrated circuit having a voltage source input adapted to receive a supply potential within a pre-specified range of voltages, and including components on the integrated circuit that use an on chip voltage higher than the pre-specified range for the supply voltage.
  • a sense circuit is included on the integrated circuit which generates an output indicating a level of the supply voltage within the pre-specified range.
  • the on chip voltage supply circuit is coupled to the sense circuit and to the voltage source input and generates the on chip voltage in response to the output of the sense circuit and the supply voltage.
  • the sense circuit output indicates the level of the supply voltage so that the on chip voltage supply circuit is able to adapt the amount of boosting utilized to produce the on chip voltage.
  • the output of the sense circuit in one embodiment comprises a binary signal which indicates whether the supply voltage is above the threshold within the pre-specified range.
  • the on chip voltage supply circuit includes a first element which adds a first amount to the supply voltage to produce the on chip voltage when the binary signal is in a first state, and a second element which adds a second amount to the supply voltage to produce the on chip voltage when the binary signal is in a second state.
  • the output of the sense circuit indicates the level of the supply voltage relative to a plurality of thresholds, allowing for more control over the boosting circuit operation.
  • an integrated circuit memory device having a voltage source input, a memory array, and a plurality of address inputs.
  • the memory array includes a plurality of word lines coupled to the gates of memory cells in the array.
  • the memory cells in the array have a first threshold below a read voltage to indicate a first memory state and a second threshold above the read voltage to indicate a second memory state.
  • Word line driving circuits are responsive to addresses to supply a word line voltage to selected word lines to establish the read voltage at the gates of memory cells coupled to the selected word lines in response to the addresses.
  • An on chip voltage supply circuit as described above generates the word line voltage at a node coupled to the word line driving circuits in response to the output of a circuit that senses the level of the supply voltage, and in response to the supply voltage itself.
  • the word line driving circuits comprise a plurality of word line decoder sections, each section coupled to a corresponding subset of the plurality of word lines, and identified by a portion of an address.
  • a selector is coupled to the node at which the word line voltage is generated and to the plurality of word line decoder sections. The selector is responsive to the portion of the address that identifies the word line decoder section to connect the node to a selected word line decoder section.
  • the on chip voltage supply circuit comprises an idle pump which produces a charge on the node that establishes an idle voltage level when the memory is not being read.
  • a section boost pump is provided for boosting the charge on the node by an amount that depends on the output of the sense circuit when a selected decoder section is connected to the node.
  • the section boost pump provides charge to account for the charge lost to the parasitic capacitance of the word line decoder section.
  • a word line boost pump is also included which boosts the charge on the node to account for a charge lost due to the parasitic capacitance of a selected word line within a given section.
  • Address transition circuits are provided to indicate the switching between word lines within a section and enable the word line boost pump, and to indicate the switching between word line decoder sections to enable the section boost pump.
  • the word line boost pump can be enabled on transitions between sections to provide some additional boosting for the switching between word line decoder sections in one embodiment.
  • an additional boost pump is provided to boost the charge on the node on transitions between word line decoder sections which provides additional charge.
  • the word line boost pump is not enabled on transitions between word line sections.
  • the word line boost pump, the section boost pump, and the additional boost pump are all responsive to the output of the sense circuit to generate an amount of charge which is suited to the level of the supply voltage.
  • less than all of the pumps are responsive to the output of the sense circuit, according to the needs of a particular implementation.
  • the on chip voltage supply circuit is utilized in a memory array of floating gate memory cells, such as a flash memory.
  • the on chip voltage supply circuit provides a regulated word line voltage for use with the flash memory array.
  • FIG. 1 is a block diagram of an integrated circuit memory device including the on chip voltage supply circuit of the present invention.
  • Fig. 2 is a block diagram of the word line boost circuit of the present invention for use in the system of Fig. 1.
  • Fig. 3 is a simplified diagram of the supply voltage level sensor used in the system of Fig. 1.
  • Figs. 4A, 4B and 4C illustrate the components of the boost circuit used on transitions between word line decoder sections, and the voltage regulation circuit for the system of Fig. 2.
  • Fig. 5 is a more detailed block diagram of the sense circuit of Fig. 3.
  • Fig. 6 is a schematic diagram of the idle pump for the system of Fig. 2.
  • Figs. 7 A, 7B, 7C and 7D illustrate the implementation of the read pump in the system of Fig. 2.
  • Fig. 8 is a plot of the voltage levels at selected nodes in Figs. 4A-4C, used for illustrating the operation of the boost circuit.
  • Fig. 9 is a graph of voltages at selected nodes in the circuits of Figs. 7A- 7D used for illustrating operation of the read pump.
  • Fig. 1 provides an overview of a flash memory device incorporating the on chip voltage supply circuit for generating read mode word line voltages.
  • Fig. 1 illustrates an integrated circuit.
  • the integrated circuit includes a supply voltage input 10 adapted to receive a supply voltage VDD.
  • the supply voltage in one example embodiment is 2.7 to 3.6 volts.
  • a ground input 11 is provided.
  • Other input and output pins are included on the integrated circuit including address inputs 12, control signal inputs such as a chip enable input 13 and an output enable input 14, and data input/output pins 15.
  • the integrated circuit includes a flash memory array 16 which includes a plurality of word lines represented for example by the arrows 17.
  • the word lines are driven by a word line decoder that includes a plurality of sections, including word line decoder section 0, word line decoder section 1, word line decoder section 2, word line decoder section 3, word line decoder section 4, word line decoder section 5, word line decoder section 6, and word line decoder section 7 in this example.
  • a column decoder and data input/output circuit 18 is coupled to a plurality of bit lines represented by arrows 19 in the array 16. The column decoder 18 and the word line decoder 20 are controlled by addresses received from the address inputs 12.
  • the address can be characterized as including row addresses on line 21 and column addresses on line 22 which drive the word line decoder 20 and the column decoder 18 respectively.
  • a word line predecoder 23 is included which is coupled to the address line 12.
  • the word line predecoder generates select control signals SEL(0-7) on line 24 which are supplied respectively to the word line decoder sections 0-7. Three of the more significant bits of the row address portion of the address on line 12 are used to control the word line predecoder 23 and select a particular word line decoder section from the word line decoder 20.
  • the word line predecoder 27 also generates control signal RSEL(0-7) on line 25.
  • Mode logic 26 is included on the chip.
  • the mode logic 26 receives the chip enable and chip select signals on lines 13 and 14, as well as other signals in order to control the mode of operation of the flash memory.
  • Flash memory devices include a read mode, a program mode, an erase mode, and other modes as suits a particular implementation for program and erase operations.
  • a READ control signal on line 40 is generated by the mode control logic 26.
  • Program and erase mode word line voltage pumps 28 are included on the chip.
  • a read mode word line voltage boost circuit 29 is included.
  • the read mode word line voltage boost circuit 29 includes compensation for the level of the supply potential.
  • the output of the read mode word line boost circuit 29 includes eight word line voltages AVX(0-7) on line 30 for the respective word line decoder sections.
  • the read mode word line voltage boost circuit 29 is responsive to the output on line 31 of a supply voltage level sensor 32.
  • the supply voltage level sensor 32 is connected to the supply voltage input 10 and to the ground input 11 and generates an output on line 31 which indicates the level of the supply voltage at the input 10.
  • the read mode word line voltage boost circuit 29 is responsive to address transition detection circuits 33 and 34.
  • the address transition detection circuit 33 generates a signal on line 35 which indicates the transition of the three more significant bits of the row address which are used to select a particular word line decoder section.
  • the signal ATD0 on line 35 indicates a transition between word line decoder sections in the word line decoder 20.
  • the address transition detection circuit 34 is responsive to the less significant bits in the row address to indicate a transition between word lines.
  • the output ATDX on line 36 indicates a transition between word lines within a particular word line decoder section.
  • the present invention is applied as shown in Fig. 1 for word line voltage generation for the read mode of a flash memory device.
  • the invention is particularly suited for flash memory with low power supply voltage in the range for example of 2.7 to 3.6 volts.
  • the supply voltage level is sensed, and the boosting power of the word line voltage generator is controlled in response to the level of the supply potential.
  • the boosting is reduced to save power.
  • the present invention by controlling the amount of boosting in response to the level of the supply potential, reduces transient fluctuations in the on chip voltage which are generated by prior art systems, by limiting the amount of boosting at the high end of the supply potential.
  • control signal generated by the sense circuit is a binary signal, indicating whether the supply potential is greater than or equal to 3.2 volts or other predetermined level for a regulated external power supply falling in the range of 2.7 to 3.6 volts.
  • more levels are sensed.
  • multiple comparators can be applied to detect three levels for example including greater than 3.3 volts, less than 3 volts, and between 3 and 3.3 volts. Therefore, performance in the terms of power dissipation, and otherwise, can be further optimized.
  • FIG. 2 A block diagram of the circuitry utilized according to the present invention is shown in Fig. 2. As shown in the figure, there are a number of circuit blocks including a boost circuit 50 (section boost pump), an idle pump 51, a read pump 52 (wordline boost pump), and an auxiliary boost pump 53.
  • the boost circuit 50, idle pump 51, read pump 52, and auxiliary boost pump 53 all supply charge to a node 54 at which a voltage AVXS is established.
  • a voltage regulation circuit 55 is coupled to node 54.
  • the voltage regulation circuit 55 is enabled and disabled by transistor 56 having a control signal READ supplied at its gate on line 57 (corresponding to line 40 of Fig. 1).
  • the control signal READ is set to a logic 1 when the device is in the read mode, and when the chip enable signal goes active.
  • the voltage regulation circuit 55 is enabled in the read mode.
  • the node AVXS is coupled to word line driving circuits which include for each subset of the plurality of word lines a read control switch 58, 59, and a word line decoder section 60, 61.
  • the word line decoder section 60 corresponds to the word line decoder section 7 of Fig. 1 and drives the word lines WL( 1792:2047) on line 62.
  • the word line decoder section 61 corresponds to the decoder section 0 of Fig. 1 and drives the word lines WL(0:255) on line 63.
  • the read control switch 58 and the word line decoder section 60 are used to drive word line decoder section 7.
  • the control signal READ on line 57 is supplied to the read control switch 58.
  • the control signal RSEL7 is supplied to the read control switch 58 on line 64.
  • the output of the read control switch 58 is supplied on line 70 and provides a potential AVX to the word line decoder section 60.
  • the word line decoder section 60 is enabled by the SEL7 signal on line 66, and the less significant bits of the address supplied on line 59.
  • the output of the word line decoder section 60 is a subset of the plurality of word lines in the array on line 62. In this example, the subset includes word lines WL(1792:2047).
  • the read control switch 59 and the word line decoder section 61 are utilized. Read control switch 59 receives the READ signal on line 57, and the control signal RSEL0 on line 65.
  • the output is the AVX voltage on line 71 which is supplied to the word line decoder section 61.
  • the word line decoder section 61 is enabled by the SEL0 signal on line 67 and the address signals on line 69 to drive the word lines on line 63.
  • the subset of word lines driven by the word line decoder section 61 includes word lines WL(0:255).
  • Corresponding word line decoder sections 1, 2, 3, 4, 5 and 6 are not shown in Fig. 2 for simplicity, but include similar connections.
  • the output of the supply voltage level sensor 32 is supplied on line 80 to each of the boost circuit 50, the idle pump 51, the read pump 52, and the auxiliary boost pump 53.
  • the address transition detection circuits 33 and 34 of Fig. 1 supply the section transition signal ATDO on line 81 to the boost circuit 50 and the auxiliary boost pump 53.
  • the word line transition signal ATDX is supplied on line 82 to the read pump 52.
  • the control signal READ is supplied on line 83 to the idle pump 51.
  • the amount of charge supplied to the node 54 is dependent on the output of the supply voltage sensor 32 of Fig. 1.
  • the operation of each of the boost circuit 50, idle pump 51, read pump 52 and auxiliary boost pump 53 are described in more detail below.
  • Fig. 3 provides a simplified diagram of the supply voltage sensor 32 of
  • Fig. 1 The supply voltage is applied at node 100 in Fig. 3.
  • a first resistor RI and a second resistor R2 are coupled in series between node 100 and ground.
  • Node 101 is found between resistors RI and R2.
  • Node 101 is connected to the first input of a comparator 103 and a reference potential is supplied on a second input 104 to the comparator 103.
  • the output of the comparator is the signal
  • VHH which is applied on line 80 in Fig. 2.
  • the comparator is used to detect the voltage level of the external power supply VDD.
  • the comparator relies on a stable Vref on line 104.
  • a preferred reference voltage is approximately 2 volts given a power supply of 2.7 volts to 3.6 volts.
  • Figs. 4A-4C illustrate one example boost circuit for use in the system of Fig. 3.
  • the first stage in Fig. 4A receives as input the ATDO signal on line 200.
  • the signal is applied to first inverter 201 which generates a signal NATD on line 202.
  • Line 202 is connected to inverter 203 which drives the input of inverter 204.
  • the output of inverter 204 is applied to node 205 labeled NW1.
  • Node 205 is connected across capacitor 206 to the AVXS node 210, which corresponds to node 54 of Fig. 2.
  • the inverter 204 has its power supply terminal 211 coupled through the level selection circuit 288.
  • the level selection circuit 288 includes n- channel transistor 207 and p-channel transistor 208 connected in parallel between the supply terminal 211 of the inverter 204, and the power supply input 212 which receives voltage VDD.
  • the gates of the transistors 207 and 208 are connected to the VHH signal on line 213.
  • VHH the level of the output of the inverter 204 depends on the output of the comparator shown in Fig. 3.
  • the second stage of the boost pump is illustrated in Fig. 4B.
  • the stage in Fig. 4B receives as input the READ signal on line 220, the address transition signal ATDO on line 200, and the chip enable signal (active low) CEL on line 221. Also the output at node 210 is coupled to the voltage regulation circuit 222.
  • the READ signal on line 220 is connected to inverter 223.
  • the output of inverter 223 is connected to node 224 labeled NX0.
  • Node 224 is connected to the gate of p-channel transistor 225 and to the gate of n-channel transistor 226.
  • P-channel transistor 225 has its source connected to the supply terminal 212, and its drain connected to the anode of diode 227. The cathode of diode
  • NAND gate 227 is connected to the node 228, labeled ATD3.
  • the READ signal on line 220 is connected as one input to NAND gate 229.
  • the other input to the NAND gate 229 is the address transition signal ATDO.
  • the output of NAND gate 229 drives inverter 230.
  • the output of the inverter 230 is connected to node 231, labeled ATD2.
  • Node 231 is coupled to the source and drain of capacitor connected transistor 232.
  • the gate of transistor 232 is connected to node 228.
  • the chip enable signal CEL on line 221 is connected to the gate of n- channel transistor 233.
  • the drain of transistor 233 is connected to node 228, and the source of transistor 233 is connected to the ground terminal.
  • Node 228 is also connected to the gate of transistor 235.
  • the source of transistor 235 is connected to output node 210.
  • the drain of transistor 235 is connected to the supply terminal 212.
  • a voltage regulator 222 is coupled to the output node 210.
  • the READ signal on line 220 is supplied to the voltage regulator 222, and used to enable and disable the voltage regulator 222.
  • a wide variety of voltage regulators 222 could be used.
  • the voltage regulator 222 includes a forward biased diode string 240 connected between node 210 and the source and well of triple well p-channel transistor 241.
  • the gate of transistor 241 is coupled to a reference voltage (for example 2.0 volts), and the drain of transistor 241 is connected to the drain of n-channel transistor 242, which has its source connected to ground, and its gate connected to the
  • READ signal line 220 This circuit will clamp node 210 at about 4.8 volts.
  • Fig. 4C The final stage of the boost circuit is illustrated in Fig. 4C.
  • This circuit receives the READ signal on line 220 as input.
  • the input 220 is connected to the inverter 245.
  • the output of the inverter 245 is connected to the source of transistor 246.
  • Transistor 246 has its gate connected to the supply terminal 212 and its drain connected to node 247.
  • Node 247 is connected to the input of inverter 248 and the output of inverter 249.
  • the inverters 248 and 249 have their supply terminals coupled to the node 210.
  • the output of inverter 248 and the input of inverter 249 are connected to the node 250, labeled NW0.
  • Node NWO is connected to the gate of triple well p-channel transistor 251 and triple well p-channel transistor 252.
  • Transistor 251 has its source and n-well coupled to the terminal 210 and its drain coupled to the source of transistor 252. The drain and n-well of transistor 252 are connected to the supply terminal 212.
  • transistors 232, 233, 226, 235, 241, 246, 251 and 252 have a thicker gate oxide, for example about 180 angstroms, than the other transistors in the circuit.
  • the other transistors typically have a gate oxide thickness of about 100 angstroms.
  • the thicker gate oxide allows for higher voltage operation.
  • the transistors 232, 235 and 246 comprise "native mode" transistors, in which the channel region has the native substrate p-type doping.
  • the other transistors have a threshold enhancement implant which raises the threshold of the transistor slightly. Thus, transistors 232, 235 and 246 have a lower threshold voltage than other transistors in the circuit.
  • the boost pump of Figs. 4A-4C operates to boost the node 210 by an amount which is dependent on the signal VHH on line 213.
  • the address transistion signals ATDO and ATDX are produced using address transistion detection circuit, such as that described in our co-pending United States Patent Application entitled ADDRESS TRANSISTION DETECTION CIRCUIT, filed 15 November 1996, having application number 08/751,513, or another address transistion circuit as known in the art.
  • a preferred length of an address transistion signal for this embodiment is about 20 nanoseconds for each transistion in the address signal supplied to the chip.
  • the READ signal on line 220 goes high. This enables the voltage regulation circuit 222, and turns on transistor 225 and turns off transistor 226. Also, this signal causes node NWO to go high turning off transistors 251 and 252.
  • the stage of Fig. 4C causes the node 210 to be driven to the supply potential 212, because node NWO is low in this circumstance.
  • the address transistion signal ATDO on line 200 goes high, the node 231 is driven high. Node 228 was at a low potential until the chip enable signal was pulsed low, turning off transistor 233. Transistor 225 is fully turned on and the node 228 is pulled to about the supply potential less the threshold drop across diode 227.
  • the output AVXS is thus pulled to a level near the supply potential as well.
  • node 231 goes high, this pulls up node 228 to a level of about one and a half of the supply potential VDD. Consequently, transistor 235 is almost fully turned on, causing AVXS to be charged to about VDD level.
  • the stage illustrated in Fig. 4A operates to boost the node AVXS in response to the signal ATDO on line 200 and the signal VHH on line 213.
  • ATDO goes high
  • node 202 goes low and node NWl at point 205 goes low.
  • node 205 is pushed high. This boosts node 210 across capacitor 206 an amount which depends on the voltage at node 211.
  • VHH is a logic 1, meaning that the sensing circuit indicated that the supply potential VDD is higher than a predetermined level, then the p-channel transistor in the inverter 204 is connected to the supply potential VDD through the n- channel transistor 207. Hence the node NWl can only reach the supply potential minus a threshold voltage. This effectively reduces the final voltage level of
  • Fig. 8 provides a partial timing diagram by which operation of the circuit of Figs. 4A-4C can be understood. In Fig. 8, the voltages for various nodes in the circuit are shown. The traces are given the same reference number as their corresponding node in Figs. 4A-4C. Thus, trace 210 corresponds to the voltage AVXS at node 210.
  • Trace 200 corresponds to the voltage at node 200 for the address transistion detection signal ATDO
  • trace 228 corresponds to the voltage ATD3 at node 228
  • Trace 205 corresponds to the voltage at node 205.
  • the READ signal is asserted causing the node 228 to rise to a level slightly below the supply potential.
  • node 228 rises to a level equal to about one and a half of the supply potential.
  • node 205 begins to discharge to about the ground potential as driven by the output of inverter 204.
  • AVXS is finally charged to slightly less than VDD level, since transistor 235 is almost fully turned on.
  • node NWl 205 rises to about the level determined by the level controlling circuit 288. Node 228 falls. However, the boosting action which results from the rising of node 205 causes the voltage at node AVXS to rise to its full read potential close to 5 volts.
  • the pumping energy provided by the boost circuit of Figs. 4A-4C is sufficient to handle the parasitic capacitance of switches between word line decoder sections on the device.
  • Fig. 5 is a circuit diagram of the comparator 103 shown in Fig. 3 for one example implementation.
  • the resistors RI and R2 of Fig. 3 are implemented by resistor 300 and resistor 301.
  • the inputs to the comparator include the reference voltage VREF at node 302, and the divided supply potential at node 304.
  • the supply potential is divided down by resistors 300 and 301.
  • the reference voltage at node 302 is set to about 2 volts using a stable reference supply.
  • the trip point of the comparator of Fig. 5 is determined by the selection of the values of the resistors 300 and 301. For example, if the ratio of resistor 300 to resistor 301 is about 3 to 5, then the trip point is about
  • the comparator is implemented by connecting node 304 to the gate of the triple well n-channel transistor 310, and connecting the reference potential at node 302 to the gate of triple well n-channel transistor 311.
  • the drain of transistor 310 is connected to the drain of p-channel transistor 312.
  • the gate of transistor 312 is connected to its drain, and the source of transistor 312 is connected to the supply potential.
  • the drain of transistor 311 is connected to the drain of p-channel transistor 313 which has its source connected to the supply potential, and its gate connected to the gate of transistor 312.
  • the source and n-well of both transistors 311 and 310 are coupled to the drain of n-channel transistor 314 which has its gate connected to the supply potential, and its source connected to transistor 315.
  • N-channel transistor 315 has its gate connected to the control signal READ and its source coupled to ground.
  • the output VHH on node 305 is driven by the inverter 316 which has its input driven by the output of inverter 317.
  • Inverter 317 is connected to the node between transistors 311 and 313.
  • Fig. 6 illustrates one example embodiment of the idle pump 51 as illustrated in Fig.2.
  • the idle pump serves to supply charge to the node 210 at which the voltage AVXS is generated in order to overcome gradual loss in voltage due to leakage current.
  • the idle pump receives as inputs the READ signal on line 220, and the control signal VHH on line 213.
  • An oscillator is implemented with NAND gate 350 which has its output connected to inverter 351, which in turn has its output connected to inverter 352.
  • the output of inverter 352 is connected back as an input to the NAND gate 350.
  • the control signal VHH the control signal
  • transistor 353 This is accomplished by connecting the drain of transistor 353 to the output of the NAND gate 350, the source of transistor 353 to capacitor 354, and the opposite node of capacitor 354 to ground.
  • the gate of transistor 353 is connected to the control signal VHH.
  • transistor 355 and capacitor 356 are coupled to the output of inverter 351.
  • transistor 357 and capacitor 358 are coupled to the output of inverter 352. This causes the frequency of oscillation at the output of inverter 352 to be a lower value when VHH is high, than when VHH is low.
  • the idle pump receives as input the output of inverter 352. This input is supplied to the input of inverter 360 which has its output connected to the input of inverter 361.
  • inverter 360 The output of inverter 360 is connected across capacitor 362 to node 363.
  • the output of inverter 361 is connected across capacitor 364 to node 365.
  • Three triple well n-channel transistors 366, 367, 368 are coupled in series between the supply potential at node 303, and the node 210 at which the voltage AVXS is generated.
  • the transistors 366, 367, 368 are also "thick" transistors having gate oxides of about 180 angstroms.
  • the pumping capability and consequently the power consumption of the charge pump used for the idle pump is dependent on the level VDD, and the frequency of oscillation. Thus when VDD is high, it is desirable to reduce the pumping frequency in order to reduce power consumption.
  • the idle pump is a relatively weak pump in the sense that its pumping capability is small compared to the read pump.
  • the main function of the idle pump is to supply charge to overcome losses due to leakage.
  • the clock frequency of the idle pump is relatively slow, and the pumping capacitances 362, 364 are relatively small.
  • the pumping capability of the idle pump can be enhanced. Such an approach is especially useful for low power supply situations.
  • a signal AVXS may be pumped to a higher level by the idle pump, before the next read operation is requested. For example, the voltage level AVXS drops due to switching between word lines.
  • the level AVXS is not high enough, it takes more power for the read pump to recharge the voltage AVXS to the desired level between reads.
  • the pumping capability of the read pump can be reduced.
  • the total power of consumption can be reduced, by use of a more powerful idle pump.
  • a two stage charge pump is shown. Depending on the value of the external power supply voltage and the target value of the voltage AVXS at node 210, single stage or larger number of stages could be used instead.
  • Figs. 7A-7D illustrate an example implementation of the read pump 52 as shown in Fig. 2.
  • the read pump is divided into four components.
  • the first component shown in Fig. 7A generates a control signal BCKl on node 400.
  • the input is the address transition detection signal ATDX on line 401, which is generated upon the detection of the address transition in the less significant bits of the row address indicating a change between word lines, but not a change between word line sections.
  • the signal ATDX is not asserted when the signal ATDO is asserted.
  • the circuit includes SR latch 402 which receives the ATDX signal at its S input.
  • the output of the latch 402 is connected to node 403 which is fed back through a delay circuit comprised of inverter 404, capacitor 405, and inverter 406.
  • the output of the inverter 406 drives the R input of the SR latch 402. This results in a pulse on node 403 of a duration which is set by the size of the capacitor 405, and the driving capacity of the inverter 404 and 406.
  • Node 403 is connected to inverter 407.
  • the output of inverter 407 is connected to the input of inverter 408 to the output of the inverter 408 is connected to node 400 to supply the signal BCKl .
  • Fig. 7B illustrates the generation of the BCK2 on node 410.
  • the input to the circuit in Fig. 7B is the control signal BCKl from node 400.
  • Node 400 is connected to a one shot circuit consisting of NOR gate 411 which has its input connected to node 400, and the other input connected to delay circuit comprised of a series of inverters 412, in this example three inverters in series.
  • the output of the one shot circuit is a pulse which is supplied to the input of the SR latch 413.
  • the output of the SR latch is connected to node 414 which is fed back through the delay circuit composed of inverter 415, capacitor 416, and inverter 417.
  • the output of inverter 417 is connected to the R input of the SR latch 413. This results in a pulse at node 414 which is applied to the input of inverter 418.
  • inverter 418 The output of inverter 418 is connected to the input of the inverter 419.
  • the output of inverter 419 is the control signal BCK2 at node 410.
  • Figs. 7C and 7D illustrate the alternative charge pump circuits used for the read pump.
  • the charge pump which is selected depends on the value of the signal VHH. Also, the amount of pumping depends on the frequency and pulse widths of the control signals BCKl and BCK2.
  • Fig. 7C is activated when the signal VHH is low. Thus, it receives as input the signal VHH from node 213. Node 213 is connected through inverter 425 as the input of NAND gate 426. The second input the NAND gate 426 is the control signal BCKl on node 400.
  • the signal VHH is also supplied through inverter 427 as a first input to NAND gate 428.
  • the second input to the NAND gate 428 is the control signal BCK2 from node 410.
  • NAND gate 426 is connected through inverter 429 to capacitor 430.
  • the opposite node at capacitor 430 is connected to node 431.
  • the output of NAND gate 428 is connected through inverter 432 to capacitor 433.
  • the opposite node at capacitor 433 is connected to node 434.
  • a series of n-channel triple well transistors 435, 436 and 437 are connected in diode configurations.
  • Transistor 435 has its anode connected to the supply potential at node 212.
  • the cathode of diode connected transistor 435 is connected to node 431.
  • Node 431 is connected to the anode of diode connected transistor 436, the cathode of which is connected to node 434.
  • Node 434 is also connected to the anode of diode connected transistor 437.
  • the cathode of diode connected transistor 437 is connected to the AVXS node 210.
  • the charge pump illustrated in Fig. 7D is enabled when the control signal VHH is high. Its inputs include the control signal VHH on line 213, and the control signal BCK2 on line 410. These signals are supplied as input to NAND gate 440.
  • the output of NAND gate 440 is connected through inverter 441 through capacitor 442 to the node 443.
  • a diode connected triple well transistor 444 is connected between the supply potential at node 212 and node 443.
  • Node 443 is connected across diode connected triple well transistor 445 to the output node 210 at which the voltage AVXS is generated.
  • the node 210 at which AVXS is supplied loses charge because it is required to charge up the newly selected word line. For example, when a word line, such as WL0 is selected, it is charged up to the AVXS read level, for example about 4.5 volts. All the other word lines WLl-WLN within the word line decoder section, as well as word lines in other word line decoder sections remained at the ground level. If during the next read, another word line such as WL1 is selected, WL1 is charged up to the AVXS level, while word line WL0 is discharged to ground. Thus, the AVXS level is pulled to a lower level when the word line switches. This is illustrated in Fig.
  • the trace 210 corresponds to the signal AVXS
  • the trace 401 corresponds to the ATDX signal
  • the trace 410 corresponds to the control signal BCK2.
  • the word line switches such as at time Tl
  • the voltage at node AVXS drops.
  • the address transition signal is asserted.
  • the signal BCK2 goes high a short time later, at time T2. This results in a pump in the charge of the signal ATDX back up to near its original level.
  • the control signal BCK2 falls, the level ATDX falls slightly, but maintains its level of about 4.5 volts.
  • the read pump of Figs. 7A-7D is designed to achieve this purpose.
  • the signal VHH is used to determine which of the two read pumps, that of Fig. 7C or that of 7D is used. If the signal VDD is lower than the threshold value, then the two stage pump of Fig. 7C is used providing higher pumping capability. However, if the supply potential VHH is high, then the single stage pump with lower pumping capability is used.
  • the pulse BCKl triggered by the address transition detection signal ATDX has a preferred duration of about 15 nanoseconds.
  • the pulse BCK2 is triggered by the falling edge of BCKl, and has a duration of about 20 nanoseconds.
  • a read pump with different numbers of stages can be utilized. Also the duration of the pumping pulses can also be modified. Finally, it is pointed out that if the word lines do not switch for a next read operation, that is the data from the same word line address are to be read in sequence, the AVXS level does not drop significantly. Thus, no additional charge is needed to be supplied. In this case, the ATDX signal is not triggered. This further reduces power dissipation in the on chip voltage supply generator.
  • the read pump in this example includes two stages. More stages could be used for a given embodiment, depending on such factors as the range of VDD and the target value of AVXS.
  • the auxiliary boost pump 53 shown in Fig. 2 is similar in implementation to the read pump, and can be adapted as suits the needs for a particular situation.
  • Conventional boosting methods have a certain limit on the highest word line level which can be achieved. A theoretical maximum is twice the supply potential, and the practical maximum value is about 1.7 times the supply potential. However, if the supply potential is as low as 1.8 volts, the word line level can be boosted only to about 3.0 volts in this case. If a word line level must be at least 3.6 volts for example, the conventional auxiliary boost pump can be utilized to pump the word line level to this higher level after the initial boost.
  • the structure of the auxiliary boost pump is like the read pump. This pumping capability however is smaller since it is only used for incremental increase in word line level after the initial boost. Furthermore, in this example it is only turned on in response to transitions between word line sections.
  • the auxiliary boost pump can be merged with the read pump. In these situations, the ATDX signal is triggered also when the ATDO signal is triggered. That is, the read pump is energized on all address transitions on the row address, rather than just on address transitions within a word line decoder section. This allows the read pump to increase the initial level of the AVXS voltage instead of the auxiliary boost pump.
  • the design parameters of the auxiliary pump are dependent on the boosted level that can be reached by the boost circuit. If the boost circuit alone is able to pull the AVXS node to a voltage level high enough for the read mode, no auxiliary pump is necessary. However, if the boost circuit alone is not enough to reach the desired range, then an auxiliary pump must be used. For example, if the target read mode AVXS range is 4.5 to 5.2 volts, and the power supply voltage is about 2.7 volts, the boost circuit is able to boost the node AVXS to about 4.2 volts. In this case we need the auxiliary pump to supplement the boost circuit so as to pull the final level of AVXS to above 4.5 volts, for example 4.6 volts.
  • the auxiliary pump is able to supply the 0.4 voltage difference in this case. Furthermore, if after each word line switch, the AVXS drops to 3.2 volts, the read pump must be designed to supply at least 1.3 volts of difference. Thus, the read pump cannot be utilized as the auxiliary boost pump, because it would result in charging the AVXS level to a level which is too high as can be determined by adding the 1.3 volt read pump boost to the 4.2 volt boost circuit result. This shows a 5.5 volt value which exceeds the target range of 4.5 to 5.2 volts. In this case, an auxiliary pump is necessary.
  • the read mode pump needs to be designed to pull the node from 4 volts back to about 4.5 volts. This is only a 0.5 volt difference. Consequently, the read pump can be utilized as the auxiliary pump, and still fall within the design target.
  • an on chip voltage supply circuit which is sensitive to the level of the power supply potential, to provide better control over the internal voltage generated, and a reduced power consumption.
  • the invention is particularly suited for the generation of read voltages or other on chip voltages on flash memory devices, where power consumption is a critical design parameter, particularly in systems which are designed for low power supply potentials.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Read Only Memory (AREA)

Abstract

Un circuit de génération de tension sur puce destiné à être utilisé sur des circuits intégrés tels que des dispositifs à mémoire flash avec alimentation basse tension, comprend un circuit de détection (32) sur le circuit intégré qui génère un signal de sortie (31) indiquant un niveau de tension d'alimentation. Le circuit d'alimentation de tension sur puce génère la tension sur puce (30) en réponse au signal de sortie du circuit de détection (32) et la tension d'alimentation. La sortie du circuit de détection (31) indique la valeur de la tension d'alimentation (10), de sorte que le circuit d'alimentation de tension sur puce (29) est capable d'adapter la quantité d'amplification utilisée pour produire la tension sur puce. Le circuit d'alimentation de tension sur puce (29) génère la tension de lignes de mots à un noeud accouplé à des circuits de commande de lignes de mots (20) dans le dispositif.
PCT/US1997/021513 1997-11-21 1997-11-21 Generation de tension sur puce pour circuits integres faible puissance WO1999027537A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/029,945 US6002630A (en) 1997-11-21 1997-11-21 On chip voltage generation for low power integrated circuits
PCT/US1997/021513 WO1999027537A1 (fr) 1997-11-21 1997-11-21 Generation de tension sur puce pour circuits integres faible puissance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1997/021513 WO1999027537A1 (fr) 1997-11-21 1997-11-21 Generation de tension sur puce pour circuits integres faible puissance

Publications (1)

Publication Number Publication Date
WO1999027537A1 true WO1999027537A1 (fr) 1999-06-03

Family

ID=22262127

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/021513 WO1999027537A1 (fr) 1997-11-21 1997-11-21 Generation de tension sur puce pour circuits integres faible puissance

Country Status (1)

Country Link
WO (1) WO1999027537A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001033571A1 (fr) * 1999-10-29 2001-05-10 Advanced Micro Devices, Inc. Poursuite d'une ligne de mots de memoire flash a travers la totalite de la puce
WO2001097230A3 (fr) * 2000-06-13 2002-05-30 Advanced Micro Devices Inc Procede de reduction de la charge capacitive dans un decodeur-x a memoire flash pour la commande precise de la tension sur des lignes de mots et des lignes de selection
WO2003085725A3 (fr) * 2002-04-01 2004-09-10 Intel Corp Approvisionnement de circuits integres dans des alimentations a boitier
WO2008075292A3 (fr) * 2006-12-18 2008-08-21 Nxp Bv Capteur de température de mise sous tension/détection spd

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646902A (en) * 1994-10-20 1997-07-08 Goldstar Electron Co., Ltd. Static random access memory device with low power dissipation
US5663926A (en) * 1995-01-30 1997-09-02 Nec Corporation Semiconductor device having an internal voltage step-up control circuit
US5706240A (en) * 1992-06-30 1998-01-06 Sgs-Thomson Microelectronics S.R.L. Voltage regulator for memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5706240A (en) * 1992-06-30 1998-01-06 Sgs-Thomson Microelectronics S.R.L. Voltage regulator for memory device
US5646902A (en) * 1994-10-20 1997-07-08 Goldstar Electron Co., Ltd. Static random access memory device with low power dissipation
US5663926A (en) * 1995-01-30 1997-09-02 Nec Corporation Semiconductor device having an internal voltage step-up control circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001033571A1 (fr) * 1999-10-29 2001-05-10 Advanced Micro Devices, Inc. Poursuite d'une ligne de mots de memoire flash a travers la totalite de la puce
WO2001097230A3 (fr) * 2000-06-13 2002-05-30 Advanced Micro Devices Inc Procede de reduction de la charge capacitive dans un decodeur-x a memoire flash pour la commande precise de la tension sur des lignes de mots et des lignes de selection
WO2003085725A3 (fr) * 2002-04-01 2004-09-10 Intel Corp Approvisionnement de circuits integres dans des alimentations a boitier
CN100437418C (zh) * 2002-04-01 2008-11-26 英特尔公司 为集成电路提供封装内电源的装置和方法
US7823279B2 (en) 2002-04-01 2010-11-02 Intel Corporation Method for using an in package power supply to supply power to an integrated circuit and to a component
WO2008075292A3 (fr) * 2006-12-18 2008-08-21 Nxp Bv Capteur de température de mise sous tension/détection spd

Similar Documents

Publication Publication Date Title
US6002630A (en) On chip voltage generation for low power integrated circuits
US12002520B2 (en) Voltage generation circuit which is capable of executing high-speed boost operation
JP4094104B2 (ja) 半導体集積回路装置および記憶装置
US6642757B2 (en) Semiconductor memory device having a power-on reset circuit
US6226224B1 (en) Semiconductor integrated circuit device and storage device
US5677643A (en) Potential detecting circuit which suppresses the adverse effects and eliminates dependency of detected potential on power supply potential
US20030123289A1 (en) Nonvolatile semiconductor memory
US6266276B1 (en) Non-volatile semiconductor memory device and internal operation method for said non-volatile semiconductor memory device
US6255900B1 (en) Rapid on chip voltage generation for low power integrated circuits
KR0167872B1 (ko) 반도체장치의 내부전원회로
KR100309602B1 (ko) 전위검출회로에서의전력소비를감소시키는반도체장치
US6735119B2 (en) Nonvolatile semiconductor memory
US7623394B2 (en) High voltage generating device of semiconductor device
US5642313A (en) Voltage booster circuit for a memory device
US6762970B2 (en) Flash memory device
KR19990050472A (ko) 승압전압 발생회로
EP1151365B1 (fr) Generation rapide de tension dans le microcircuit dans le cas de circuits integres courant faible
JP2012226805A (ja) 半導体メモリの内部電源電圧生成回路及び内部電源電圧生成方法
WO1999027537A1 (fr) Generation de tension sur puce pour circuits integres faible puissance
JP4435203B2 (ja) 半導体集積回路装置
JPH1069796A (ja) 高速試験機能付半導体集積回路
JP2916364B2 (ja) 半導体装置の内部電源回路
JP4478170B2 (ja) 半導体集積回路装置
KR950007565Y1 (ko) 저전압작동 반도체메모리의 워드라인 전압 공급회로

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 09029945

Country of ref document: US

AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase