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WO1999031711A2 - Circuit de precharge pour memoire a semiconducteur - Google Patents

Circuit de precharge pour memoire a semiconducteur Download PDF

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Publication number
WO1999031711A2
WO1999031711A2 PCT/KR1998/000430 KR9800430W WO9931711A2 WO 1999031711 A2 WO1999031711 A2 WO 1999031711A2 KR 9800430 W KR9800430 W KR 9800430W WO 9931711 A2 WO9931711 A2 WO 9931711A2
Authority
WO
WIPO (PCT)
Prior art keywords
true
complement
precharge
input
control signal
Prior art date
Application number
PCT/KR1998/000430
Other languages
English (en)
Other versions
WO1999031711A3 (fr
Inventor
Dae-Soon Kim
Original Assignee
Daewoo Electronics Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daewoo Electronics Co., Ltd. filed Critical Daewoo Electronics Co., Ltd.
Publication of WO1999031711A2 publication Critical patent/WO1999031711A2/fr
Publication of WO1999031711A3 publication Critical patent/WO1999031711A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present invention relates to a semiconductor memory device, more particularly, to a precharge circuit of a semiconductor memory device capable of precharging bit lines by using input/output data lines.
  • DRAM dynamic random access memory
  • Such precharge operation is performed by means of a precharge circuit which is connected to a memory cell array.
  • the precharge circuit charges bit lines to a precharge voltage when a prechage operation activating signal is applied thereto.
  • bit lines of a semiconductor memory element are precharged to Vcc/2 at a standby mode. Since data which are stored in a memory cell array are transmitted to bit lines and are sensed and amplified by a sense amplifier at an active mode, the bit lines are converted into a power supply potential Vcc or a ground potential Vss . After data are outputted to an outside of the semiconductor memory element, when the element again changes the standby mode the bit lines at Vcc or Vss are converted into Vcc/2.
  • FIG. 1 shows a conventional precharge circuit of a semiconductor memory device and a peripheral circuit thereof .
  • a plurality of memory cells 100 (only one is shown in FIG. 1) are connected to a word line L and are driven in response to word line drive signals.
  • Each of the memory cells 100 includes a capacitor Cll for storing information and a pass transistor Qll for opening/closing charging and discharging paths of the capacitor Cll.
  • One terminal of the capacitor Cll is connected to a ground Vss.
  • the pass transistor Qll is connected to a pair of bit lines BL and /BL.
  • a plurality of memory cells 100 are connected to the pair of bit lines BL and /BL and other bit lines.
  • the pair of bit lines BL and /BL transmit a data signal which is stored in the memory cell 100 to a pair of input/output data lines DB and /DB through a sense amplifier 102 and a pair of column selecting transistors Q15 and Q16. Also, the pair of bit lines BL and /BL provides a data signal transmitted in the pair of input/output data lines DB and /DB from an outside to the memory cell 100 through the pair of column selecting transistors Q15 and Q16 and the sense amplifier 102.
  • the sense amplifier 102 is connected to the pair of bit lines BL and /BL and senses and amplifies a data signal transmitted on the pair of bit lines BL and /BL from the memory cell 100 and transmits the data signal into a pair of input/output data lines DB and /DB through a pair of column selecting transistors Q15 and Q16.
  • the sense amplifier 102 includes a cross-coupled latch consisting of two PMOS transistors Pll and P12 and two NMOS transistors Nil and N12 coupled between the pair of bit lines BL and /BL.
  • a precharge circuit 104 is connected to the pair of bit lines BL and /BL and precharges and equalizes the pair of bit lines BL and /BL to Vcc/2 level according to a precharge voltage Vcc/2 generated by means of a precharge voltage supply 106.
  • the precharge circuit 104 includes a precharging section 108 and an equalizing NMOS transistor Q14.
  • the precharging section 108 includes two NMOS transistors Q12 and Q13.
  • the precharge voltage supply 106 generates a precharge voltage, that is, Vcc/2, and feeds the Vcc/2 to NMOS transistor Q12 and Q13 of the precharging section through a precharge power line 110.
  • the precharging section 108 charges the pair of bit lines BL and /BL to a precharge voltage Vcc/2 from the precharge voltage supply 106 according to a bit line precharge control signal EQ.
  • the equalizing NMOS transistor Q14 equalizes between the pair of bit lines BL and /BL.
  • the pair of data input/output lines DB and /DB transmits a data signal on the pair of bit lines BL and /BL to an outside through a data input/output buffer (not ⁇ hown) . Also, the pair of data input/output lines DB and /DB transmit a data signal inputted from the outside through data input/output buffer into the pair of bit lines BL and /BL .
  • the pair of column selecting transistors Q15 and Q16 are connected between the pair of bit lines BL and /BL and the pair of data input/output lines DB and /DB .
  • the gates of column selecting transistors Q15 and Q16 are commonly connected to a column selecting signal CAE which is an output signal of a column decoder which is not shown and are controlled by the column selecting signal CAE.
  • a precharge circuit for a semiconductor memory device comprising: true and complement input/output data lines for selectively receiving one of a precharge voltage and a data input/output control signal and precharging true and complement bit lines of the semiconductor memory device or performing a normal information sensing operation in response to the received signal; and true and complement multiplexors for selecting one of the precharge voltage and the data input/output control signal in response to a precharge control signal to transmit to the true and complement input/output data lines.
  • the precharge operation is performed by using data input/output lines without an additive precharge circuit.
  • an area increase due to a precharge circuit can be removed when designing a DRAM to thereby reduce a design area thereof .
  • FIG. 1 is a view for showing a conventional precharge circuit of a semiconductor memory device and a peripheral circuit thereof;
  • FIG. 2 is a view for showing a precharge circuit of a semiconductor memory device and a periphery circuit thereof according to a first embodiment of the present invention.
  • FIG. 3 is a view for showing a precharge circuit of a semiconductor memory device and a- periphery circuit thereof according to a second embodiment of the present invention.
  • input/output lines for transmitting input/output data serve as paths for producing through an output buffer, data read out of a selected memory cell, and commonly serves as paths for supplying external data to a selected memory cell.
  • the input/output lines for transmitting data also are made of a pair of lines corresponding to the pair of bits.
  • one of the lines represents memory cell information, while the other line represents a complement value thereof.
  • FIG. 2 shows a precharge circuit 20 of a semiconductor memory device and a periphery circuit thereof according to a first embodiment of the present invention.
  • a plurality of memory cells 200 (only one is shown in FIG. 2) are connected to a word line WL and are driven in response to word line drive signals.
  • Each of the memory cells 200 includes a capacitor C21 for storing information and a pass transistor Q21 for opening/closing charging and discharging paths of the capacitor C21.
  • One terminal of the capacitor C21 is connected to a ground Vss.
  • the pass transistor Q21 is connected to true and complement bit lines BL and /BL.
  • a plurality of memory cells 200 are connected to the true and complement bit lines BL and /BL and other bit lines.
  • a sense amplifier 202 is connected to the true and complement bit lines BL and /BL and senses and amplifies a data signal transmitted on the true and complement bit lines BL and /BL from the memory cell 200 and transmits the data signal into true and complement input/output data lines DB and /DB through true and complement column selecting transistors Q22 and Q23.
  • the sense amplifier 202 also senses and amplifies a data signal transmitted on the true and complement bit lines BL and /BL from an outside through the complement input/output data lines DB and /DB and the true and complement column selecting transistors Q22 and Q23 and provides the data signal to the memory cell 200.
  • the sense amplifier 202 includes a cross-coupled latch consisting of two PMOS transistors P21 and P22 and two NMOS transistors N21 and N22 coupled between the true and complement bit lines BL and /BL.
  • the precharge circuit 20 of a semiconductor memory device includes true and complement input/output data lines DB and /DB and true and complement multiplexors 203 and 204.
  • the true and complement input/output data lines DB and /DB are connected to the true and complement bit lines BL and /BL through the true and complement column selecting transistors Q22 and Q23.
  • the true and complement input/output data lines DB and /DB receive a precharge voltage Vpr from a precharge voltage supply 201 through true and complement multiplexors 203 and 204 during a precharge operation and transmit the precharge voltage Vpr to the true and complement bit lines BL and /BL. Accordingly, the true and complement bit lines BL and /BL are precharged to the precharge voltage Vpr.
  • the precharge voltage Vpr is Vcc/2 which is 1/2 of the power source potential Vcc.
  • the true and complement input/output data lines DB and /DB transmit a data signal read from the memory cell 200 through true and complement bit lines BL and /BL, a sense amplifier 202, and true and complement column selecting transistors Q22 and Q23 in response to data input/output control signal I/O and /I/O.
  • the true and complement input/output data lines DB and /DB transmit a data signal written from the outside to the memory cell 200 trough the true and complement column selecting transistors Q22 and Q23, the true and complement bit lines BL and /BL, and the sense amplifier 202 in response to data input/output control signals I/O and /I/O.
  • the true and complement input/output data lines DB and /DB selectively receive one of the precharge voltage Vpr and the data input/output control signals I/O and /I/O and precharge the true and complement bit lines BL and /BL or performs a normal information sensing operation including read and writing operations in response to the received signal.
  • the true and complement multiplexors 203 and 204 each includes first input terminals 203a and 204a commonly connected to the precharge voltage source 201.
  • the second input terminals 203b and 204b of the true and complement multiplexors 203 and 204 are connected to true and complement data input/output control signals I/O and /I/O, respectively.
  • the output terminals 203c and 204c of the true and complement multiplexors 203 and 204 are connected to true and complement input/output data lines DB and /DB, respectively.
  • the true and complement multiplexors 203 and 204 select one of the precharge voltage Vpr and the data input/output control signals I/O and /I/O in response to a precharge control signal EQ and the true and complement input/output data lines DB and /DB .
  • the true and complement multiplexors 203 and 204 select the precharge voltage Vpr of the precharge voltage Vpr generated by means of the precharge voltage source 201 and the data input/output control signals I/O and /I/O and transmit the precharge voltage Vpr to the true and complement input/output data lines DB and /DB .
  • the true and complement multiplexors 203 and 204 select the data input/output control signals I/O and /I/O from the precharge voltage Vpr and the data input/output control signals I/O and /I/O and perform a normal information sensing operation including read and writing operations in response to the data input/output control signals I/O and /I/O.
  • the precharge circuit 20 further includes true and complement column selecting transistors Q22 and Q23 connected between the true and complement bit lines BL and /BL and the true and complement input/output data lines DB and /DB for switching a signal between the true and complement bit lines BL and /BL and the true and complement input/output data lines DB and /DB.
  • the true and complement column selecting transistors Q22 and Q23 are controlled by means of a column selecting signal CAE from a column decoder (not shown) and transmit the precharge voltage Vpr transmitted on the true and complement input/output data lines DB and /DB from the precharge voltage source 201 to true and complement bit lines BL and /BL.
  • the true and complement column selecting transistors Q22 and Q23 are controlled by the column selecting signal CAE and transmit the data signal transmitted on the true and complement bit lines BL and /BL from the memory cell 200 to true and complement input/output data lines DB and /DB .
  • the true and complement column selecting transistors Q22 and Q23 are controlled by the column selecting signal CAE and transmit the data signal transmitted on true and complement input/output data lines DB and /DB from the outside to the true and complement bit lines_ BL and /BL.
  • the precharge circuit 20 further includes a metal oxide semiconductor transistor Q24 including a drain electrode and a source electrode coupled between the true and complement input/output data lines DB and /DB and a gate connected to the precharge control signal EQ.
  • the metal oxide semiconductor transistor Q24 equalizes the true and complement input/output data lines DB and /DB.
  • the column selecting signal CAE of a low level is applied to the gate electrodes of the selecting transistors Q22 and Q23 so that the true and complement column selecting transistors Q22 and Q23 are turned-off .
  • a precharge operation with respect to bit lines BL and /BL is completed.
  • true and complement multiplexors 203 and 204 select true and complement data input/output control signals I/O and /I/O and transmit the data input/output control signals I/O and /I/O to the true and complement input/output data lines DB and /DB. Accordingly, a normal information sensing operation is carried.
  • FIG. 3 shows a precharge circuit of a semiconductor memory device and a periphery circuit thereof according to a second embodiment of the present invention.
  • a plurality of memory cells 300 are connected to a word line WL and are driven in response to word line drive signals.
  • Each of the memory cells 300 includes a capacitor C31 for storing information and a pass transistor Q31 for opening/closing charging and discharging paths of the capacitor C31.
  • One terminal of the capacitor C31 is connected to a ground Vss.
  • the pass transistor Q31 is connected to true and complement bit lines BL and /BL.
  • a plurality of memory cells 300 are connected to the true and complement bit lines BL and /BL and other bit lines.
  • a sense amplifier 302 is connected to the true and complement bit lines BL and /BL and senses and amplifies a data signal transmitted on the true and complement bit lines BL and /BL from the memory cell 300 and transmits the data signal into true and complement input/output data lines DB and /DB through true and complement column selecting transistors Q32 and Q33.
  • the sense amplifier 302 also senses and amplifies a data signal transmitted on the true and complement bit lines BL and /BL from an outside through the complement input/output data lines DB and /DB and the true and complement column selecting transistors Q32 and Q33 and provides the data signal to the memory cell 300.
  • the sense amplifier 302 includes a cross-coupled latch consisting of two PMOS transistors P31 and P32 and two NMOS transistors N31 and N32 coupled between the true and complement bit lines BL and /BL.
  • the precharge circuit 30 of a semiconductor memory device includes true and complement input/output data lines DB and /DB and true and complement multiplexors 303 and 304.
  • the true and complement input/output data lines DB and /DB are connected to the true and complement bit lines BL and /BL through the true and complement column selecting transistors Q32 and Q33.
  • the true and complement input/output data lines DB and /DB receive a precharge voltage Vpr from a precharge voltage supply 301 through true and complement multiplexors 303 and 304 during a precharge operation and transmit the precharge voltage Vpr to the true and complement bit lines BL and /BL.
  • the true and complement bit lines BL and /BL are precharged to the precharge voltage Vpr.
  • the precharge voltage Vpr is Vcc/2 which is 1/2 of the power source potential Vcc.
  • the true and complement input/output data lines DB and /DB transmit a data signal read from the memory cell 200 through true and complement bit lines BL and /BL, a sense amplifier 302, and true and complement column selecting transistors Q32 and Q33 in response to data input/output control signal I/O and /I/O.
  • the true and complement input/output data lines DB and /DB transmit a data signal written from the outside to the memory cell 300 trough the true and complement column selecting transistors Q32 and Q33, the true and complement bit lines BL and /BL, and the sense amplifier 302 in response to data input/output control signals I/O and /I/O.
  • the true and complement input/output data lines DB and /DB selectively receive one of the precharge voltage Vpr and the data input/output control signals I/O and /I/O and precharge the true and complement bit lines BL and /BL or performs a normal information sensing operation including read and writing operations in response to the received signal.
  • the true and complement multiplexors 303 and 304 each includes first input terminals 303a and 304a commonly connected to the precharge voltage source 301.
  • the second input terminals 303b and 304b of the true and complement multiplexors 203 and 204 are connected to true and complement data input/output control signals I/O and /I/O, respectively.
  • the output terminals 303c and 304c of the true and complement multiplexors 203 and 204 are connected to true and complement input/output data lines DB and /DB, respectively.
  • the true and complement multiplexors 303 and 304 select one of the precharge voltage Vpr and the data input/output control signals I/O and /I/O in response to a precharge control signal EQ and the true and complement input/output data lines DB and /DB .
  • the true and complement multiplexors 303 and 304 select the precharge voltage Vpr of the precharge voltage Vpr generated by means of the precharge voltage source 301 and the data input/output control signals I/O and /I/O and transmit the precharge voltage Vpr to the true and complement input/output data lines DB and /DB .
  • the true and complement multiplexors 303 and 304 select the data input/output control signals I/O and /I/O from the precharge voltage Vpr and the data input/output control signals I/O and /I/O and perform a normal information sensing operation including read and writing operations in response to the data input/output control signals I/O and /I/O.
  • the precharge circuit 30 further includes true and complement column selecting transistors Q32 and Q33 connected between the true and complement bit lines BL and /BL and the true and complement input/output data lines DB and /DB for switching a signal between the true and complement bit lines BL and /BL and the true and complement input/output data lines DB and /DB.
  • the true and complement column selecting transistors Q32 and Q33 are controlled by means of a column selecting signal CAE from a column decoder (not shown) and transmit the precharge voltage Vpr transmitted on the true and complement input/output data lines DB and /DB from the precharge voltage source 301 to true and complement bit lines BL and /BL.
  • the true and complement column selecting transistors Q32 and Q33 are controlled by the column selecting signal CAE and transmit the data signal transmitted on the true and complement bit lines BL and /BL from the memory cell 200 to true and complement input/output data lines DB and /DB .
  • the true and complement column selecting transistors Q32 and Q33 are controlled by the column selecting signal CAE and transmit the data signal transmitted on true and complement input/output data lines DB and /DB from the outside to the true and complement bit lines BL and /BL.
  • the precharge circuit 30 further includes a metal oxide semiconductor transistor Q34 including a drain electrode and a source electrode coupled between the true and complement input/output data lines DB and /DB and a gate connected to the precharge control signal EQ.
  • the metal oxide semiconductor transistor Q34 equalizes the true and complement input/output data lines DB and /DB.
  • the precharge circuit 30 further includes a precharge NMOS transistor Q35 including a gate electrode for receiving the precharge control signal EQ, a drain electrode connected to the true bit line BL, and a source electrode connected to the complement bit line /BL.
  • a precharge NMOS transistor Q35 including a gate electrode for receiving the precharge control signal EQ, a drain electrode connected to the true bit line BL, and a source electrode connected to the complement bit line /BL.
  • true and complement multiplexors 203 and 204 select a precharge voltage Vcc/2 generated by means of the precharge voltage source 301 and transmit the precharge voltage Vcc/2 to the true and complement input/output data lines DB and /DB . Accordingly, the true and complement input/output data lines DB and /DB are precharged and equalized to the precharge voltage Vcc/2. Also, equalizing NMOS transistor Q34 is turned-on and serves to equalize the true and complement input/output data lines DB and /DB.
  • the precharge NMOS transistor Q35 is turned-on and serves the true and complement bit lines BL and /BL to be precharged at high speed.
  • the column selecting signal CAE of a low level is applied to the gate electrodes of the selecting transistors Q32 and Q33 so that the true and complement column selecting transistors Q22 and Q23 are turned-off.
  • a precharge operation with respect to bit lines BL and /BL is completed.
  • true and complement multiplexors 203 and 204 select true and complement data input/output control signals I/O and /I/O and transmit the data input/output control signals I/O and /I/O to the true and complement input/output data lines DB and /DB . Accordingly, a normal information sensing operation is carried. At this time, the precharge NMOS transistor Q35 is turned off in response to the precharge control signal EQ of the low level.
  • a precharge circuit 30 of FIG. 3 includes a precharge circuit by using data input/output lines and a dummy precharge circuit to which one transistor is added to the precharge circuit so that a precharge operation can be performed at a high speed even if an area increase is attended with.
  • the precharge operation is performed by using data input/output lines without an additive precharge circuit .
  • an area increase due to a precharge circuit can be removed when designing a DRAM to thereby reduce a design area thereof.
  • the present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

L'invention concerne un circuit de précharge destiné à une mémoire à semiconducteur, servant à précharger des lignes de bit au moyen de lignes de données d'entrée/de sortie. Dans le circuit de précharge présenté, des lignes de données d'entrée/de sortie normales et complémentaires reçoivent sélectivement une tension de précharge ou un signal de commande d'entrée/de sortie de données et préchargent les lignes de bits normales et complémentaires de la mémoire à semiconducteur ou exécutent une détection d'informations normale en réaction au signal reçu. Des multiplexeurs normaux et complémentaires sélectionnent la tension de précharge ou le signal de commande d'entrée/de sortie de données en réaction à un signal de commande de précharge, pour émettre vers les lignes de données d'entrée/de sortie normales et complémentaires. Grâce audit circuit de précharge, l'opération de précharge est exécutée au moyen de lignes d'entrée/de sortie de données sans circuit de précharge supplémentaire. Ainsi, on évite une augmentation de surface due à un circuit de précharge lors de la conception d'une mémoire RAM dynamique qui présente donc une surface réduite.
PCT/KR1998/000430 1997-12-17 1998-12-15 Circuit de precharge pour memoire a semiconducteur WO1999031711A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019970069620A KR19990050493A (ko) 1997-12-17 1997-12-17 반도체 메모리 장치용 프리차지 회로
KR1997/69620 1997-12-17

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WO1999031711A2 true WO1999031711A2 (fr) 1999-06-24
WO1999031711A3 WO1999031711A3 (fr) 1999-09-30

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KR0149224B1 (ko) * 1994-10-13 1998-10-01 김광호 반도체 집적장치의 내부전압 승압회로
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WO1999031711A3 (fr) 1999-09-30

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