[go: up one dir, main page]

WO1999031711A3 - Precharge circuit for semiconductor memory device - Google Patents

Precharge circuit for semiconductor memory device Download PDF

Info

Publication number
WO1999031711A3
WO1999031711A3 PCT/KR1998/000430 KR9800430W WO9931711A3 WO 1999031711 A3 WO1999031711 A3 WO 1999031711A3 KR 9800430 W KR9800430 W KR 9800430W WO 9931711 A3 WO9931711 A3 WO 9931711A3
Authority
WO
WIPO (PCT)
Prior art keywords
precharge
precharge circuit
memory device
semiconductor memory
input
Prior art date
Application number
PCT/KR1998/000430
Other languages
French (fr)
Other versions
WO1999031711A2 (en
Inventor
Dae-Soon Kim
Original Assignee
Daewoo Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daewoo Electronics Co Ltd filed Critical Daewoo Electronics Co Ltd
Publication of WO1999031711A2 publication Critical patent/WO1999031711A2/en
Publication of WO1999031711A3 publication Critical patent/WO1999031711A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

A precharge circuit of a semiconductor memory device precharges bit lines by using input/output data lines. In the precharge circuit for a semiconductor memory device, true and complement input/output data lines selectively receives one of a precharge voltage and a data input/output control signal and precharges true and complement bit lines of the semiconductor memory device or performs a normal information sensing operation in response to the received signal. True and complement multiplexors select one of the precharge voltage and the data input/output control signal in response to a precharge control signal to transmit to the true and complement input/output data lines. According to the precharge circuit, since the precharge operation is performed by using data input/output lines without an additive precharge circuit. Thus an area increase due to a precharge circuit can be removed when designing a DRAM to thereby reduce a design area thereof.
PCT/KR1998/000430 1997-12-17 1998-12-15 Precharge circuit for semiconductor memory device WO1999031711A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019970069620A KR19990050493A (en) 1997-12-17 1997-12-17 Precharge Circuit for Semiconductor Memory Devices
KR1997/69620 1997-12-17

Publications (2)

Publication Number Publication Date
WO1999031711A2 WO1999031711A2 (en) 1999-06-24
WO1999031711A3 true WO1999031711A3 (en) 1999-09-30

Family

ID=19527615

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR1998/000430 WO1999031711A2 (en) 1997-12-17 1998-12-15 Precharge circuit for semiconductor memory device

Country Status (2)

Country Link
KR (1) KR19990050493A (en)
WO (1) WO1999031711A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108540124A (en) * 2018-04-16 2018-09-14 电子科技大学 A kind of level shifting circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2294345A (en) * 1994-10-13 1996-04-24 Samsung Electronics Co Ltd Voltage boosting circuit of a semiconductor memory
US5608688A (en) * 1995-10-05 1997-03-04 Lg Semicon Co., Ltd. DRAM having output control circuit
US5636171A (en) * 1994-06-04 1997-06-03 Samsung Electronics Co., Ltd. Semiconductor memory device having low power self refresh and burn-in functions

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636171A (en) * 1994-06-04 1997-06-03 Samsung Electronics Co., Ltd. Semiconductor memory device having low power self refresh and burn-in functions
GB2294345A (en) * 1994-10-13 1996-04-24 Samsung Electronics Co Ltd Voltage boosting circuit of a semiconductor memory
US5608688A (en) * 1995-10-05 1997-03-04 Lg Semicon Co., Ltd. DRAM having output control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108540124A (en) * 2018-04-16 2018-09-14 电子科技大学 A kind of level shifting circuit

Also Published As

Publication number Publication date
KR19990050493A (en) 1999-07-05
WO1999031711A2 (en) 1999-06-24

Similar Documents

Publication Publication Date Title
EP0383080A3 (en) Semiconductor memory device
EP0726577A3 (en) Synchronous dual port RAM
AU1424297A (en) Circuit and method for enabling a function in a multiple memory device module
TW337018B (en) Semiconductor nonvolatile memory device
KR930001226A (en) Sense Amplifiers Perform High-Speed Sensing Operations
EP0401521B1 (en) Semiconductor memory device
KR960025791A (en) Sense amplifier circuit
US5506522A (en) Data input/output line sensing circuit of a semiconductor integrated circuit
TW286404B (en) Semiconductor memory device for reducing operating power consumption amount
KR880014564A (en) Output buffer control circuit for memory device
JP2658768B2 (en) Dynamic RAM
TW331643B (en) Bit line sensor amplifier array for semiconductor memory device
TWI266335B (en) Local input/output line precharge circuit of semiconductor memory device
US5754487A (en) Bit line precharge circuit
US5742185A (en) Data bus drive circuit for semiconductor memory device
KR960025011A (en) Data input / output detection circuit of memory device
WO1999031711A3 (en) Precharge circuit for semiconductor memory device
IE811741L (en) Semiconductor read only memory device
WO2004055821A3 (en) Architecture for high-speed magnetic memories
EP1278198A3 (en) Semiconductor memory device
KR960019307A (en) Semiconductor memory device
WO2003032322A3 (en) Adjustable memory self-timing circuit
US5781041A (en) Sense amplifier with low power in a semiconductor device
JP2557337B2 (en) Semiconductor memory device
KR850008238A (en) Semiconductor memory

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

122 Ep: pct application non-entry in european phase