WO2001053845A1 - A printed circuit assembly with configurable boundary scan paths - Google Patents
A printed circuit assembly with configurable boundary scan paths Download PDFInfo
- Publication number
- WO2001053845A1 WO2001053845A1 PCT/US2001/000923 US0100923W WO0153845A1 WO 2001053845 A1 WO2001053845 A1 WO 2001053845A1 US 0100923 W US0100923 W US 0100923W WO 0153845 A1 WO0153845 A1 WO 0153845A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- test
- boundary scan
- printed circuit
- circuit assembly
- recited
- Prior art date
Links
- 238000012360 testing method Methods 0.000 claims abstract description 115
- 239000000523 sample Substances 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims description 2
- 230000004044 response Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- 238000010998 test method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 9
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 239000012085 test solution Substances 0.000 description 4
- 101100482081 Agrobacterium vitis (strain S4 / ATCC BAA-846) iaaM gene Proteins 0.000 description 3
- 102100029647 Apoptosis-associated speck-like protein containing a CARD Human genes 0.000 description 3
- 101100170834 Arabidopsis thaliana ERDJ3A gene Proteins 0.000 description 3
- 101100110004 Homo sapiens PYCARD gene Proteins 0.000 description 3
- 101100095608 Mus musculus Serinc3 gene Proteins 0.000 description 3
- 101100509792 Oncorhynchus mykiss tck1 gene Proteins 0.000 description 3
- 101150116154 tms1 gene Proteins 0.000 description 3
- 101100125297 Agrobacterium vitis (strain S4 / ATCC BAA-846) iaaH gene Proteins 0.000 description 2
- 101100095600 Mus musculus Serinc1 gene Proteins 0.000 description 2
- 238000007792 addition Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 101150046289 tms2 gene Proteins 0.000 description 2
- 239000013598 vector Substances 0.000 description 2
- 101000640743 Ralstonia solanacearum (strain GMI1000) Tryptophan 2,3-dioxygenase 2 Proteins 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts
Definitions
- FIG. 3 The configuration shown includes two separate single scan paths, each with its own set of test signals (TDI and TDO) and control signals (TMS and TCK) These scan paths may be tested either sequentially or simultaneously
- Figure 1 is a block diagram of an exemplary integrated circuit configured for boundary scan testing
- ICT system 100 upon which a printed circuit assembly with configurable boundary scan paths is tested is shown
- ICT system 100 includes an instrument bay 101 and a test fixture 102
- a fixture interface 103 at the top of instrument bay 101 is configured to electrically couple test fixture 102 to instrument bay 101
- Test fixture 102 includes a plurality of test probes 104 configured to make electrical contact with test points located on printed circuit assembly 200
- Test probes 104 are electrically coupled to fixture interface 103 through fixture wires 105, which are typically arranged as twisted pairs
- a retainer 106 is configured to secure printed circuit assembly 200 m place during testing
- FIG. 8 is a block diagram illustrating an embodiment using switches to configure two parallel shared scan paths into a single scan path
- the embodiment shown mcludes a plurality of IC's 300 configured for boundary scan testing, each including a plurality of boundary scan cells 300, which are monitored through signal pms 320 during testing
- the two separate scan paths share a common TDI input and TDO output Switches 350S enable the two boundary scan paths to be electrically coupled, thus forming a smgle, common boundary scan path
- the separate TMS and TCK signals I e TMS1 and TMS2, TCK1 and TCK2
- test data may be shifted into the boundary scan path through common TDI signal path
- test data may then be shifted through the first path (upper path m the drawing) and then through the second path before exiting the chain through the common TDO signal path
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A printed circuit assembly (PCA) with configurable boundary scan paths. A printed circuit assembly, with a number of integrated circuits configured for boundary scan testing, includes a number of switches. These switches allow multiple boundary scan paths to be combined into a common boundary scan path. The switches can be used to combine scan paths of various configurations, such as multiple independent scan paths and parallel shared scan paths. The type of switches used may include multiplexers, demultiplexers, relays, or other types. The PCA may be tested on automated test equipment (ATE), such as a bed-of-nails in-circuit tester, that is configured to perform boundary scan testing.
Description
TITLE: A PRINTED CIRCUIT ASSEMBLY WITH CONFIGURABLE BOUNDARY SCAN PATHS
BACKGROUND OF THE INVENTION
1 Field of the Invention
This invention relates to the testing of electronic circuits, and more specifically, the use of boundary scan for testing pπnted circuit assemblies
2 Description of the Relevant Art
Boundary scan is one solution to testing integrated circuits with large gate and pm counts As the gate and pm counts of integrated circuits has grown, device-level testing of integrated circuits on printed circuit assemblies (PCA's) has become increasingly difficult, and in many cases is no longer practical Device-level testing involves driving logic stimuli to the inputs of a device, and monitoring the resulting outputs Such testing may require the generation of a very large number of test vectors Despite the difficulty of device-level testing, the need persists for ensuring that the correct devices are mounted upon a printed circuit board in the correct orientation with good solder connections Boundary scan may provide a solution to this problem
Boundary scan testing occurs at the boundary between the core logic of a device and its external pm connections A device configured for boundary scan typically includes boundary scan cells, each of which is located between a signal pm and the core logic of the device A plurality of these boundary scan cells may be connected together to form a boundary scan chain, or path Figure 1 is an illustration of an exemplary integrated circuit (IC) configured for boundary scan testing The IC includes a plurality of boundary scan cells chained together During normal IC operations, data may pass unaffected through the boundary scan cells between the core logic and signal pms During boundary scan test operations, test data may enter the IC through the TDI (Test Data In) pin, and pass through the chain of boundary scan cells, leaving the chip through the TDO (Test Data Out) pm In effect, the chain of boundary scan cells acts as a shift register, as data bits may be shifted from one cell to the next The state of each boundary scan cell may be monitored during scan shifting through those signal pms associated with an output or bi-directional signal For example, during boundary scan testing of the exemplary IC shown m Figure 1 (assuming all pms are bi-directional), the state of each boundary scan cell may be monitored by automated test equipment (ATE) through its associated signal pm as data bits are shifted through the boundary scan path During the shifting of data through the boundary scan path, each cell will typically make several transitions between a logic high level and a logic low level If a defect is present (such as an unsoldered signal pm), the ATE may not detect the expected state for the given cell at a given time, thereby causing a test failure In this manner, a defective signal connection may be detected For input signals, test data may be driven into a boundary scan cell through its associated signal pm, and may be monitored through the TDO pm after shifting it through the scan chain
Often times, boundary scan testing is conducted at a PCA level, wherein a number of boundary scan IC's are mounted upon a printed circuit board (PCB) To this end, longer, board-level scan paths may be created by coupling the TDO output of one boundary scan IC to the TDI input of another on a PCA As boundary scan testing has evolved, several different types of board-level scan paths have come into use Figure 2 is a block diagram ot a
smgle scan path In the drawing, a plurality of boundary scan IC"s are chamed together by coupling TDO outputs to TDI inputs A TMS (Test Mode Select) signal is used to place the chips m a test mode, while the TCK (Test Clock) provides the necessary clock signal for shifting data through the scan chain
Multiple independent scan paths are illustrated m Figure 3 The configuration shown includes two separate single scan paths, each with its own set of test signals (TDI and TDO) and control signals (TMS and TCK) These scan paths may be tested either sequentially or simultaneously
Another popular configuration is parallel shared scan paths, as shown in Figure 4 In this configuration, two separate scan paths share TDI and TDO signal connections Each path has its own TMS and TCK signals Because of the shared TDI and TDO signals, only one scan path may be tested at a given time In general, a large number of scan path configurations are possible, and each configuration provides certain advantages and disadvantages Some configurations may be easier to implement during the design of a printed circuit assembly, but result in greater difficulty m generating test vectors Other configurations may provide simpler test solutions, but result in longer test times or lower test coverage
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a printed circuit assembly (PCA) designed with configurable boundary scan paths In one embodiment, a PCA is designed with a plurality of boundary scan paths, and these paths may be of different configurations Switches are mounted upon the printed circuit assembly m such a manner as to allow the boundary scan paths to be connected together These switches may be used to configure the multiple boundary scan paths into a single common boundary scan path The PCA may undergo boundary scan testing on automated test equipment (ATE), such as a bed-of-nails m-circuit tester During testing, the tester may drive control signals to the UUT (Unit Under Test, l e the PCA being tested) for the purposes of configuring the boundary scan path When the UUT is properly configured, the boundary-scan test may be run
The switches used to configure the boundary scan paths may take on various forms In one embodiment, a plurality of 2-to-l multiplexers and l-to-2 de-multiplexers may be used to configure the boundary scan paths In other embodiments, various other types of switches may be used Control of the switch may be provided by the ATE during testing
Thus, in various embodiments, the configurable boundary scan paths may provide greater flexibility in creating boundary scan test solutions for a PCA upon which they are implemented Since multiple scan path configurations are available, a test engineer may choose among a number of test solutions which enable the greatest test coverage Such test solutions may be easier to implement than those for non-configurable boundary scan paths
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which
Figure 1 (prior art) is a block diagram of an exemplary integrated circuit configured for boundary scan testing,
Figure 2 (prior art) is a block diagram of a single scan path configuration,
Figure 3 (prior art) is a block diagram of a multiple independent scan path configuration,
Figure 4 (prior art) is a block diagram of a parallel shared scan path configuration,
Figure 5 is a drawing of one embodiment of an m-circuit test system upon which boundary scan tests may be performed,
Figure 6 is a drawing of a printed circuit assembly of one embodiment including two independent scan paths with switches for reconfiguring the paths,
Figure 7 is a block diagram illustrating an embodiment using switches to configure two multiple independent scan paths into a common scan path, and
Figure 8 is a block diagram illustrating an embodiment using switches to configure two parallel shared scan paths into a common scan path While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example m the drawings and will herein be described m detail It should be understood, however, that the drawings and description thereto are not intended to limit the invention to the particular form disclosed, but, on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling with the spirit and scoped of the present invention as defined be the appended claims
DETAILED DESCRIPTION OF THE INVENTION
Turning now to Figure 5, one embodiment of a bed-of-nails m-circuit test (ICT) system 100 upon which a printed circuit assembly with configurable boundary scan paths is tested is shown ICT system 100 includes an instrument bay 101 and a test fixture 102 A fixture interface 103 at the top of instrument bay 101 is configured to electrically couple test fixture 102 to instrument bay 101 Test fixture 102 includes a plurality of test probes 104 configured to make electrical contact with test points located on printed circuit assembly 200 Test probes 104 are electrically coupled to fixture interface 103 through fixture wires 105, which are typically arranged as twisted pairs A retainer 106 is configured to secure printed circuit assembly 200 m place during testing
During testing, instrument bay 101 is configured to drive test signals to printed circuit assembly 200 through fixture interface 103, fixture wires 105, and test probes 104 Instrument bay 101 may also receive response signals from printed circuit assembly 200 Signals driven to pπnted circuit assembly (PCA) 200 from instrument bay 101 may include analog and/or digital signals In particular, instrument bay 101 may drive digital signals for boundary scan testing to a test-data m (TDI) node on a PCA, and receive signals from a test-data out (TDO) node of the PCA Instrument bay 101 is configured to determine the pass/fail status for a given test of a PCA Instrument bay 101 is also configured to drive control signals to the PCA under test, such as the TMS (Test Mode Select) and TCK (Test Clock) signals that may be required for boundary scan testing In addition, instrument bay 101 may drive control signals for switch positioning to a PCA having switches for connecting boundary scan paths together
Moving now to Figure 6, a drawing of one embodiment of PCA 200, including two independent scan paths with switches for reconfiguring the paths is shown Integrated circuits (IC's) 300 are mounted upon a printed circuit board (PCB) 250 Each IC 300 is configured for boundary scan testing In the embodiment shown, two independent scan paths are present, as represented by signal lines 400A and 400B respectively (this configuration will be illustrated m more detail with reference to Figure 7) Signal line 450 connects the two independent scan paths via switches 350S m order to form a single, common scan path Switches 350S in this embodiment mclude both multiplexers and demultiplexers When testing with the paths connected, test data is driven to PCA 200
through test point 420TDI, with test data leaving the scan chain through test point 420TDO TMS and TCK control signals are driven to test points 420TMS and 420TCK, respectively These control signals are common to both independent scan paths when they are connected to form a common scan path The individual control signals of each path are connected via switches 350T and internal signal lines Figure 7 is a block diagram illustrating an embodiment using switches to configure two independent scan paths into a smgle scan path In the embodiment shown, IC's 300 are configured for boundary scan testing The scan paths are formed by connecting the tdo output of a given IC 300 to the tdi input of the next IC 300 m the path Two switches 350S and a signal path (represented by a dashed line) may be used to connect the two boundary paths together to form a common boundary scan path Similarly, the separate TMS and TCK signals (l e TMS1 and TMS2, TCK1 and TCK2) may be connected with switches 350T and signal paths when forming a single boundary scan path The types of switches used may mclude multiplexers, demultiplexers, relays, and/or vanous other types of switches
When performing boundary scan testing on the embodiment shown in Figure 7, switch control signals configure switches 350S to connect the two independent scan paths in order to form a common scan path Similarly, switches 350T are configured such that test control signals TMS1 and TCK1 control the entire scan cham With the switches properly configured, test data may be shifted m through the TDI-1 signal path of the first scan chain Each IC 300 includes a plurality of boundary scan cells 330, through which the test data is shifted During shifting, automated test equipment (such as that described m reference to Figure 5) may monitor the state of each boundary scan cell through signal pms 320 Test data may be shifted out of the scan path through the TDO-2 signal path Test results may be determined based on the state of each boundary scan cell during the shifting of test data
Figure 8 is a block diagram illustrating an embodiment using switches to configure two parallel shared scan paths into a single scan path The embodiment shown mcludes a plurality of IC's 300 configured for boundary scan testing, each including a plurality of boundary scan cells 300, which are monitored through signal pms 320 during testing The two separate scan paths share a common TDI input and TDO output Switches 350S enable the two boundary scan paths to be electrically coupled, thus forming a smgle, common boundary scan path Similarly, the separate TMS and TCK signals (I e TMS1 and TMS2, TCK1 and TCK2) may be connected with switches 350T and signal paths when forming a common boundary scan path With the switches properly configured, test data may be shifted into the boundary scan path through common TDI signal path When the switches are configured to form a common scan path, test data may then be shifted through the first path (upper path m the drawing) and then through the second path before exiting the chain through the common TDO signal path
In general, any number of scan paths may be combined to form a common scan path using switches to connect the paths Furthermore, the boundary scan paths which are combined may be of different configurations For example, embodiments are contemplated wherein several independent scan paths may be combined with parallel shared scan paths to form a common boundary scan path Additionally, other scan path configurations not explicitly discussed here may also be combined to form a smgle scan path
While the present invention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not so limited Any variations,
modifications, additions, and improvements to the embodiments described are possible These variations, modifications, additions, and improvements may fall withm the scope of the inventions as detailed withm the following claims
Claims
WHAT IS CLAIMED IS:
A printed circuit assembly comprising a printed circuit board including a plurality of boundary scan signal paths for boundary scan testing, a plurality of integrated circuits mounted upon said pπnted circuit board, said integrated circuits including signal connections to support said boundary scan testing; and at least one switch mounted upon said printed circuit board, wherein said switch is configured to selectively connect one of said plurality of boundary scan signal paths to another of said plurality of boundary scan signal paths to thereby create a common boundary scan signal path
The printed circuit assembly as recited in claim 1 , wherein said printed circuit assembly includes a plurality of test points for testing on automated test equipment (ATE)
The printed circuit assembly as recited in claim 2, wherein said automated test equipment is a bed-of-nails m-circuit tester
The printed circuit assembly as recited in claim 3, wherein a plurality of test points are configured to receive control signals for positioning said switches from said bed-of-nails m-circuit tester
The printed circuit assembly as recited m claim 3, wherein test data input signals are driven to said pπnted circuit assembly by said bed-of-nails m-circuit tester
The printed circuit assembly as recited in claim 3, wherein test data output signals are received by said bed-of-nails m-circuit tester
The printed circuit assembly as recited m claim 1 , wherein said boundary scan signal paths are independent scan paths
The printed circuit assembly as recited in claim 1 , wherein said boundary scan signal paths are shared parallel scan paths
The printed circuit assembly as recited m claim 1 , wherein said switches are multiplexers
The printed circuit assembly as recited m claim 1, wherein said switches are demultiplexers
The printed circuit assembly as recited m claim 1 , wherein said switches are relays
The printed circuit assembly as recited in claim 1 wherein each of said integrated circuits mcludes a signal connection for a test-data in (TDI) signal
The printed circuit assembly as recited m claim 1, wherein each of said integrated circuits includes a signal connection for a test-data out (TDO) signal
The printed circuit assembly as recited in claim 1, wherein each of said integrated circuits mcludes a signal connection for a test clock (TCK) signal
The printed circuit assembly as recited in claim 1 , wherein each of said integrated circuits mcludes a signal connection for a test mode select (TMS) signal
A test system comprising a printed circuit assembly (PCAj, wherein said PCA is a unit under test, said PCA including a printed circuit board having a plurality of test points, and wherein said PCA includes a plurality of boundary scan signal paths and at least one switch mounted upon said printed circuit board, said switch configuied to selectively connect one of said plurality of boundary scan paths to another of said plurality of boundary scan paths in order to create a common boundary scan signal path, a test fixture upon which said PCA is mounted during testing, said test fixture including a plurality of test probes configured to make electrical contact with said test points, an instrument bay configured to drive test signals to said PCA and receive response signals from said PCA during said testing, and a fixture interface for coupling said test fixture to said instrument bay
The test system as recited m claim 16, wherein said instrument bay is further configured to drive control signals to said PCA during said testing
The test system as recited m claim 17, wherein said control signals include signals for controlling said switch
The test system as recited in claim 17, wherein said control signals include a test mode select (TMS) signal
The test system as recited in claim 17, wherein said control signals include a test clock (TCK) signal
The test system as recited m claim 16, wherein said test fixture includes a plurality of wires configured to couple said test probes to said fixture interface
A method of testing a printed circuit assembly (PCA) having a plurality of boundary scan signal paths, the method comprising driving switch control signals to at least one switch, said switch configured to selectively connect one of said plurality of boundary scan signal paths to another of said plurality of boundary scan signal paths in order to create a common boundary scan signal path, dπvmg test control signals to a plurality of integrated circuits, each of said integrated circuits having a plurality of boundary scan cells, driving test data to said printed circuit assembly through a test data input (TDI), shifting said test data through said common boundary scan path, monitoring the state of said boundary scan cells during said shifting, and determining test results based on said state of said boundary scan cells during said shifting
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020027009124A KR20020087931A (en) | 2000-01-21 | 2001-01-12 | A printed circuit assembly with configurable boundary scan paths |
| JP2001554079A JP2003520967A (en) | 2000-01-21 | 2001-01-12 | Printed circuit assembly with configurable boundary scan path |
| AU2001232778A AU2001232778A1 (en) | 2000-01-21 | 2001-01-12 | A printed circuit assembly with configurable boundary scan paths |
| EP01904832A EP1248953A1 (en) | 2000-01-21 | 2001-01-12 | A printed circuit assembly with configurable boundary scan paths |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US48906000A | 2000-01-21 | 2000-01-21 | |
| US09/489,060 | 2000-01-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2001053845A1 true WO2001053845A1 (en) | 2001-07-26 |
Family
ID=23942238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2001/000923 WO2001053845A1 (en) | 2000-01-21 | 2001-01-12 | A printed circuit assembly with configurable boundary scan paths |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1248953A1 (en) |
| JP (1) | JP2003520967A (en) |
| KR (1) | KR20020087931A (en) |
| AU (1) | AU2001232778A1 (en) |
| WO (1) | WO2001053845A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1326082A1 (en) * | 2001-12-27 | 2003-07-09 | Infineon Technologies AG | Integrated circuit with configurable scan path |
| DE10238578B4 (en) * | 2001-09-04 | 2010-08-26 | Verigy (Singapore) Pte. Ltd. | Bandwidth adaptation for scan setups in an integrated circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101222737B1 (en) * | 2010-09-27 | 2013-01-15 | 삼성전기주식회사 | Boundary scan testing apparatus for embedded-type substrate and method thereof |
| ES2909189T3 (en) | 2017-12-22 | 2022-05-05 | Lvmh Rech | Oil-in-water emulsion cosmetic |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5581565A (en) * | 1993-12-01 | 1996-12-03 | U.S. Philips Corporation | Measuring apparatus used for testing connections between at least two subassemblies |
-
2001
- 2001-01-12 KR KR1020027009124A patent/KR20020087931A/en not_active Withdrawn
- 2001-01-12 JP JP2001554079A patent/JP2003520967A/en active Pending
- 2001-01-12 AU AU2001232778A patent/AU2001232778A1/en not_active Abandoned
- 2001-01-12 WO PCT/US2001/000923 patent/WO2001053845A1/en not_active Application Discontinuation
- 2001-01-12 EP EP01904832A patent/EP1248953A1/en not_active Withdrawn
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5581565A (en) * | 1993-12-01 | 1996-12-03 | U.S. Philips Corporation | Measuring apparatus used for testing connections between at least two subassemblies |
Non-Patent Citations (2)
| Title |
|---|
| "SN54ACT8997, SN74ACT8997 SCAN PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCENTRATORS", TEXAS INSTRUMENTS, DALLAS, TEXAS, December 1996 (1996-12-01), pages 1 - 24, XP002166813 * |
| MOORE T J: "A WORKSTATION ENVIRONMENT FOR BOUNDARY SCAN INTERCONNECT TESTING", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE,US,NEW YORK, IEEE, 1991, pages 1096 - 1103, XP000272352, ISBN: 0-8186-9156-5 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10238578B4 (en) * | 2001-09-04 | 2010-08-26 | Verigy (Singapore) Pte. Ltd. | Bandwidth adaptation for scan setups in an integrated circuit |
| EP1326082A1 (en) * | 2001-12-27 | 2003-07-09 | Infineon Technologies AG | Integrated circuit with configurable scan path |
Also Published As
| Publication number | Publication date |
|---|---|
| AU2001232778A1 (en) | 2001-07-31 |
| EP1248953A1 (en) | 2002-10-16 |
| KR20020087931A (en) | 2002-11-23 |
| JP2003520967A (en) | 2003-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7171600B2 (en) | Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device | |
| US5270642A (en) | Partitioned boundary-scan testing for the reduction of testing-induced damage | |
| US4812678A (en) | Easily testable semiconductor LSI device | |
| US7661048B2 (en) | Apparatus and method for embedded boundary scan testing | |
| US7977959B2 (en) | Method and apparatus for testing devices using serially controlled intelligent switches | |
| US5487074A (en) | Boundary scan testing using clocked signal | |
| US20040068675A1 (en) | Circuit board having boundary scan self-testing function | |
| US5621740A (en) | Output pad circuit for detecting short faults in integrated circuits | |
| US6862705B1 (en) | System and method for testing high pin count electronic devices using a test board with test channels | |
| KR102797672B1 (en) | Burn in board test device and system | |
| KR19980064249A (en) | VAT instruction decode test register and its test method | |
| EP1358498B1 (en) | Input/output continuity test mode circuit | |
| US20040165071A1 (en) | Boundary scan device | |
| US6519728B2 (en) | Semiconductor integrated circuit having test circuit | |
| EP1248953A1 (en) | A printed circuit assembly with configurable boundary scan paths | |
| US6865703B2 (en) | Scan test system for semiconductor device | |
| EP1149297A1 (en) | A scan test point observation system and method | |
| JPH07159483A (en) | Integrated circuit device and test method thereof | |
| JPH06213972A (en) | Boundary lease cancel circuit, boundary scan test circuit and method of using the same | |
| KR100669073B1 (en) | Boundary scan method with package options | |
| JP3588052B2 (en) | Boundary scan test circuit | |
| KR20060095283A (en) | Cable Delay Failure Test Controller for System-on-Chip with Multiple System Clocks and Heterogeneous Cores | |
| JP3586972B2 (en) | Semiconductor integrated circuit and test method therefor | |
| KR20040057495A (en) | Test board system and JTAG test method of BUMP type by input/output signal distribution | |
| Gericota et al. | Programmable logic devices: A test approach for the input/output blocks and pad-to-pin interconnections |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
| DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
| WWE | Wipo information: entry into national phase |
Ref document number: 2001904832 Country of ref document: EP |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 1020027009124 Country of ref document: KR |
|
| ENP | Entry into the national phase |
Ref country code: JP Ref document number: 2001 554079 Kind code of ref document: A Format of ref document f/p: F |
|
| WWP | Wipo information: published in national office |
Ref document number: 2001904832 Country of ref document: EP |
|
| WWP | Wipo information: published in national office |
Ref document number: 1020027009124 Country of ref document: KR |
|
| REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
| WWW | Wipo information: withdrawn in national office |
Ref document number: 2001904832 Country of ref document: EP |