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WO2001099167A3 - Memory device including nanoclusters and method for manufacture - Google Patents

Memory device including nanoclusters and method for manufacture Download PDF

Info

Publication number
WO2001099167A3
WO2001099167A3 PCT/US2001/016585 US0116585W WO0199167A3 WO 2001099167 A3 WO2001099167 A3 WO 2001099167A3 US 0116585 W US0116585 W US 0116585W WO 0199167 A3 WO0199167 A3 WO 0199167A3
Authority
WO
WIPO (PCT)
Prior art keywords
nanoclusters
dielectric layer
tunnel dielectric
layer
formation
Prior art date
Application number
PCT/US2001/016585
Other languages
French (fr)
Other versions
WO2001099167A2 (en
Inventor
Sucharita Madhukar
Ramachandran Muralidhar
David L O'meara
Hsing H Tseng
Bruce E White
Michael A Sadd
Sufi Zafar
Bich-Yen Nguyen
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2001263370A priority Critical patent/AU2001263370A1/en
Publication of WO2001099167A2 publication Critical patent/WO2001099167A2/en
Publication of WO2001099167A3 publication Critical patent/WO2001099167A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). Such growth is facilitated by formation of a nitrogen-containing layer (502), which may be nitride, overlying the tunnel dielectric layer (14). Selected portions of the nitrogen-containing layer (502) may be removed to aid in controlling where nanoclusters are formed. The growth of the nanoclusters may also be facilitated by treating the surface of the tunnel dielectric layer (14) to alter the bonding structure of the tunnel dielectric layer. After formation of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). A gate electrode (24) is then formed over the control dielectric, and portions of the control dielectric layer (20), the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).
PCT/US2001/016585 2000-06-16 2001-05-23 Memory device including nanoclusters and method for manufacture WO2001099167A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001263370A AU2001263370A1 (en) 2000-06-16 2001-05-23 Memory device including nanoclusters and method for manufacture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59583000A 2000-06-16 2000-06-16
US09/595,830 2000-06-16

Publications (2)

Publication Number Publication Date
WO2001099167A2 WO2001099167A2 (en) 2001-12-27
WO2001099167A3 true WO2001099167A3 (en) 2002-04-04

Family

ID=24384850

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/016585 WO2001099167A2 (en) 2000-06-16 2001-05-23 Memory device including nanoclusters and method for manufacture

Country Status (3)

Country Link
AU (1) AU2001263370A1 (en)
TW (1) TW494572B (en)
WO (1) WO2001099167A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100601943B1 (en) * 2004-03-04 2006-07-14 삼성전자주식회사 Method for manufacturing a memory device having a gate containing evenly distributed silicon nano dots
US7361567B2 (en) * 2005-01-26 2008-04-22 Freescale Semiconductor, Inc. Non-volatile nanocrystal memory and method therefor
WO2010023575A1 (en) * 2008-08-26 2010-03-04 Nxp B.V. A capacitor and a method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11111869A (en) * 1997-10-03 1999-04-23 Sharp Corp Semiconductor storage element
JPH11330273A (en) * 1998-05-08 1999-11-30 Toshiba Corp Semiconductor element
EP0971416A1 (en) * 1998-01-26 2000-01-12 Sony Corporation Memory device and method of manufacturing the same, and integrated circuit and method of manufacturing semiconductor device
US6060743A (en) * 1997-05-21 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same
US6140181A (en) * 1997-11-13 2000-10-31 Micron Technology, Inc. Memory using insulator traps

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060743A (en) * 1997-05-21 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same
JPH11111869A (en) * 1997-10-03 1999-04-23 Sharp Corp Semiconductor storage element
US6140181A (en) * 1997-11-13 2000-10-31 Micron Technology, Inc. Memory using insulator traps
EP0971416A1 (en) * 1998-01-26 2000-01-12 Sony Corporation Memory device and method of manufacturing the same, and integrated circuit and method of manufacturing semiconductor device
JPH11330273A (en) * 1998-05-08 1999-11-30 Toshiba Corp Semiconductor element
US6208000B1 (en) * 1998-05-08 2001-03-27 Kabushiki Kaisha Toshiba Semiconductor element having charge accumulating layer under gate electrode and using single electron phenomenon

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 09 30 July 1999 (1999-07-30) *

Also Published As

Publication number Publication date
WO2001099167A2 (en) 2001-12-27
AU2001263370A1 (en) 2002-01-02
TW494572B (en) 2002-07-11

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