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WO2001099169A3 - Systeme de couche d'arret de gravure - Google Patents

Systeme de couche d'arret de gravure Download PDF

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Publication number
WO2001099169A3
WO2001099169A3 PCT/US2001/019613 US0119613W WO0199169A3 WO 2001099169 A3 WO2001099169 A3 WO 2001099169A3 US 0119613 W US0119613 W US 0119613W WO 0199169 A3 WO0199169 A3 WO 0199169A3
Authority
WO
WIPO (PCT)
Prior art keywords
etch
stop layer
etch stop
layer system
sige
Prior art date
Application number
PCT/US2001/019613
Other languages
English (en)
Other versions
WO2001099169A2 (fr
Inventor
Kenneth C Wu
Eugene A Fitzgerald
Jeffrey T Borenstein
Gianna Taraschi
Original Assignee
Massachusetts Inst Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/599,260 external-priority patent/US6689211B1/en
Application filed by Massachusetts Inst Technology filed Critical Massachusetts Inst Technology
Priority to AU2001268577A priority Critical patent/AU2001268577A1/en
Priority to JP2002503924A priority patent/JP2003536273A/ja
Priority to EP01946546A priority patent/EP1295319A2/fr
Publication of WO2001099169A2 publication Critical patent/WO2001099169A2/fr
Publication of WO2001099169A3 publication Critical patent/WO2001099169A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un système de matériau d'arrêt de gravure monocristallin SiGe sur un substrat de silicium monocristallin. La composition exacte dudit système de matériau d'arrêt de gravure peut varier, celui-ci étant constitué d'un alliage dopé ou non dopé Si1-xGex, et x étant en général compris entre 0,2 et 0,5. Dans son épaisseur, le matériau d'arrêt de gravure comprend une composition uniforme. Le matériau d'arrêt de gravure s'utilise dans le micro-usinage à l'aide d'agents de gravure aqueux anisotropes de silicium tels que l'hydroxyde de potassium, l'hydroxyde de sodium, l'hydroxide de lithium, l'éthylènediamine/pyrocatéchol/pyrazine (EDP), TMAH, et l'hydrazine. Ces solutions permettent en général de graver un silicium quelconque contenant moins de 7x1019 cm-3 d'alliages de bore ou de Si¿1-x?Gex non dopé, x étant approximativement inférieur à 18. Le silicium d'alliage avec des concentrations modérées de germanium permet d'obtenir d'excellentes sélectivités de gravure, c'est-à-dire des différences de vitesse de gravure par rapport au silicium pur non dopé. Ceci est attribué à la modification de la structure de la bande d'énergie par l'addition de germanium. De plus, le dopage non dégénéré de l'alliage Si1-xGex ne doit pas affecter le comportement du matériau d'arrêt de gravure. Le système d'arrêt de gravure de l'invention comprend l'utilisation d'un tampon à composition classée entre le substrat de silicium et le matériau d'arrêt de gravure SiGe. Le tampon possède essentiellement une composition changeant linéairement par rapport à l'épaisseur, du silicium pur à l'interface substrat/tampon à une composition de germanium et, éventuellement, de dopant, à l'interface tampon/arrêt de gravure, avec une possibilité de gravure à une vitesse appréciable. Dans le cas présent, l'augmentation stratégique de germanium et de la concentration du côté tampon de l'interface au matériau d'arrêt de gravure permet d'obtenir une couche d'arrêt de gravure nettement plus résistante à l'agent de gravure. Ce processus et la structure de la couche permettent d'utiliser toute une gamme de nouveaux matériaux de microélectronique. Les capacités d'arrêt de gravure introduisent de nouveaux processus et structures tels que les alliages SiGe relaxés sur Si, SiO2, et SiO2/Si. Ces matériaux peuvent être utilisés dans les futurs dispositifs et circuits Si MOSFET contraints.
PCT/US2001/019613 2000-06-22 2001-06-20 Systeme de couche d'arret de gravure WO2001099169A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2001268577A AU2001268577A1 (en) 2000-06-22 2001-06-20 Etch stop layer system
JP2002503924A JP2003536273A (ja) 2000-06-22 2001-06-20 エッチング阻止層システム
EP01946546A EP1295319A2 (fr) 2000-06-22 2001-06-20 Systeme de couche d'arret de gravure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/599,260 2000-06-22
US09/599,260 US6689211B1 (en) 1999-04-09 2000-06-22 Etch stop layer system

Publications (2)

Publication Number Publication Date
WO2001099169A2 WO2001099169A2 (fr) 2001-12-27
WO2001099169A3 true WO2001099169A3 (fr) 2002-04-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/019613 WO2001099169A2 (fr) 2000-06-22 2001-06-20 Systeme de couche d'arret de gravure

Country Status (4)

Country Link
EP (1) EP1295319A2 (fr)
JP (1) JP2003536273A (fr)
AU (1) AU2001268577A1 (fr)
WO (1) WO2001099169A2 (fr)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6864115B2 (en) 2000-01-20 2005-03-08 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6881632B2 (en) 2000-12-04 2005-04-19 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
US7049627B2 (en) 2002-08-23 2006-05-23 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US7250359B2 (en) 1997-06-24 2007-07-31 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US7256142B2 (en) 2001-03-02 2007-08-14 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7259108B2 (en) 2002-03-14 2007-08-21 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US7307273B2 (en) 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7332417B2 (en) 2003-01-27 2008-02-19 Amberwave Systems Corporation Semiconductor structures with structural homogeneity
US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7348259B2 (en) 2001-04-04 2008-03-25 Massachusetts Institute Of Technology Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7465619B2 (en) 2001-08-09 2008-12-16 Amberwave Systems Corporation Methods of fabricating dual layer semiconductor devices
US7594967B2 (en) 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy

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US6750130B1 (en) 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6969875B2 (en) 2000-05-26 2005-11-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
DE60125952T2 (de) 2000-08-16 2007-08-02 Massachusetts Institute Of Technology, Cambridge Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6593641B1 (en) 2001-03-02 2003-07-15 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
EP1364411A1 (fr) * 2001-03-02 2003-11-26 Amberwave Systems Corporation Plate-forme de silicium germanium relachee pour electronique cmos tres rapide et circuits analogiques tres rapides
US6900103B2 (en) 2001-03-02 2005-05-31 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6855649B2 (en) * 2001-06-12 2005-02-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6900094B2 (en) 2001-06-14 2005-05-31 Amberwave Systems Corporation Method of selective removal of SiGe alloys
US7301180B2 (en) 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
WO2003001607A1 (fr) 2001-06-21 2003-01-03 Massachusetts Institute Of Technology Mosfets a couches semi-conductrices contraintes
US6730551B2 (en) 2001-08-06 2004-05-04 Massachusetts Institute Of Technology Formation of planar strained layers
US7138649B2 (en) 2001-08-09 2006-11-21 Amberwave Systems Corporation Dual-channel CMOS transistors with differentially strained channels
US6933518B2 (en) 2001-09-24 2005-08-23 Amberwave Systems Corporation RF circuits including transistors having strained material layers
US6649492B2 (en) * 2002-02-11 2003-11-18 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
US7615829B2 (en) 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7138310B2 (en) 2002-06-07 2006-11-21 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
AU2003247513A1 (en) 2002-06-10 2003-12-22 Amberwave Systems Corporation Growing source and drain elements by selecive epitaxy
US6982474B2 (en) 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
FR2842350B1 (fr) * 2002-07-09 2005-05-13 Procede de transfert d'une couche de materiau semiconducteur contraint
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
FR2842349B1 (fr) 2002-07-09 2005-02-18 Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon
US7018910B2 (en) 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
US7781850B2 (en) * 2002-09-20 2010-08-24 Qualcomm Mems Technologies, Inc. Controlling electromechanical behavior of structures within a microelectromechanical systems device
DE10260860B4 (de) * 2002-12-23 2008-07-10 Robert Bosch Gmbh Schicht aus Si1-xGex, Verfahren zu deren Herstellung und mikromechanisches Bauelement damit
US6808953B2 (en) * 2002-12-31 2004-10-26 Robert Bosch Gmbh Gap tuning for surface micromachined structures in an epitaxial reactor
WO2004081982A2 (fr) 2003-03-07 2004-09-23 Amberwave Systems Corporation Procede d'isolation par tranchee peu profonde
US7176041B2 (en) * 2003-07-01 2007-02-13 Samsung Electronics Co., Ltd. PAA-based etchant, methods of using same, and resultant structures
US7495266B2 (en) 2004-06-16 2009-02-24 Massachusetts Institute Of Technology Strained silicon-on-silicon by wafer bonding and layer transfer
TWI283442B (en) * 2004-09-09 2007-07-01 Sez Ag Method for selective etching
FR2892733B1 (fr) 2005-10-28 2008-02-01 Soitec Silicon On Insulator Relaxation de couches
US7705370B2 (en) 2005-11-01 2010-04-27 Massachusetts Institute Of Technology Monolithically integrated photodetectors
US8063397B2 (en) 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
DE102010042570B4 (de) 2010-10-18 2012-07-26 Jörg Funke Falt- und teilweise zerlegbares Fahrrad
US9093478B1 (en) 2014-04-11 2015-07-28 International Business Machines Corporation Integrated circuit structure with bulk silicon FinFET and methods of forming
US9842913B1 (en) 2016-05-18 2017-12-12 Globalfoundries Inc. Integrated circuit fabrication with boron etch-stop layer
FR3064398B1 (fr) * 2017-03-21 2019-06-07 Soitec Structure de type semi-conducteur sur isolant, notamment pour un capteur d'image de type face avant, et procede de fabrication d'une telle structure
JP7668626B2 (ja) * 2019-10-04 2025-04-25 東京応化工業株式会社 エッチング液、及び半導体素子の製造方法
FR3125631B1 (fr) * 2021-07-23 2025-01-31 Commissariat Energie Atomique Procede de fabrication d’un substrat semi-conducteur sur isolant de type soi ou sigeoi par besoi et structure pour fabriquer un tel substrat
JP2024160726A (ja) * 2023-05-02 2024-11-15 株式会社Ｓｃｒｅｅｎホールディングス 基板処理方法

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7250359B2 (en) 1997-06-24 2007-07-31 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6864115B2 (en) 2000-01-20 2005-03-08 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6881632B2 (en) 2000-12-04 2005-04-19 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
US7501351B2 (en) 2001-03-02 2009-03-10 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7256142B2 (en) 2001-03-02 2007-08-14 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7348259B2 (en) 2001-04-04 2008-03-25 Massachusetts Institute Of Technology Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers
US7465619B2 (en) 2001-08-09 2008-12-16 Amberwave Systems Corporation Methods of fabricating dual layer semiconductor devices
US7259108B2 (en) 2002-03-14 2007-08-21 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US7307273B2 (en) 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7375385B2 (en) 2002-08-23 2008-05-20 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups
US7368308B2 (en) 2002-08-23 2008-05-06 Amberwave Systems Corporation Methods of fabricating semiconductor heterostructures
US7049627B2 (en) 2002-08-23 2006-05-23 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US7594967B2 (en) 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
US7332417B2 (en) 2003-01-27 2008-02-19 Amberwave Systems Corporation Semiconductor structures with structural homogeneity
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures

Also Published As

Publication number Publication date
AU2001268577A1 (en) 2002-01-02
WO2001099169A2 (fr) 2001-12-27
EP1295319A2 (fr) 2003-03-26
JP2003536273A (ja) 2003-12-02

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