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WO2002041369A2 - Planarisation par polissage électrolytique et traitement chimio-mécanique - Google Patents

Planarisation par polissage électrolytique et traitement chimio-mécanique Download PDF

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Publication number
WO2002041369A2
WO2002041369A2 PCT/US2001/043368 US0143368W WO0241369A2 WO 2002041369 A2 WO2002041369 A2 WO 2002041369A2 US 0143368 W US0143368 W US 0143368W WO 0241369 A2 WO0241369 A2 WO 0241369A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
electropolishing
polishing pad
polishing
electrolyte
Prior art date
Application number
PCT/US2001/043368
Other languages
English (en)
Other versions
WO2002041369A3 (fr
Inventor
Gautam Banerjee
Lee Melbourne Cook
Original Assignee
Rodel Holdings, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rodel Holdings, Inc. filed Critical Rodel Holdings, Inc.
Publication of WO2002041369A2 publication Critical patent/WO2002041369A2/fr
Publication of WO2002041369A3 publication Critical patent/WO2002041369A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23H—WORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
    • B23H5/00—Combined machining
    • B23H5/06—Electrochemical machining combined with mechanical working, e.g. grinding or honing
    • B23H5/08—Electrolytic grinding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/046—Lapping machines or devices; Accessories designed for working plane surfaces using electric current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/16—Polishing
    • C25F3/30—Polishing of semiconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Definitions

  • Electropolishing and Chemical Mechanical Planarization The invention relates to a method for planarization of a substrate by a combination of electropolishing and chemical mechanical planarization, CMP.
  • a semiconductor substrate comprises, a silicon wafer on which is deposited successive layers of materials.
  • a dielectric layer is deposited, and is provided with multiple trenches that are recessed in the dielectric layer.
  • a thin barrier film for example, tantalum, tantalum nitride or a tantalum alloy, is deposited to cover the surface of the dielectric layer including the trenches, which provides a barrier to migration of metal ions into the dielectric layer.
  • a metal layer is deposited to fill the trenches with metal to provide electrical circuit interconnects in the trenches.
  • the substrate is polished by a rotating polishing pad and a polishing fluid at an interface of the substrate and the polishing pad.
  • the polishing operation removes metal by a combination of, abrasion applied by the polishing pad, and chemical reaction of the metal with the polishing fluid.
  • a single step polishing operation, or two step polishing operations, may be performed to provide complete removal of the metal layer, and complete removal of the barrier film, without spots of residual metal on the polished surface, while leaving all of the trenches filled with metal at a level that is planar with the smooth planar polished surface.
  • 6,056,864 discloses removing metal from a metal layer on a semiconductor substrate by dissolving ions of the metal into an electopolishing electrolyte, followed by performing CMP to remove a remaining thickness of metal. A faster rate of removal of the metal is attained as compared to that attained solely by peforming CMP.
  • an apparatus comprises both an electropolishing apparatus and a CMP apparatus.
  • an electropolishing electrolyte comprises a CMP polishing composition. According to an embodiment of the invention, performance of both electropolishing and CMP on the same apparatus leads to a significant reduction in processing time per substrate.
  • Figure 1 is a cross section view of a portion of a semiconductor substrate having a dielectric layer provided with multiple trenches, one of which is shown;
  • Figure 2 is a view similar to Fig. 1 with the substrate having a deposited metal layer to fill each of the trenches with metal;
  • Figure 3 is a view similar to Fig. 2 with a reduced thickness of the metal layer obtained by electropolishing;
  • Figure 6 is a diagrammatic view of an apparatus that is both an electropolishing apparatus and a CMP apparatus;
  • Figure 7 is a graph of weight loss of copper metal versus time of electropolishing with an electropolishing electrolyte comprising a CMP slurry
  • Figure 8 is a graph of removed thickness of copper metal versus time of electropolishing with an electropolishing electrolyte comprising a CMP slurry.
  • Fig. 1 discloses a trench 10 that is etched or otherwise formed in a dielectric layer 11, typically SiO . The trench is then coated with an adhesion or barrier layer 12, as shown in Figure 2, followed by a metal layer 13 which fills the trench 10 with metal.
  • Fig. 3 discloses a reduced thickness 14 of the metal layer 13 obtained by electropolishing.
  • Fig. 5 discloses an electropolishing apparatus 20 according to which multiple substrates 22 are placed in a tank 24 filled with electrolyte 26.
  • the substrates 22 are connected to the positive side of a DC voltage source 28 so that the wafers act as anodes.
  • the negative side of the DC voltage source 28 is connected to a chemically inert electrode 30 that acts as a cathode.
  • the voltage source 28 applies a DC voltage across the anodes and the cathode.
  • a DC electrical current flows through the electrolyte, causing removal of ions of the metal from the substrates 22 and into solution with the electrolyte.
  • the DC voltage source 28 produces the required current density for the metal layer to be reduced in thickness faster than by performing CMP.
  • the electropolishing apparatus 20 is incapable of providing a planar polished surface on the substrates 22. Accordingly, the substrates 22 are removed from the electropolishing apparatus 20, and the polished surface is provided on a CMP apparatus, not shown. Because removal and transfer of the substrates 22 consumes time, the processing time for each substrate 22 is extended.
  • Fig. 6 discloses an apparatus that comprises both an electropolishing apparatus and a CMP apparatus.
  • Each semiconductor substrate 22 that is mounted to the apparatus for electropolishing and CMP serves as an anode by having a conducting portion thereof being connected to a positive side of a DC voltage source 28.
  • a cathode is provided by a conducting portion of a polishing pad 30 connected to a negative side of the DC voltage source 28.
  • Electrolyte 26 is applied by a dispenser 27 at the interface of the substrate and the polishing pad 30.
  • the substrate 22 is held by an electrically insulating holder, and is positioned in close proximity to the conducting portion of the polishing pad 30, while maintaining adequate separation between the same to allow for electrolyte flow.
  • a voltage applied by the voltage source 28 generates a current flow through the known electropolishing electrolyte, which causes the metal of the metal layer on each respective substrate to dissolve in the electrolyte.
  • An advantage of the invention is that, the polishing pad 30 itself will pool the electrolyte about the substrate 22 without requiring immersion in a tank, such as, the tank 24. Electropolishing is performed until substantial reduction of the thickness 24 of the metal layer 15 is attained for each substrate 22 being polished.
  • the removal rate of the metal layer 15 is faster than that resulting from CMP, even while the apparatus of Fig. 6 is not operating to perform CMP during electropolishing.
  • the removal rate of the metal layer 15 is faster while the apparatus of Fig. 6, according to another embodiment thereof, performs CMP during electropolishing.
  • a nonconducting portion of the polishing pad 30 contacts the substrate, especially when the nonconducting portion is a polishing surface of the polishing pad 30, which spaces the conducting portion of the polishing pad 30 away from the substrate 22.
  • the conducting portion of the polishing pad 30 is recessed away from the polishing surface, and is spaced away from the substrate 22 in contact with the polishing surface.
  • a further embodiment of the electrolyte comprises a chemical composition for performance of CMP, as well as, for performance of electropolishing.
  • the removal rate of the metal layer 15 is faster than that resulting from CMP solely. Further, by combining both electropolishing and CMP, the removal rate of the metal layer 15 is faster than that resulting from either electropolishing solely or CMP solely.
  • the apparatus of Fig. 6 operates solely to perform CMP.
  • Metal is removed by abrasion applied by the polishing pad and by chemical reaction with the electrolyte that comprises a CMP polishing composition.
  • the CMP operation without electropolishing provides a smooth, planar polished surface on the substrate that is unattainable by performing electropolishing.
  • dishing refers to unwanted recesses in the metal in the trenches, which are considered as damage to the circuit interconnects.
  • CMP without electropolishing is performed by having the DC voltage source turned off.
  • the DC voltage source is reversible in polarity.
  • the current direction is reversed relative to electropolishing, which clears away charged contaminants from the metal layer 15 during CMP. Any metal ions that tend to plate onto the metal layer 15 are removed by CMP.
  • CMP is then performed in the presence of the applied electrical field at a downforce of up to about 10 psi to obtain a planar surface.
  • the applied voltage difference will be of such low magnitude as to prevent local hot spots and corrosion on the substrate surface.
  • CMP is performed simultaneously with electropolishing, when an electropolishing electrolyte further comprises a CMP polishing compositon.
  • a CMP polishing composition comprises, a metal complexing agent, a metal oxidizing agent and/or a metal corrosion inhibitor.
  • Exemplary complexing agents comprise, mono- and dicarboxylic aliphatic or aromatic acids and their salts such as malic acid, malates, tartaric acid and tartarates, gluconic acid and gluoconates, citric acid and citrates, malonic acid and malonates, formic acid and formates, lactic acid and lactates, phthalic acid and phtalates. Polyhydroxybenzoic acid and its salts are also used.
  • oxidizing agents comprise, hydrogen peroxide; and iodates, nitrates, carbonates, perchlorates, and/or persulfates of alkali, alkaline earth and rare earth metals.
  • inhibitors examples include BTA (benzotriazole) and TTA (tolyltriazole) or mixtures thereof.
  • Other inhibitors that can be used are 1-hydroxybenzotriazole, N-(1H- benzotriazole-l-ylmethyl)formamide, 3,5-dimethylpyrazole, indazole, 4-bromopyrazole, 3-amino-5-phenylpyrazole, 3-amino-4-pyrazolecarbonitrile, 1-methyimidazole, Indolin QTS and the like.
  • This example illustrates the removal rate due to electropolishing copper using a conventional, abrasive free CMP polishing fluid as the electrolyte.
  • a current density of 0.1 Amp per sq. cm. was used during this experiment.
  • Each data point was generated using a copper (Cu) disk, 1.2 cm, available from Johnson Matthey Company, immersed in the CMP polishing fluid for various contact times.
  • the CMP polishing fluid contained about 5% of ammonium hydrogen phthalate, about 1% of iminodiacetic acid, about 0.08% of tolyltriazole and about 1.7% of hydrogen peroxide.
  • the experimental results are tabulated below.
  • CMP of copper results in a removal rate of about 2,000 to about 4,000 Angstroms per minute. Thus for copper layer about 15,000 Angstroms in thickness, the average duration is about 5 minutes.
  • electropolishing requires the use of phosphoric acid or phosphate salt electrolytes or other electrolytes used in the plating industry. This choice of electrolyte makes integration of conventional electropolishing with CMP difficult due to cross-contamination and waste handling issues. Using a CMP slurry as the electrolyte enables integration of electropolishing with CMP resulting in a hybrid process that reduces processing time, significantly reduces wastes and yields substrates with highly planar surfaces.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)

Abstract

La présente invention concerne un procédé d'enlèvement de métal d'un substrat de semi-conducteur par dissolution des ions du métal dans un électrolyte. A cet effet, on mène de front trois opérations: d'une part application d'une tension entre un tampon de polissage et le substrat, d'autre part apport d'un électrolyte de polissage électrolytique à l'interface entre le substrat et le tampon de polissage, et enfin, accumulation de l'électrolyte autour du substrat au niveau du tampon de polissage.
PCT/US2001/043368 2000-11-20 2001-11-20 Planarisation par polissage électrolytique et traitement chimio-mécanique WO2002041369A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US24999500P 2000-11-20 2000-11-20
US60/249,995 2000-11-20

Publications (2)

Publication Number Publication Date
WO2002041369A2 true WO2002041369A2 (fr) 2002-05-23
WO2002041369A3 WO2002041369A3 (fr) 2004-01-08

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US (1) US20020104764A1 (fr)
WO (1) WO2002041369A2 (fr)

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Publication number Priority date Publication date Assignee Title
WO2006138110A3 (fr) * 2005-06-13 2007-06-07 Cabot Microelectronics Corp Procédé de polissage électrochimique régulé

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US7192335B2 (en) * 2002-08-29 2007-03-20 Micron Technology, Inc. Method and apparatus for chemically, mechanically, and/or electrolytically removing material from microelectronic substrates
US7078308B2 (en) * 2002-08-29 2006-07-18 Micron Technology, Inc. Method and apparatus for removing adjacent conductive and nonconductive materials of a microelectronic substrate
US7153195B2 (en) 2000-08-30 2006-12-26 Micron Technology, Inc. Methods and apparatus for selectively removing conductive material from a microelectronic substrate
US7074113B1 (en) * 2000-08-30 2006-07-11 Micron Technology, Inc. Methods and apparatus for removing conductive material from a microelectronic substrate
US7112121B2 (en) 2000-08-30 2006-09-26 Micron Technology, Inc. Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a microelectronic substrate
US7134934B2 (en) * 2000-08-30 2006-11-14 Micron Technology, Inc. Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or polishing medium
US7160176B2 (en) 2000-08-30 2007-01-09 Micron Technology, Inc. Methods and apparatus for electrically and/or chemically-mechanically removing conductive material from a microelectronic substrate
US7220166B2 (en) * 2000-08-30 2007-05-22 Micron Technology, Inc. Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate
US7094131B2 (en) * 2000-08-30 2006-08-22 Micron Technology, Inc. Microelectronic substrate having conductive material with blunt cornered apertures, and associated methods for removing conductive material
US7153410B2 (en) * 2000-08-30 2006-12-26 Micron Technology, Inc. Methods and apparatus for electrochemical-mechanical processing of microelectronic workpieces
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US6899804B2 (en) 2001-04-10 2005-05-31 Applied Materials, Inc. Electrolyte composition and treatment for electrolytic chemical mechanical polishing
US20070290166A1 (en) * 2001-03-14 2007-12-20 Liu Feng Q Method and composition for polishing a substrate
US7232514B2 (en) 2001-03-14 2007-06-19 Applied Materials, Inc. Method and composition for polishing a substrate
US7582564B2 (en) 2001-03-14 2009-09-01 Applied Materials, Inc. Process and composition for conductive material removal by electrochemical mechanical polishing
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US7390429B2 (en) 2003-06-06 2008-06-24 Applied Materials, Inc. Method and composition for electrochemical mechanical polishing processing
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US7153777B2 (en) * 2004-02-20 2006-12-26 Micron Technology, Inc. Methods and apparatuses for electrochemical-mechanical polishing
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WO2006138110A3 (fr) * 2005-06-13 2007-06-07 Cabot Microelectronics Corp Procédé de polissage électrochimique régulé
US7998335B2 (en) 2005-06-13 2011-08-16 Cabot Microelectronics Corporation Controlled electrochemical polishing method

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Publication number Publication date
WO2002041369A3 (fr) 2004-01-08
US20020104764A1 (en) 2002-08-08

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