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WO2002015260A1 - Sonde, carte a sondes et procede de fabrication de sondes - Google Patents

Sonde, carte a sondes et procede de fabrication de sondes Download PDF

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Publication number
WO2002015260A1
WO2002015260A1 PCT/KR2001/001358 KR0101358W WO0215260A1 WO 2002015260 A1 WO2002015260 A1 WO 2002015260A1 KR 0101358 W KR0101358 W KR 0101358W WO 0215260 A1 WO0215260 A1 WO 0215260A1
Authority
WO
WIPO (PCT)
Prior art keywords
probe
conductive
substrate
unit
penetration hole
Prior art date
Application number
PCT/KR2001/001358
Other languages
English (en)
Inventor
Dal-Lae Rhyu
Original Assignee
Nanomechatronics Inc
Apex International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020000047274A external-priority patent/KR20000064001A/ko
Application filed by Nanomechatronics Inc, Apex International Inc filed Critical Nanomechatronics Inc
Priority to AU2001277799A priority Critical patent/AU2001277799A1/en
Publication of WO2002015260A1 publication Critical patent/WO2002015260A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07357—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with flexible bodies, e.g. buckling beams
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips

Definitions

  • the present invention relates to a probe for testing semiconductor integrated circuit (IC) devices formed on a semiconductor wafer, probe card on which a plurality of probes is installed, and probe manufacturing method.
  • IC semiconductor integrated circuit
  • An instrument for the above-noted test is a probe instrument on which a tester and a probe card are installed, and the probe card electrically connects various electrical signal generators in the tester with pads in the semiconductor IC devices, or an electrical signal detector of the tester with the pads in the semiconductor IC devices.
  • FIGs. 1 (a) and 1 (b) show a prior tungsten needle probe card. As shown in
  • FIG. 1 (a) the needles 1 1 made of tungsten are provided in a predetermined array and are electrically insulated.
  • a tungsten needle jig 12 maintains the tungsten needles 1 1 in a high density, and a needle contact unit 13 is protruded from the tungsten needle jig 1 2.
  • Another terminal unit 14 of the tungsten needles 1 1 is passed through a tungsten needle supporter 1 5 in low density and protrudes from the tungsten needle supporter 1 5.
  • a connection unit (not illustrated) is connected to another terminal unit 1 4, passed through a circuit substrate 1 6, and electrically connected to a testing device (not illustrated.) As shown in FIG.
  • the testing device (not illustrated) is connected to an IC device through a tungsten needle probe card.
  • the conventional tungsten needle probe card having the above- described configuration reduces a pitch of the needle contact unit 1 3. Also, as many as the number of the needles is increased, it becomes difficult to array the needle contact unit 13 on an identical height, and a restriction of an expansion of the number of the needles 1 1 cannot fully satisfy the requirements of semiconductor manufacturers, who desire to increase the testing productivity by increasing the number of needles and concurrently testing many semiconductor devices. Also, the tungsten needles are manufactured by a sintering, and material defects such as cavities are densely provided to a contact unit that is acutely processed because of manufacturing features, and when they are repeatedly used, aluminum that is material of the pad of the semiconductor IC device is deposited on the defects and accordingly contact resistance is increased.
  • the tungsten needles lose their elasticity because the horizontal degree is distorted when they are repeatedly used.
  • the semiconductor IC tests are required at room temperature and high temperature, and since the probe and the probe card have different thermal expansion coefficients from the semiconductor IC wafer and also have different expansion directions when the temperature is increased, a sliding effect is generated between the contact unit of the probe and the pad of the semiconductor IC, and accordingly the contact resistance is increased and the contact states may be unstable. Also, when used for testing a high-speed semiconductor IC, since the lengths of the needles are long and the needles are adjacent to each other, the adjacent needles generate electrical interaction, and hence the precision of the test becomes unfavorable.
  • FIG. 2 shows a thin film probe card.
  • the conventional thin film probe card comprises a support plate
  • a conductive bumper 24 is provided on the support film 22 and optionally connected to a connection unit 25.
  • the conductive bumper 24 is contacted to a pad 26 of the IC device, and a testing device (not illustrated) is connected to the IC device via the conventional thin film card.
  • the above-described thin film probe card generates problems because of its short stroke. In detail, it is possible to array the conductive bumper 24 up to a precise pitch and increase its precision, but the height of the conductive bumper becomes shorter than the diameter of the bottom portion of the bumper.
  • the vertical operational probes can increase the density, but other problems of the tungsten probes such as elasticity reduction generated by repeated use, difficulty for uniformly maintaining the height of the needle contact unit, and a problem of deposition of the pad material of the semiconductor IC on the contact unit. Also, the productivity is decreased since all the probes must be inserted into an auxiliary plate one by one.
  • FIG. 3 shows a detail schematic diagram of a conventional probe and a probe card.
  • a plurality of detailed probes 31 is provided on a glass substrate 32, the glass substrate 32 is affixed on an auxiliary circuit substrate 33, and the auxiliary circuit substrate 33 is combined with a main circuit board 35 via a buffer pad 34.
  • a terminal of the probe 31 is electrically connected to the auxiliary circuit substrate 33 via a cavity on the glass substrate 32 using a wire 36, and the auxiliary circuit substrate 33 is electrically connected to the main circuit board 35 via the buffer pad 34 that includes a plurality of minute wires.
  • the semiconductor ICs have different pad layouts according to their categories, and in order to test other categories of the semiconductor ICs when the conventional probe and probe card are used, the probe 31 , the glass substrate 32 and the auxiliary circuit substrate 33 must be again manufactured except the main circuit board of the compatible probe card. Also, a space 37 for bonding the wire 36 is needed in addition to the probe 31 , and in order to install a plurality of probes, wafers of large diameter must be used since the probes are processed after silicon wafer and glass wafer are bonded, and in this case, the product cost increases, the etching uniformity becomes poor and the characteristics of the respective probes are differentiated, and accordingly, the total quality of the probe card is worsened.
  • a probe card comprises: a probe substrate including a plurality of probes and a support substrate for supporting the probes; a printed circuit board (PCB) having at least one probe substrate; and a space transformer having a first surface connected to the probe substrate and a second surface connected to the PCB, and adjusting gaps between the probe substrate and the PCB, wherein the probe comprises: an elasticity unit including: a first terminal and connected to the support substrate; and a second terminal, positions of which is elastically transformed and recovered upwards and downwards when pressure is applied or canceled; a contact unit protruded on a bottom portion of the second terminal of the elasticity unit; and a probe conductive pattern provided from the contact unit to the surface of the support substrate via the elasticity unit.
  • PCB printed circuit board
  • a method for manufacturing a probe substrate comprises: performing a photo lithographic process on the top portion of a silicon wafer and generating a probe elasticity unit and a support substrate having a predetermined thickness; performing a photo lithographic process on the bottom portion of the silicon wafer and generating a probe contact unit; generating an insulation film on exposed silicon surfaces including the probe and the support substrate; and forming a probe conductive pattern that covers from the surface of the contact unit to the surface of the support substrate through the elasticity unit.
  • FIG. 1 shows a conventional tungsten needle probe card
  • FIG. 1 (b) shows a contact state of a tungsten needle and a pad of a semiconductor IC when using the conventional tungsten needle probe card
  • FIG. 2 shows an operation of a conventional thin film probe card
  • FIG. 3 shows a conventional detailed probe and a probe card
  • FIG. 4 shows a probe card according to a preferred embodiment of the present invention
  • FIG. 5(a) shows a ground plan of a probe according to a first preferred embodiment of the present invention
  • FIG. 5(b) shows a cross sectional view of FIG. 5(a) with respect to a line 1 -1 ' ;
  • FIG. 5(c) shows a cross sectional view of FIG. 5(a) with respect to a line 2-2' ;
  • FIG. 5(d) shows an operation of the probe according to the first preferred embodiment of the present invention
  • FIG. 6(a) shows a ground plan of a probe according to a second preferred embodiment of the present invention
  • FIG. 6(b) shows a cross sectional view of FIG. 6(a) with respect to a line 1 -1 ' ;
  • FIG. 6(c) shows a cross sectional view of FIG. 6(a) with respect to a line 2-2' ;
  • FIGs. 7(a) to 7(f) show processes for manufacturing the probe according to the first preferred embodiment of the present invention
  • FIGs. 8(a) to 8(f) show processes for manufacturing the probe according to the second preferred embodiment of the present invention
  • FIG. 9 shows a cross sectional view of .a probe card including a conventional space transformer
  • FIG. 10 shows a space transformer according to the first preferred embodiment of the present invention
  • FIGs. 1 1 (a) to 1 1 (e) show processes for manufacturing the space transformer according to the first preferred embodiment of the present invention
  • FIGs. 12(a) to 1 2(b) show processes for manufacturing the space transformer according to the second preferred embodiment of the present invention
  • FIG. 13 shows a space transformer according to third preferred embodiment of the present invention
  • FIGs. 1 4(a) to 14(e) show processes for manufacturing the space transformer according to the third preferred embodiment of the present invention.
  • FIGs. 1 5(a) and 1 5(b) show processes for manufacturing a micro solder ball in the probe card according to the preferred embodiment of the present invention.
  • FIG. 4 shows a cross sectional view of a probe card according to a preferred embodiment of the present invention.
  • the probe card comprises: a probe substrate 1 12 for including a plurality of probes and a support substrate for supporting the probes; a printed circuit board (PCB) 1 20 for installing at least one probe substrate 112; and a space transformer 1 13 for having a first surface contacted with the probe substrate 1 12 and a second surface contacted with the PCB 1 20 and controlling a gap between the probe substrate 1 12 and the PCB 120.
  • PCB printed circuit board
  • the probe comprises a first terminal and a second terminal.
  • the first terminal is connected to the support substrate, and the second terminal comprises an elasticity unit, positions of which are elastically transformed and recovered upwards and downwards when pressure is applied or canceled; a contact unit protruded on a bottom portion of the elasticity unit; a probe conductive pattern provided from the contact unit to the surface of the support substrate via the elasticity unit; first and second metallic housings 1 1 7 and 1 1 8 formed from an outer portion of the space transformer 1 13 to a top portion of the PCB 120; and a screw 1 19.
  • FIG. 5(a) shows a ground plan of a probe
  • FIG. 5(b) shows a cross sectional view of FIG. 5(a) with respect to a line 1 -1 '
  • FIG. 5(c) shows a cross sectional view of
  • FIG. 5(a) with respect to a line 2-2' shows an operation of the probe.
  • the probe 41 is formed by optionally etching a predetermined portion of a single or poly crystalline wafer, and the probes are separated from a peripheral probe substrate 43 except one or a plurality of connection units 42.
  • a contact unit 44 is formed to protrude higher than other peripheral units.
  • the surface of the probe and the probe, substrate are formed of an insulation film 45.
  • Probe metal 47 that covers a predetermined bottom portion of the probe 41 including the protruded contact unit 44 and covers the top portion of the probe 41 and a probe pad 46 that is formed to connect with an external PCB (not illustrated) are formed to be connected with each other by plating them with solid metal or alloy, and accordingly, the contact unit 44 and the probe pad 46 are electrically connected.
  • FIG. 5(d) shows a state that a predetermined pressure is supplied to the probe 41 and the probe 41 is contacted to a pad 49 of a semiconductor IC device 48.
  • FIG. 6(a) shows a ground plan of a probe according to a second preferred embodiment of the present invention
  • FIG. 6(b) shows a cross sectional view of FIG. 6(a) with respect to a line 1 -1 '
  • FIG. 6(c) shows a cross sectional view of FIG. 6(a) with respect to a line 2-2' .
  • the probe 51 is formed by optionally etching a predetermined portion of a single or poly crystalline wafer, and the probes are separated from a peripheral probe substrate 53 except one or a plurality of connection units 52.
  • a contact unit 54 is formed to be protruded higher than other peripheral units.
  • a circular or polygonal groove 55 that penetrates a wafer is formed on the wafer. The diameter of the groove 55 can be from several micrometers to several hundreds of micrometers, and if considering a subsequent plating process, several micrometers are appropriate.
  • All the silicon surfaces including the probe, the probe substrate and the groove are formed of insulation film 56.
  • Probe metal 58 that covers the protruded contact unit, the bottom portion of the probe, the groove and inner walls of the groove 55 and a pad 57 that is formed on the top portion of the substrate to connect with an external PCB (not illustrated) are formed to be connected with each other by plating them with solid metal or alloy, and accordingly, the contact unit 54 and the pad 57 are electrically connected.
  • the single or poly crystalline silicon is of high elasticity, its plasticity transformation is rarely generated, and its intensity in the case of a minute structure of micrometers is greater than the stainless steel.
  • the probe according to the present invention is made of the above-noted crystalline silicon, the original form is preserved without any distortion or plasticity transformation even when the probe is repeatedly contacted hundreds of times.
  • the first step is to adjust the thickness of the probe and obtain a top space.
  • thin film for etching the silicon such as silicon nitride film , silicon oxide film or their compound film is formed on the top portion of the single or poly crystalline silicon wafer 61 as a protection film 62, and a photoresist pattern is formed thereon via a photo process.
  • a predetermined pattern is formed on the protection film 62 by using a dry etching that uses phosphoric acid or a wet etching that uses CCI 2 F 3 in the case of the nitride film or by using the wet etching that uses HF or the dry etching that uses gases such as CCI 2 F 3 , CF 4 , C 2 F 6 and C 3 F 8 in the case of the oxide film .
  • the silicon on the bottom portion is etched at a predetermined depth using the protection film 62 and the protection film is uncovered.
  • etching speeds of KOH, Ethylene Diamine Pyrocathechol (EDP) and TetraMethyl Ammonium Hydroxide (TMAH) according to crystal directions of the silicon 1 1 1 are slow about several thousand times of the etching speeds of other crystal directions are used to perform an anisotropic wet etching or an anisotropic dry etching that uses gases such as Cl 2 , CCI , BCI 3 , CHCI 3 , CHF 3 and CF 4 , and when the poly crystalline wafer is used, an anisotropic etching using the dry etching is performed.
  • the depth of the wafer to be etched is appropriately selected according to the thickness of the wafer, the thickness of the desired probe and the height of a contact needle unit of the probe.
  • the thickness of the probe is very important since the thickness as well as the width and length of the probe is a variable that determines the elasticity and intensity of the probe when the pressure for the contact is supplied, and therefore, an accurately calculated thickness must be formed according to usage environments of the desired probe, and since the usage environments can be greatly varied , detailed thickness will not be provided in the present invention.
  • the second step is to form an appearance of the probe. As shown in FIG.
  • an outer shape unit 63 of the probe is etched via the above-noted anisotropic etching so that the outer shape unit 63 is penetrated onto the bottom portion or a predetermined portion of the silicon film 64 is remained.
  • the thickness of the remaining silicon must be slimmer than the height of the probe' s contact unit to be formed in the subsequent step so that the remaining film is removed when the probe' s contact unit is formed and accordingly, the outer shape of the probe is completed.
  • the third step is to from the contact unit of the probe. As shown in FIG. 7(d) , portions except a contact unit 65 on the bottom portion of a probe substrate are removed as high as the height of the contact unit via the photo process and the etching process used when forming the photoresist pattern. Accordingly, the shape of the probe including the contact unit is completed.
  • an isotropic dry or wet etching that uses gas such as X e F 2 is used, and when using the single crystalline wafer, the crystal directions are appropriately provided, the anisotropic wet etching is used.
  • the fourth step is to electrically insulate the manufactured probes.
  • insulation film 66 such as the silicon nitride film or the silicon oxide film is provided for a full insulation on all the surfaces of the probe that is provided on the bottom portion of the probe substrate via the photo process and the etching process and the surfaces of the substrate.
  • the thermal oxide film forming method using an electrical furnace is the most appropriate method.
  • the appropriate thickness of the insulation thin film ranges from several hundreds to several ten thousand angstroms.
  • the fifth step is to electrically connect a pad 67 connected to the external PCB with a contact unit 68 of the probe.
  • the contact unit 68 and a predetermined portion of the probe are optionally plated using the metal of good conductivity, oxidation-resistance and relative high hardness such as nickel, tungsten and chrome or the alloy 69 via the photo process and the thin film forming process, and the top portion of the probe and the top portion of the probe substrate connected to it are optionally plated in a pad shape of several ten to several hundred micrometers using the above-noted metal and the alloy 69 via the photo process and the thin film forming method. Accordingly, when the contact unit 68 and the pad 67 of the probe are electrically connected, the silicon probe and the probe substrate are formed.
  • the pad 67 is directly joined with a micro solder ball that will be described in a subsequent step, and it is good to form an under bumper metallurgy (UBM) unit 70 on the pad 67 for a stable solder ball junction.
  • UBM under bumper metallurgy
  • the UBM unit 70 that comprises a diffusion protecting film for protecting the diffusion of the solder and a wet film such as the gold or the copper for improving the wetness of the solder is optionally formed via the photo process and a conventional electrolyte or electroless plating method. ''
  • FIGs. 8(a) to 8(f) show processes for manufacturing the probe according to the second preferred embodiment of the present invention.
  • the probe manufacturing method according to the second preferred embodiment is identical with that according to the first preferred embodiment except that a penetration hole is concurrently manufactured, and the metallic wiring for electrically connecting the contact unit with the pad of the probe is formed on the bottom portion of the probe in the step of forming the appearance of the probe.
  • the thickness of the probe is adjusted and a space for bending the probe is obtained.
  • a thin film for etching the silicon such as silicon nitride film , silicon oxide film or their compound film is formed on the top portion of the single or poly crystalline silicon wafer 1001 as a protection film 1 002, and a photoresist pattern is formed thereon via a photo process.
  • a predetermined pattern is formed on the protection film 1 002 by using a dry etching that uses phosphoric acid or a wet etching that uses CCI 2 F 3 in the case of the nitride film or by using the wet etching that uses HF or the dry etching that uses gases such as CCI 2 F 3 , CF 4 , C 2 F 6 and C 3 F 8 in the case of the oxide film .
  • the silicon on the bottom portion is etched at a predetermined depth using the protection film 1002 and the protection film is uncovered.
  • the above-described silicon etching when the single crystalline wafer is used, characteristics that etching speeds of KOH, Ethylene Diamine Pyrocathechol (EDP) and TetraMethyl Ammonium Hydroxide (TMAH) according to crystal directions of the silicon 1 1 1 are slow about several times of the etching speeds of other crystal directions are used to perform an anisotropic wet etching or an anisotropic dry etching that uses gases such as Cl 2 , CCI 4 , BCI 3 , CHCI 3 , CHF 3 and CF 4 , and when the poly crystalline wafer is used, an anisotropic etching using the dry etching is performed.
  • FIG. 8(c) an appearance of the probe and a
  • penetration hole are formed.
  • An outer shape unit 1 003 of the probe and the penetration hole 1 004 are etched using the anisotropic etching, and accordingly, they are penetrated to the bottom of the silicon wafer 1 001 or a predetermined amount of a silicon film 1 005 is preserved.
  • the thickness of the remained silicon must be slimmer than the height of the probe' s contact unit to be formed in the subsequent step so that the remained film is removed when the probe' s contact unit is formed and accordingly, the outer shape of the probe is completed.
  • portions except a contact unit 1 006 on the bottom portion of a probe substrate are removed as high as the height of the contact unit via the photo process and the etching process. Accordingly, the shape of the probe including the contact unit is completed. In this instance, so as to process the end portion of the contact unit 1006 in the shape of a pyramid or a similar sharp shape, an isotropic dry or wet etching that uses gas such as X ⁇ F 2 is used, and when using the single crystalline wafer, the crystal directions are appropriately provided, the anisotropic wet etching is used.
  • the next step is to electrically insulate the manufactured probes. As shown in FIG. 8(e) , insulation film 1 007 such as the silicon nitride film or the silicon oxide film is provided on all the surfaces of the probe and the surfaces of the substrate for a full insulation.
  • the thermal oxide film forming method using an electrical furnace is the most appropriate method.
  • the appropriate thickness of the insulation thin film ranges from several hundreds to several ten thousand angstroms.
  • a pad 1 008 connected to the external PCB is electrically connected with a contact unit 1 009 of the probe.
  • a predetermined portion of the probe is optionally plated using the metal of good conductivity, oxidation-resistance and relative high hardness such as nickel, tungsten and chrome or the alloy 1010 via the photo process and the thin film forming process, and the top portion of the probe and the top portion of the probe substrate connected to it are optionally plated in a pad shape of several ten to several hundred micrometers using the above-noted metal and the alloy 1010 via the photo process and the thin film forming method.
  • the silicon probe and the probe substrate are formed.
  • the physical vapor deposition (PVD), the chemical vapor deposition (CVD), the electrolyte plating or the electroless plating is used to form the thin film of the metal or the alloy, and particularly, the CVD, the electrolyte plating or the electroless plating is effectively used to perform fluent electrical connections between the top and bottom following the side wall of the penetration hole.
  • the pad 1008 of the probe is directly joined with a micro solder ball that will be described in a subsequent step, and it is good to form an under bumper metallurgy (UBM) unit 1011 on the pad 1008 for a stable solder ball junction.
  • UBM under bumper metallurgy
  • the UBM unit 1011 that comprises a diffusion protecting film for protecting the diffusion of the solder and a wet film such as the gold or the copper for improving the wetness of the solder is optionally formed via the photo process and a conventional electrolyte or electroless plating method.
  • FIG. 9 shows a cross sectional view of a conventional probe card including a space transformer.
  • the probe card comprises a main board 71 ; a space transformer 72; a probe 73; and housings 74 and 75. These parts are combined using screws 76.
  • a user appropriately determines and uses a distance ' a' between a bottom surface of the main board 71 and a probe contact unit 73 or a distance ' b' between a top surface of the main board 71 and the probe contact unit 73 according to specifications of peripheral devices that use the probe card such as a probe machine or a testing device. That is, the distances ' a' and ' b' must be adjusted and manufactured according to the user' s desired specifications since the probe card is one of compatible expendable supplies.
  • the thickness of the probe card is adjusted by the space transformer 72 that maintains electrical connections and appropriately adjusts the total thickness of the probe card.
  • the ceramic space transformer will be used for subsequent preferred embodiments.
  • the space transformer comprises a ceramic substrate 81 including a penetration hole 82 having a predetermined size and a predetermined thickness and being positioned on a predetermined location; a penetration hole conductive unit formed in the penetration hole 82; first and second conductive patterns 84 and 88 each of which formed on both surfaces of the ceramic substrate 81 and connected via the penetration hole conductive unit; and a photoresist film 85 for covering and protecting a predetermined portion of the first conductive pattern 84.
  • FIGs. 1 1 (a) to 1 1 (e) a process for manufacturing the space transformer according to the first preferred embodiment will now be described.
  • the ceramic substrate 81 is processed according to a predetermined size and thickness, and as shown in FIG. 1 1 (b), a penetration hole 82 with a diameter of a several hundreds of micrometers is generated on a predetermined position of the ceramic substrate 81 .
  • a method for generating the penetration hole 82 will be described later.
  • all the surfaces of the ceramic substrate 81 are plated with metal or alloy using electrolyte or electroless plating so as to form a plating film 83, and as shown in FIG. 1 1 (d) , both top and bottom surfaces of the ceramic substrate are mechanically processed to remove the plating film , and accordingly, the plating film is preserved only in the penetration hole.
  • FIG. 1 (c) all the surfaces of the ceramic substrate 81 are plated with metal or alloy using electrolyte or electroless plating so as to form a plating film 83, and as shown in FIG. 1 1 (d) , both top and bottom surfaces of the ceramic substrate are mechanically processed to remove the plating film , and accordingly, the plat
  • the desired electrical circuits are printed on both surfaces of the ceramic substrate via a screen printing method by using conductive pastes, or the desired first and second conductive patterns 84 and 88 are formed on both surfaces of the ceramic substrate via a lift-off method that performs a physical vapor deposition to deposit a conductive film on the photoresist pattern and remove the photoresist to obtain the desired patterns or via a method for depositing a conductive film and etching by using a photoresist pattern.
  • the first conductive pattern 84 functions as a solder ball junction pad 86 to which the micro solder ball is joined and as a wire pattern for electrically connecting the solder ball junction pad 86 with the penetration hole 82
  • the second conductive pattern 88 functions as a conductive pattern for electrical connection with the substrate.
  • a photoresist film 85 for protecting the conductive patterns is coated on the junction surface of the micro solder ball, and a conductive layer of the solder ball junction pad 86 to which the micro solder ball is joined is exposed via the photo process.
  • UBM unit 87 for a stable junction at the time of the micro solder ball junction is formed on the exposed conductive layer.
  • the UBM unit 70 that comprises a diffusion protecting film (i.e. , nickel) for protecting the diffusion of the solder and a wet film (i.e. , the gold or the copper) for improving the wetness of the solder is optionally formed via a conventional electrolyte or electroless plating method.
  • a pattern 89 such as a resist is formed via the photo process so that a wiring pattern may be formed on both surfaces of the ceramic substrate 81 through which the penetration hole 82 is generated, and then the plating film 83 is formed on portions where the resist is not coated by the electrolyte or electroless plating method. After this, when the resist film is removed, the desired wiring can be formed as the plating film 83.
  • the penetration hole will be described.
  • a wheel tool coated with diamonds is used to bore the penetration hole having a diameter of several hundreds of micrometers on the ceramic substrate.
  • the thickness of the ceramic substrate is about 1 to 2mm
  • the penetration hole having the diameter of several hundred micrometers can be relatively easily bored, but when the thickness is greater than 3mm , or 5 to 6mm , the boring process is very difficult and the corresponding cost is greatly increased.
  • FIG. 13 shows a space transformer according to third preferred embodiment of the present invention.
  • the space transformer comprises: a first ceramic substrate 91 having a plurality of first penetration holes
  • a first penetration hole conductive unit formed in the first penetration hole 92; a first conductive pattern 93 formed on both surfaces of the first ceramic substrate; a second conductive pattern 96 formed on both surfaces of the first ceramic substrate and connected to the first conductive pattern 93 via the first penetration hole conductive unit; a second ceramic substrate 91 ' having a plurality of second penetration holes 92' ; a second penetration hole conductive unit formed in the second penetration hole 92' ; a third conductive pattern formed on both surfaces of the second ceramic substrate 91 ' ; a fourth conductive pattern formed on both surfaces of the second ceramic substrate and connected to the third conductive pattern via the second penetration hole conductive unit; and an anisotropic conducting film 98 formed between the first and the second ceramic substrates 91 and 91 ' and electrically connecting the second and third conductive patterns.
  • FIGs. 14(a) to 14(e) processes for manufacturing the space transformer according to the third preferred embodiment of the present invention will be described.
  • a plurality of ceramic substrates is processed with the thickness of 1 to 2mm so as to easily bore the fine penetration holes, and as shown in FIG. 14(b), the penetration holes 92 and 92' are bored through the processed first and second ceramic substrates 91 and 91 ' according to the above-described method.
  • a pad 94 and a UBM unit 95 for joining the micro solder ball with a conductive thin film 93 are formed on one surface of the first ceramic substrate 91 , and a conductive pad 96 for joining with the substrate is formed on another surface of the first ceramic substrate 91 according to the method identical with those of the first and second preferred embodiments as shown in FIG. 10 and FIG. 12(a).
  • conductive pads 97 are formed on both surfaces of the second ceramic substrate 91 ' as shown in FIG. 14(d).
  • the conductive pad 96 of the first ceramic substrate 91 is matched with the conductive pad 97 of the second ceramic substrate 91 ' while an anisotropic conductive film 98 is positioned between the ceramic substrates 91 and 91 ' .
  • conductive balls 99 are provided in an adhesive film , and when the both substrates are compressed at high temperature, electrical connection is allowed in the compression direction via the conductive balls 99.
  • An appropriate compression temperature in this case ranges from 50 to 300°C, and more accurate temperatures and compression pressures are determined according to categories of the anisotropic conductive film.
  • the space transformer of a desired thickness can be manufactured.
  • FIGs. 1 5(a) and 1 5(b) a process for mechanically and electrically combining the space transformer, the probe and the probe substrate will now be described.
  • FIG. 1 5(a) when micro solder balls 1 02 are individually bumped on the portions where the UBM units of the space transformer 1 01 are formed or the micro solder balls 1 02 are printed using solder pastes via a screen mask, the micro solder balls are formed.
  • a silicon probe substrate 1 93 is provided on the micro solder balls on the space transformer and is then affixed on the same using a volatile adhesive, and a reflow process is performed at a temperature higher than the melting point of the micro solder balls 1 02 so as to volatilize the adhesive, and hence, the mechanical and electrical combination only by the micro solder balls 102 is completed.
  • the appropriate temperature of the reflow process ranges from 200 to 500°C, and the accurate temperature is differently determined according to the material of the solders to be utilized.
  • the silicon probe substrate includes a plurality of small modules and the small modules are repeatedly combined and are then combined with the space transformer, their effect is identical to that when a large silicon probe substrate is used according to the characteristics of the micro solder ball process. Accordingly, it is possible to manufacture a probe card that includes a plurality of probes without using a wafer of wide diameter when manufacturing the silicon probe substrate, and therefore, an expensive tool for processing the wafers of wide diameters is not needed, and a processing precision of the silicon probe substrate can be relatively increased. Also, damaged probes can be repaired more cheaply.
  • the density of the probes can be increased, and the heights of the needle contact unit of all the probes are uniformly maintained.
  • the probes manufactured according to the present invention preserve their high elasticity and their shapes are not transformed after their repeated uses, and the probe card makes it possible to concurrently test a plurality of semiconductor ICs.
  • the thermal expansion coefficient of the probe substrate according to the heat increase is identical with that of the semiconductor IC substrate, and since the configuration or shape of the probe substrate is similar to that of the semiconductor IC substrate and the expansion or shrinkage direction of the probe substrate generated according to temperature variations is identical with that of the semiconductor IC substrate, the contact unit between the probe and the semiconductor IC pad is not slid at the time of a test when the temperature is increased and a stable connection is obtained. Since the probe and the probe card according to the present invention have a shorter electrical path, electrical interferences of the adjacent probes are minimized, and thereby, test results of high reliability can be achieved when testing the high-speed operational semiconductor ICs.
  • the thickness of the probe card is adjusted using the ceramic space transformer, problems such as thermal and mechanical transformation generated by the iterated use of the probe card, and the thermal transformation in the case of the micro solder ball junction can be prevented.
  • the probe cards that have a plurality of probes can be manufactured without using the wafers of wide diameters when manufacturing the silicon probe substrate.
  • probe cards for testing the semiconductor device wafers and sockets for the burn-in tests of the LCD and the semiconductor devices can be manufactured by a slight modification or a substitute of an additional auxiliary device.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

L'invention concerne une carte à sondes qui comprend: un substrat à sondes, pourvu d'une pluralité de sondes et un substrat de support destiné à porter lesdites sondes; une carte à circuit imprimé comportant au moins un substrat à sondes; un adaptateur d'écartement, qui présente une première surface, reliée au substrat à sondes, et une seconde surface reliée à la carte à circuit imprimé, ainsi que des espaces de réglage situés entre le substrat à sondes et la carte à circuit imprimé. Une telle sonde comprend une unité élastique qui comporte: une première borne reliée au substrat de support; et une seconde borne dont les positions sont adaptées élastiquement et reprises, vers le haut et vers le bas, lorsqu'une pression est appliquée ou annulée; une unité de contact, qui fait saillie sur la partie inférieure de la seconde borne de l'unité élastique; et un motif conducteur de sonde, qui relie l'unité de contact à la surface du substrat de support, par l'intermédiaire de l'unité élastique.
PCT/KR2001/001358 2000-08-16 2001-08-09 Sonde, carte a sondes et procede de fabrication de sondes WO2002015260A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001277799A AU2001277799A1 (en) 2000-08-16 2001-08-09 Probe, probe card and probe manufacturing method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR2000/47274 2000-08-16
KR1020000047274A KR20000064001A (ko) 2000-08-16 2000-08-16 프로브 및 프로브 카드
KR10-2001-0042735A KR100415245B1 (ko) 2000-08-16 2001-07-16 프로브 카드, 그에 사용되는 프로브 기판 및 스페이스 트랜스포머, 이들의 제조 방법
KR2001/42735 2001-07-16

Publications (1)

Publication Number Publication Date
WO2002015260A1 true WO2002015260A1 (fr) 2002-02-21

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6956386B2 (en) * 2003-08-01 2005-10-18 Amst Company Limited Micro-cantilever type probe card
WO2006004779A1 (fr) * 2004-06-28 2006-01-12 Sv Probe Pte Ltd. Substrat a couche conductrice a motifs
US7141996B2 (en) * 2002-09-30 2006-11-28 Via Technologies, Inc. Flip chip test structure
WO2007049878A1 (fr) * 2005-10-28 2007-05-03 Phicom Corporation Carte sonde et son procede de fabrication
EP1847834A4 (fr) * 2005-02-10 2008-04-30 Tokyo Electron Ltd Interposeur, carte sonde, et procede de fabrication d'interposeur
EP1944613A1 (fr) * 2007-01-12 2008-07-16 Apex International, Inc. Carte de sonde pour test et son procédé de fabrication
US7859280B2 (en) 2005-06-02 2010-12-28 Phicom Corporation Probe card for testing semiconductor devices
US7868636B2 (en) 2007-05-11 2011-01-11 Amst Co., Ltd. Probe card and method for fabricating the same
JP2016085133A (ja) * 2014-10-27 2016-05-19 富士通セミコンダクター株式会社 プローブ針、プローブカード、プローブ針の製造方法及びプローブ針の再生方法

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JPH05206233A (ja) * 1992-01-29 1993-08-13 Hitachi Ltd 半導体のエージング装置
JPH0618555A (ja) * 1992-06-30 1994-01-25 Meisei Denshi Kogyo Kk マイクロスプリングコンタクト、マイクロスプリングコンタクトの集合体、該マイクロスプリングコンタクトの集合体からなる電気的接続用端子及びマイクロスプリングコンタクトの製造方法
JPH10282146A (ja) * 1997-04-07 1998-10-23 Nec Corp プローブカード及び半導体装置
JPH112645A (ja) * 1997-06-13 1999-01-06 Matsushita Electric Ind Co Ltd 半導体チップの検査装置
US5982183A (en) * 1993-07-19 1999-11-09 Tokyo Electron Limited Probing method and device with contact film wiper feature
US6005401A (en) * 1993-12-16 1999-12-21 Matsushita Electric Industrial Co., Ltd. Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method
KR20000017761A (ko) * 1999-11-19 2000-04-06 김수학 프로브 카드
JP2000131341A (ja) * 1998-10-29 2000-05-12 Micronics Japan Co Ltd プローブカード
JP2001050983A (ja) * 1999-08-09 2001-02-23 Jsr Corp プローブカード
WO2001048818A1 (fr) * 1999-12-29 2001-07-05 Formfactor, Inc. Structure d'interconnexion elastique pour composants electroniques et son procede de fabrication

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134365A (en) * 1989-07-11 1992-07-28 Nihon Denshizairyo Kabushiki Kaisha Probe card in which contact pressure and relative position of each probe end are correctly maintained
JPH05206233A (ja) * 1992-01-29 1993-08-13 Hitachi Ltd 半導体のエージング装置
JPH0618555A (ja) * 1992-06-30 1994-01-25 Meisei Denshi Kogyo Kk マイクロスプリングコンタクト、マイクロスプリングコンタクトの集合体、該マイクロスプリングコンタクトの集合体からなる電気的接続用端子及びマイクロスプリングコンタクトの製造方法
US5982183A (en) * 1993-07-19 1999-11-09 Tokyo Electron Limited Probing method and device with contact film wiper feature
US6005401A (en) * 1993-12-16 1999-12-21 Matsushita Electric Industrial Co., Ltd. Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method
JPH10282146A (ja) * 1997-04-07 1998-10-23 Nec Corp プローブカード及び半導体装置
JPH112645A (ja) * 1997-06-13 1999-01-06 Matsushita Electric Ind Co Ltd 半導体チップの検査装置
JP2000131341A (ja) * 1998-10-29 2000-05-12 Micronics Japan Co Ltd プローブカード
JP2001050983A (ja) * 1999-08-09 2001-02-23 Jsr Corp プローブカード
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WO2001036986A1 (fr) * 1999-11-19 2001-05-25 Kim, Soo, Hak Carte a sondes
WO2001048818A1 (fr) * 1999-12-29 2001-07-05 Formfactor, Inc. Structure d'interconnexion elastique pour composants electroniques et son procede de fabrication

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7141996B2 (en) * 2002-09-30 2006-11-28 Via Technologies, Inc. Flip chip test structure
US6956386B2 (en) * 2003-08-01 2005-10-18 Amst Company Limited Micro-cantilever type probe card
WO2006004779A1 (fr) * 2004-06-28 2006-01-12 Sv Probe Pte Ltd. Substrat a couche conductrice a motifs
US7180315B2 (en) 2004-06-28 2007-02-20 Sv Probe, Ltd. Substrate with patterned conductive layer
EP1847834A4 (fr) * 2005-02-10 2008-04-30 Tokyo Electron Ltd Interposeur, carte sonde, et procede de fabrication d'interposeur
US7891090B2 (en) 2005-02-10 2011-02-22 Tokyo Electron Limited Method for manufacturing an interposer
US7859280B2 (en) 2005-06-02 2010-12-28 Phicom Corporation Probe card for testing semiconductor devices
WO2007049878A1 (fr) * 2005-10-28 2007-05-03 Phicom Corporation Carte sonde et son procede de fabrication
US7975380B2 (en) 2005-10-28 2011-07-12 Phicom Corporation Method of fabricating a probe card
EP1944613A1 (fr) * 2007-01-12 2008-07-16 Apex International, Inc. Carte de sonde pour test et son procédé de fabrication
US7868636B2 (en) 2007-05-11 2011-01-11 Amst Co., Ltd. Probe card and method for fabricating the same
JP2016085133A (ja) * 2014-10-27 2016-05-19 富士通セミコンダクター株式会社 プローブ針、プローブカード、プローブ針の製造方法及びプローブ針の再生方法

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