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WO2002017364A2 - Module et son procede de fabrication - Google Patents

Module et son procede de fabrication Download PDF

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Publication number
WO2002017364A2
WO2002017364A2 PCT/US2001/041875 US0141875W WO0217364A2 WO 2002017364 A2 WO2002017364 A2 WO 2002017364A2 US 0141875 W US0141875 W US 0141875W WO 0217364 A2 WO0217364 A2 WO 0217364A2
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WO
WIPO (PCT)
Prior art keywords
microplatform
substrate
module
bonding
circuit
Prior art date
Application number
PCT/US2001/041875
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English (en)
Other versions
WO2002017364A3 (fr
Inventor
Ark-Chew Wong
Clark T.-C. Nguyen
Original Assignee
The Regents Of The University Of Michigan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Regents Of The University Of Michigan filed Critical The Regents Of The University Of Michigan
Priority to AU2001296857A priority Critical patent/AU2001296857A1/en
Publication of WO2002017364A2 publication Critical patent/WO2002017364A2/fr
Publication of WO2002017364A3 publication Critical patent/WO2002017364A3/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00253—Processes for integrating an electronic processing unit with a micromechanical structure not provided for in B81C1/0023 - B81C1/00246
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0361—Tips, pillars
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0172—Seals
    • B81C2203/019—Seals characterised by the material or arrangement of seals between parts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/033—Thermal bonding
    • B81C2203/035—Soldering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/038—Bonding techniques not provided for in B81C2203/031 - B81C2203/037
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/05—Aligning components to be assembled
    • B81C2203/051—Active alignment, e.g. using internal or external actuators, magnets, sensors, marks or marks detectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01057—Lanthanum [La]
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    • H01L2924/01059—Praseodymium [Pr]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/3011—Impedance

Definitions

  • This invention relates to modules and methods for making same.
  • Micromechanical ( ⁇ mechanical) resonators and bandpass filters with frequencies in the low-UHF range have recently been demonstrated with performances that rival (and even better in some cases) those of bulky, off-chip crystal and SAW filters used in present-day wireless transceivers.
  • ⁇ mechanical devices By integrating these ⁇ mechanical devices together with transistor circuits using a merged MEMS /transistor process technology, single-chip RF MEMS front-ends using high performance super-heterodyne architectures may eventually become possible.
  • the degree to which MEMS and transistor devices can be fnodularly combined is of utmost importance for RF MEMS applications, since the performance (e.g. , Q, stability) of resonator devices is especially sensitive to fabrication conditions (e.g. , temperatures, materials), which are often compromised in insufficiently modular merging processes.
  • Multichip Module (MCM) technology allows integrated circuits and passive devices to be mounted together on a common interconnecting substrate.
  • Flip-chip solder-bump is a chip attachment technique in which pads and the surface of the chip have solder balls placed on them. The chips are then flipped and mated with an MCM or a PCB, and the soldered reflowed to create a solder joint.
  • MCM Multichip Module
  • MCM-based microprocessors separate chip modules are flip- chip bonded to a larger substrate to form a complete system, where interconnects and signal lines between modules are formed directly on the substrate.
  • the modules are bonded to the pads on the substrate using either solder or gold bumps, which are normally deposited via evaporation or electroplating.
  • U.S. Patent No. 5,995,688 discloses a micro-opto-electromechanical device formed by a flip-chip bonding method.
  • U.S. Patent No. 6,214,644 discloses a flip-chip micromachine package wherein a micromachine chip is mounted as a flip-chip to a substrate.
  • An object of the present invention is to provide an improved module and method of making same.
  • a method for making a module includes a) providing a device including a first substrate, a microplatform, at least one microplatform bonding site on the microplatform, a structure fabricated and supported on the microplatform, and a support structure to suspend the microplatform above the first substrate.
  • the method also includes b) providing a second substrate including at least one circuit bonding site thereon and a circuit.
  • the at least one microplatform bonding site is c) aligned with the at least one circuit bonding site and d) the at least one microplatform bonding site is bonded to the at least one circuit bonding site so that the microplatform is bonded to the second substrate at at least one bond.
  • the structure may be a micromechanical structure and the circuit may be an electronic circuit.
  • the device may have a plurality of microplatform bonding sites and the second substrate may have a plurality of circuit bonding sites so that the microplatform is bonded to the second substrate at bonds.
  • the micromechanical structure may be electrically coupled to the electronic circuit by one or more of the bonds.
  • the first and second substrates may be forced apart to break the support structure and separate the first substrate from the second substrate.
  • Bond pads and solder bumps may be formed on the second substrate wherein the bond pads serve as the second plurality of bonding sites.
  • the micromechanical structure may include at least one micromechanical resonator.
  • the micromechanical structure may be a micromechanical filter.
  • the at least one microplatform may be defined by a layer of a wafer.
  • the microplatform may be defined by a silicon device layer of an SOI wafer.
  • the support structure may include a plurality of tethers for suspending the microplatform above the first substrate.
  • the second substrate may be a wafer.
  • the at least one electronic circuit may be a transistor circuit such as a BiCMOS, CMOS, bipolar, SiGe or GaAs circuit.
  • the step of bonding may include the step of compression bonding and wherein the bonds are compression bonds.
  • steps c) and d) can be repeated with the second substrate or at least one other substrate.
  • the bonds may be selectively heated in a vacuum to vacuum encapsulate the micromechanical structure.
  • Vacuum encapsulation can also be performed by burying the device under the platform under a layer of sealing material.
  • a module includes a device having a microplatform, at least one microplatform bonding site on the microplatform, and a structure fabricated and supported on the microplatform.
  • the module also includes a second substrate including at least one circuit bonding site thereon and a circuit.
  • the microplatform is coupled to the second substrate at the microplatform and circuit bonding sites such that the microplatform is in opposed and spaced relation to the second substrate.
  • the micromechanical structure may be vacuum encapsulated within a cavity defined by the microplatform and the second substrate.
  • micromechanical resonators are directly fabricated on microplatforms, which are flip-chip bonded to the bumps on the transistor circuit wafers, which are, in turn, connected to circuits via metal lines.
  • An aspect of the present invention is to provide a method for modularly merging two technologies via a process involving fabricating one technology on a platform suspended by tethers on a carrier substrate, then bonding the platform to a receiving substrate and tearing away the carrier substrate, leaving a bonded platform (on which devices in one technology are mounted) over and interconnected to devices in the other technology on the receiving substrate.
  • FIGURE la is a side sectional schematic view of a first device illustrating LOCOS nitride deposition and patterning
  • FIGURE lb is a side sectional schematic view of the first device showing an isolation trench etch
  • FIGURE lc is a side sectional schematic view of the first device showing a 2 ⁇ m isolation LOCOS oxide growth within the trench;
  • FIGURE Id is a side sectional schematic view of the first device showing stripped LOCOS nitride and an etched sealant trench;
  • FIGURE le is a side sectional schematic view of the first device showing the deposit of a 2 ⁇ m low stress nitride
  • FIGURE If is a side sectional schematic view of the first device showing the results of a surface micromachining process
  • FIGURE lg is a side sectional schematic view of the first device showing platform release using dry and wet techniques
  • FIGURE Ih is a side sectional schematic view of a second device showing deposit of a seed layer on a BiCMOS wafer
  • FIGURE li is a side sectional schematic view of the second device after plating 7 ⁇ m of Indium;
  • FIGURE lj is a side sectional schematic view of the two devices showing cold compression bonding thereof;
  • FIGURE 2 is a top plan schematic view of the first device just prior to cold compression bonding.
  • FIGURE 3 is a side view, partially broken away and in cross-section, illustrating vacuum encapsulation and sealing of a micromechanical structure.
  • Figures la-lj present the process flow of a flip-chip bonding process of the present invention and resulting module.
  • a thick and large platform is desirable such that the resonance frequency of the platform does not interfere with that of the micromechanical devices. More generally, the platform structure and design is best when its acoustic impedance is such that energy loss from the mounted resonator to the substrate is minimized.
  • the microplatform is realizable using an SOI approach, where the platform is defined by a silicon device layer 10, which is about 20 ⁇ m thick, of an SOI wafer, generally indicated at 12.
  • a buried oxide layer 14 (BOX) of the SOI wafer 12 is a 2 ⁇ m layer 14 of thermal or deposited oxide, and serves as a sacrificial layer.
  • the wafer 12 also includes a silicon substrate 16 as shown in Figure la.
  • a 2000 A thick LOCOS nitride layer 17 is first deposited on top of the SOI wafer 12. No pad oxide is required underneath the nitride layer 17 to reduce mismatch induced damage because the device layer is not used for transistors. Without the presence of a pad oxide, the bird's beak effect will be greatly minimized. To further minimize formation of a bird's beak, a thick nitride layer is preferred.
  • the nitride layer 17 is patterned and etched, and a 1 ⁇ m deep trench 18 is formed in the layer 10 using RIE ( Figure lb). This trench 18 defines an isolation region on which a resonator or filter will rest.
  • the trench 18 is refilled with 2 ⁇ m of thermal oxide 20 (Figure lc) using a LOCOS procedure.
  • the LOCOS nitride prevents oxidation in the field area, and thus only the trench regions are oxidized. Topography is greatly reduced because the thick LOCOS nitride without a pad oxide prevents the formation of bird's beaks at the oxide-nitride interface.
  • the LOCOS nitride layer is removed in a hot phosphoric acid solution.
  • a photoresist mask Using a photoresist mask, a 4 ⁇ m wide sealant trench 22 (or sealant ring) surrounding the isolation oxide region 20 (and surrounding the area of the eventual platform and its supports) is etched using an STS deep RIE ( Figure Id), which utilizes the Bosch process for straight sidewall formation.
  • the sealant trench etch is carefully characterized to prevent overetching of the Si layer 10, which can result in footing effects.
  • Footings can be minimized using a two-step etching process in which the etching chemistry is altered once the etch front gets close to the oxide.
  • careful and thorough characterization of the STS deep RIE was carried out to ensure that the etch would stop directly on exposed oxide.
  • Careful inspection of the sidewalls shows that scalloping occurred due to the Bosch process, which alternates between etch and passivation cycles.
  • the oxide layer 14 in the sealant trench 22 is removed next using a combination of dry and wet etch. Initially, the oxide 14 is etched using RIE with low pressure and high power settings to insure directivity. The last remaining 1000A of oxide 14 is removed using a 1: 10 HF:DI water solution in order to prevent polymerization on the exposed Si layer 16. The hydrophobic sidewall of the trenches 22 presents a bottleneck for the HF solution, which beads up upon contact to exposed Si. To alleviate the situation, Triton X is added to the HF solution to reduce the surface tension, making it more hydrophilic along the sidewalls. Initial dewetting of the surface with DI water and constant agitation during the etch also helps to speed up the etch front. The sealant trench 22 is separated from the oxide isolation layer 20 by about 15 ⁇ m.
  • the trench 22 is refilled with 2 ⁇ m of low stress nitride 24 (Figure le), which completely blankets the wafer.
  • the nitride 24 is deposited uniformly and conformally, and footings do not pose any major threats to the sealing.
  • the nitride 24 serves as anchors for the platform, as well as an isolation layer.
  • the nitride seal 24 also protects the oxide underneath the field area during release, providing additional stability and support to the released platforms.
  • micromechanical devices 26 such as resonators or a filter, or a mixer-filter, and conductive pads 27 are fabricated.
  • the resonators 26 are released in a surfactant-enriched straight HF solution, then interconnects and bonding pads are metallized using a lift-off procedure.
  • An optional supercritical CO 2 cleaning step can be performed at this point to purge away contaminants.
  • the process may be done by one of two methods: 1) by releasing the structure first, protecting them with PR, then continuing with the rest of the process; or 2) by keeping the sacrificial oxide intact during delineation of the platform, then releasing both the platform and resonator all at once.
  • tethers 28 for supporting all the four sides of a suspended platform 30 are patterned between the sealant ring 24 and the platform 30.
  • a folded tether design is chosen to compensate for stress and temperature variations.
  • Each tether 28 is folded symmetrically in both directions and sides, thus allowing for any changes due to stress and temperature variations to cancel out.
  • a thick resist is used in this lithography step in order to protect the MEMs structures 26 against the subsequent long HF release step. Due to the large spring stiffness of beams of the resonators 26, the resonators
  • Method #2 can be used if an HF-resistant metal is used for the micromechanical device interconnect.
  • the low stress nitride and Si layers 24 and 10, respectively, are etched using RIE and deep RIE, respectively, ( Figure lg).
  • the Si 10 under the nitride tethers 28 is removed using an optimized deep RIE etch recipe, which is intended for dry release of bulk micromachined devices. This step is best done using an isotropic recipe first until the nitride tethers are released, then using an anistropic deep RIE recipe until the POX oxide is reached.
  • the oxide 14 underneath the platform 30 is removed using a surfactant- enriched straight HF solution. Upon release, the resist is removed and an important CO 2 cleaning step is performed to prevent stiction of the platform 30.
  • Figure 2 is a schematic top plan view of a resulting device which includes a micromechanical filter 50 and Cr-Cu bond pads 52 on a thermal oxide isolation layer 54.
  • the layer 54 is supported on a nitride platform 56.
  • Nitride tethers 58 suspend the platform 56 and extend toward nitride anchors 60 over a release trench 62.
  • solder bumps 32 made of Indium are electroplated on a BiCMOS wafer, generally indicated at 34, instead.
  • Indium is malleable, making compression bonding relatively easy, and with a melting point of 170°C, it is relatively easy to reflow without affecting the BiCMOS wafer 34.
  • a Cr-Cu seed layer 36 is sputtered on the BiCMOS wafer 34 ( Figure lh).
  • the wafer 34 also includes a substrate 37, a pwell 38, a transistor circuit 40, and metal interconnects 44.
  • a plating mold is formed using a 10 ⁇ m thick photoresist.
  • the indium bumps 32 approximately 25 ⁇ m wide and 7 ⁇ m tall are then electroplated, and the resist mold is removed.
  • the Cu and Cr seed layers 36 are stripped using sulfuric peroxide and Cr etchant, respectively, but leaving behind portions of the layer 36 as pads for connecting to the bumps 32.
  • bonding could be used such as eutectic bonding, anodic bonding, fusion bonding, etc.
  • the present invention also includes the ability to do vacuum encapsulation after bonding the platform 30. If one bonds the platform 30 and second wafer 68 under vacuum, the solder can be selectively heated at bond points 70 in vacuum, thereby vacuum encapsulating the microstructure 26.
  • the present invention also includes the ability to vacuum encapsulate mounted devices within the confines of the platform 30, the second wafer 68, and the bonding sites 70. In particular, if one of the bonding sites 70 is made to completely surround and encompass the devices mounted on the microplatform 30, then bonding around this site 70 can seal the devices 26 within the confines of the platform 30, bonding site 70, and second wafer 68.
  • This invention also includes a new method for locally heating the bonding sites 70 that does not require routing of interconnect, nor any application of electrical signals to heat certain areas.
  • This new localized heating method involves the use of a heating filament material in contact with the bonding solder(s) that is sensitive to and can be heated by a certain wavelength of light, and where this wavelength of light does not heat any other materials in the total structure (e.g.
  • SiGe might be used as the heating filament, where SiGe can be heated with a certain wavelength of light that does not heat Si alone. In this way, localized heating is generated by light alone, without the need for applied voltages or cumbersome heating filament interconnect (as required by previous localized heating methods).
  • vacuum encapsulation can even be achieved without heating.
  • vacuum encapsulation can be achieved by first compression bonding as described above, but with holes in the device-surrounding bonding site. Vacuum sealing of the holes can then be achieved by depositing an appropriate sealant material 72 over the platform 30 and second wafer 68, covering the holes, and sealing platform-mounted devices 26 under vacuum.
  • sealing can be achieved by evaporating aluminum over the platforms 30 to a thickness that covers the bond site holes. (Note that aluminum evaporation is done under 0.1 microTorr vacuum, so this automatically provides a good vacuum.)
  • the bonded- microplatform technique can be quite economical for cases where the area consumed by micromechanics is smaller than that consumed by transistor circuits.
  • platform/device layouts can be duplicated many times on the "MEMS" wafer, and then the "MEMS" wafer can be used to service as many transistor circuit wafers as there are duplications.
  • a subset of platforms can be bonded to a transistor circuit wafer, then torn away, leaving those platforms on the transistor circuit wafer, but also leaving unbonded duplicates on the "MEMS" wafer.
  • These unbonded platforms can then be used to service other transistor circuit wafers.
  • the procedure for reusing a "MEMS" wafer over and over again can be implemented as a step and repeat process.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Micromachines (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Module soudé au niveau d'une microplate-forme et procédé amélioré servant à fabriquer ce module. Ce procédé consiste à utiliser un dispositif micromécanique comprenant un premier substrat, la microplate-forme, une première pluralité d'emplacements de soudage sur la microplate-forme, une structure micromécanique fabriquée et supportée sur la microplate-forme et une structure de support servant à suspendre la microplate-forme au-dessus du premier substrat. Ce procédé consiste, de plus, à mettre en application une tranche de circuit transistorisé comportant une deuxième pluralité d'emplacements de soudage et des circuits intégrés de transistor BiCMOS. La première et la deuxième pluralité d'emplacements de soudage sont alignées et soudées par compression, de façon à coupler et à accoupler mécaniquement la microplate-forme au deuxième substrat afin de constituer le module. On peut tirer sur la tranche de support de plate-forme afin de l'enlever, ce qui laisse des plates-formes soudées sur la tranche de substrat. Ceci permet de fusionner les deux techniques différentes selon un facteur de forme bas.
PCT/US2001/041875 2000-08-24 2001-08-24 Module et son procede de fabrication WO2002017364A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001296857A AU2001296857A1 (en) 2000-08-24 2001-08-24 Micromechanical multichip module and method of making same

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US22750600P 2000-08-24 2000-08-24
US60/227,506 2000-08-24

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WO2002017364A2 true WO2002017364A2 (fr) 2002-02-28
WO2002017364A3 WO2002017364A3 (fr) 2002-08-22

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AU (1) AU2001296857A1 (fr)
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EP2112471A1 (fr) * 2008-04-22 2009-10-28 Microcomponents AG Dispositif de montage pour composant électronique
CN103373697A (zh) * 2012-04-25 2013-10-30 罗伯特·博世有限公司 混合集成的部件和用于其制造的方法

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US20020072163A1 (en) 2002-06-13
US6667558B2 (en) 2003-12-23
US6569754B2 (en) 2003-05-27
US20030190776A1 (en) 2003-10-09
WO2002017364A3 (fr) 2002-08-22
AU2001296857A1 (en) 2002-03-04

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