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WO2002037298A2 - Systeme de controle a mode configurable mixte analogique et numerique - Google Patents

Systeme de controle a mode configurable mixte analogique et numerique Download PDF

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Publication number
WO2002037298A2
WO2002037298A2 PCT/US2001/046750 US0146750W WO0237298A2 WO 2002037298 A2 WO2002037298 A2 WO 2002037298A2 US 0146750 W US0146750 W US 0146750W WO 0237298 A2 WO0237298 A2 WO 0237298A2
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WO
WIPO (PCT)
Prior art keywords
analog
digital
processor
operational amplifier
peripheral
Prior art date
Application number
PCT/US2001/046750
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English (en)
Other versions
WO2002037298A3 (fr
Inventor
Hartono Darmawaskita
Ryan Scott Ellison
Randy L. Yach
Miquel Moreno
Original Assignee
Microchip Technology Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Priority to AU2002220235A priority Critical patent/AU2002220235A1/en
Publication of WO2002037298A2 publication Critical patent/WO2002037298A2/fr
Publication of WO2002037298A3 publication Critical patent/WO2002037298A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements

Definitions

  • This invention relates to controller systems having both analog and digital operating parameters, and, more particularly, to a single monolithic device such as an integrated circuit die or multi-chip package comprising a microcontroller and/or a digital signal processor (DSP) in combination with both analog and digital peripherals that may be configured and connected together, both before and during operation thereof, to function as a complete controller system.
  • a single monolithic device such as an integrated circuit die or multi-chip package comprising a microcontroller and/or a digital signal processor (DSP) in combination with both analog and digital peripherals that may be configured and connected together, both before and during operation thereof, to function as a complete controller system.
  • DSP digital signal processor
  • Controller systems are becoming more sophisticated while continuing to drop in price. More and more consumer and commercial products, such as for example but not limited to, appliances, telecommunications devices, automobiles, security systems, full- house instant hot water heaters, thermostats, and the like are being operated by these controller systems.
  • Analog inputs for receiving sensor information and analog outputs for controlling functions are necessary for the application of these controller systems.
  • Digital controllers were created from programmable logic arrays (PLA), field or mask programmable gate arrays (FPGA or PGA), microcontrollers or digital signal processors (DSP) in combination with software or firmware programs.
  • Analog input devices such as analog-to-digital converters (ADC) in conjunction with a separate operational amplifier were used to convert a time-varying analog signal into digital representations thereof for application to digital inputs of the digital controller and use thereof.
  • ADC analog-to-digital converters
  • a mixed signal controller is described in United States Patent No. 5,821,776, entitled “Field Programmable Gate Array with Mask Programmable Analog Function Circuits" to John E. McGowain.
  • the invention disclosed in this patent uses a field programmable gate array in combination with mask programmed analog functions on an integrated circuit die.
  • an integrated circuit controller must have a great deal of flexibility and capability for use in various systems configurations.
  • the integrated circuit controller should be mass-produced as a single monolithic device. Even in a single application, requirements for the integrated circuit controller may change, such as for example, but not limited to, a sleep mode and an operate mode, a low-power mode and a high-speed mode, etc.
  • Analog input peripheral devices of the integrated circuit controller must interface with very different analog input parameters such as speed, gain, offset, common mode rejection, linearity and the like.
  • different applications may have restrictions on the amount of power available to run the controller and its integral analog peripherals. Since there are so many different combinations of analog input, output and systems parameters, a large number of different types of integrated circuits having analog and digital capabilities have been required.
  • the invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing a configurable mixed analog and digital mode controller fabricated as a single monolithic device such as an integrated circuit semiconductor die or a multi-chip package (MCP).
  • the configurable mixed analog and digital mode controller comprises a processor such as a microcontroller and/or a digital signal processor (DSP) in combination with both analog and digital peripherals that may be configured and connected together, both before and during operation thereof, to function as a complete controller system.
  • DSP digital signal processor
  • Configurable parameter analog devices in combination with an analog switch matrix allows interconnection between the analog devices and connection to input/output (I/O) pads of the integrated circuit die or pins of the MCP.
  • the configurable parameter analog devices and analog switch matrix may be controlled by processor (microcontroller and/or DSP) which is also fabricated on the same integrated circuit die or in the MCP.
  • processor microcontroller and/or DSP
  • the processor has, but is not limited to, the following elements/components: program, volatile and non- volatile data storage; general input-output (I/O) ports; general digital peripherals such as timers, UART/USART, I 2 C, SPI and the like.
  • digital peripherals may be included to control power devices such as pulse width modulation (PWM) and programmable switched mode controller (PSMC) modules.
  • PWM pulse width modulation
  • PSMC programmable switched mode controller
  • analog peripherals such as digital- to-analog converters (DAC) and operational amplifiers (op-amp) may be included for generating or controlling analog outputs.
  • analog peripherals such as analog multiplexer switches, op-amps, programmable gain amplifiers (PGA), sample and hold amplifiers, comparators, analog-to-digital converters (ADC), voltage references, analog multipliers and the like may be included and adapted for receiving analog input signals.
  • a feature of the present invention is programmable gain bandwidth of the analog peripherals.
  • Still another feature is programmable gain of the analog peripherals.
  • Another feature is input offset zero calibration of the input offset voltage of the analog peripherals.
  • Another feature is programmable input offset zero calibration of the input offset voltage of the analog peripherals after every gain bandwidth or gain change of the analog peripherals.
  • Another feature is turning on and off the analog peripherals so as to conserve system power (sleep mode). Another feature is access to the inputs and outputs of the analog peripherals to connect feedback components thereto.
  • Another feature is programmable access to the inputs and outputs of the analog peripherals to connect feedback components thereto.
  • Another feature is programmable connections between the inputs and outputs of the analog peripherals, and also to input-output pads or pins of the controller package.
  • Another feature is programmable speed/power for operation of the analog input peripherals such as op-amps and comparators.
  • Another feature is configuration of a controller interrupt input or status input for connection to a digital output of an analog input voltage comparator. Another feature is small signal operation at or near a power supply rail voltage.
  • Another feature is small signal operation at or near ground reference.
  • Another feature is small signal operation at or near Ncc reference.
  • the configurable mixed analog and digital mode controller may be adapted for configuration depending on the applications or target market for the controller and, may comprise in combination with the processor (microcontroller and/or DSP), for example, but not limited to: a) Analog multiplexer switches for enabling analog comiections and also input and output analog signal routing to and from the analog peripherals of the controller. b) An op-amp ahead of an ADC for signal conditioning prior to analog-to-digital conversion, i.e., gain stage, filtering, sensor interface, etc. c) A programmable gain amplifier (PGA) ahead of the ADC where the combination thereof is adapted for auto ranging applications.
  • PGA programmable gain amplifier
  • a sample and hold amplifier ahead of the ADC adapted for sampling of one or more analog signals for later ADC conversion. This is especially applicable to power and motor control applications.
  • An op-amp ahead of a comparator for signal conditioning of the signal value to be compared. This enables high resolution firmware assisted analog-to-digital conversion such as delta sigma, slope ADC, etc.
  • An op-amp, comparator and ADC in combination wherein the comparator is adapted for coarse/crude monitoring of analog signal values even during a sleep mode, wherein the ADC may be used for other applications until • the comparator detects that a critical event has occurred, requiring the use of the ADC.
  • the ADC can be used for general analog-to-digital conversion, while the op-amp and comparator may be used for higher resolution firmware assisted delta sigma or slope ADC conversion for a selected channel.
  • a comparator in combination with a programmable switched mode controller (PSMC) for creating a complete closed control loop in hardware.
  • PSMC programmable switched mode controller
  • the processor need only setup the configuration parameters and set point with minimal firmware overhead and involvement of the processor.
  • An ADC in combination with a DAC or PSMC for creating a complete closed loop control system.
  • the ADC in combination with an op-amp can measure sensor inputs, the processor performs a control algorithm, and the DAC or PSMC interfaces to power actuators.
  • the op-amp and multiplier combination may also be used for signal modulation and demodulation in communications applications.
  • a programmable gain op-amp in combination with a digital-to- analog converter (DAC) that is connected to one of the inputs of the programmable gain op-amp may be used as an input stage for a low level analog sensor or transducer having a voltage offset.
  • the voltage offset introduced by the sensor may be cancelled out by a voltage of equal value thereto from the DAC to one of the inputs of the op-amp which then combines and cancels out this voltage offset.
  • the low level output from the analog sensor or transducer may be amplified to an optimal voltage level by programming the gain of the programmable gain op-amp.
  • a digital offset value is sent to the input of the DAC from either the processor or from the digital I/O.
  • the processor may also perform other function such as system timing, sequence control, user interface, communications, logging, etc.
  • the configurable operational amplifier(s), according to the present invention may comprise, for example, but not limited to, the following programmable features: programmable gain bandwidth product (GBWP), programmable amplifier gain, programmable selection of operational amplifier or comparator modes of operation, input offset zero calibration, ultra low input bias current, rail-to-rail input operation, and rail-to-rail output operation.
  • GWP programmable gain bandwidth product
  • the configurable op-amp(s) may also be programmed to a "sleep mode" which further reduces system power requirements.
  • the programmable gain bandwidth product (GBWP) feature enables the configurable op-amp of the invention to be utilized for slow, medium or high speed applications. Conservation of power in battery powered applications is readily facilitated by configuring the op-amp in a low GBWP mode, since the op-amp will consume a minimum amount of power from the power supply (battery).
  • the programmable gain feature may be utilized for various applications requiring a specific amount of gain.
  • the programmable gain feature may be utilized with sensors requiring both input offset and gain (span) calibration. It is contemplated and within the scope of the embodiments of the present invention that input offset zero calibration of the input offset voltage of the analog peripherals may be performed upon demand and may be programmed to occur whenever a gain change and/or input offset change is made.
  • op-amp operational amplifier
  • comparator modes of operation feature enables a configurable op-amp to also be utilized in an application as a comparator in combination with the processor. This feature adds flexibility and increased capabilities in the application of the controller system.
  • the input offset zero calibration feature may be used to minimize the input offset voltage of the op-amp. This feature enables the op-amp to be used for high gain applications, for example, but not limited to, instrumentation sensors such as temperature, pressure, vibration, humidity, gas, ozone, pH, vibration, battery charge and the like.
  • the input offset zero calibration feature may be invoked on demand during start-up of the controller system or at any time during operation thereof.
  • the input offset zero calibration feature can be performed at different (user programmable/selectable) common-mode input voltage levels. These features enable the op-amp to maintain an extremely low input offset voltage over the entire operating range of voltage and temperature which occurs during operation of the application.
  • Auto zeroing of the analog input peripherals such as op-amps and programmable gain amplifiers may be easily accomplished by connecting the output to the input of the analog input peripheral, then measuring the output voltage thereof. A voltage offset equal to the measured output voltage may then be used to auto zero the analog input peripheral. This voltage offset may be added or subtracted with a measured input value by calculation in the processor, or the voltage offset may be generated by a digital-to-analog converter whose output is connected to an input of the analog input peripheral.
  • the ultra low input bias current feature allows the op-amp to be used in very high impedance sensor applications such as, for example but not limited to, smoke detectors, carbon monoxide detectors, chemical sensors, photo detectors and the like.
  • the rail-to-rail input feature allows the op-amp to be used in applications requiring resolution of small input signal values that are near to one or the other of the power supply rails (such as voltages N DD or N ss ).
  • the rail-to-rail output feature allows the op-amp to take advantage of the entire input range of an analog-to-digital converter (ADC), i.e., maximum use of the total bit range (scale) of the ADC. It is contemplated and with the scope of the embodiments of the present invention that a plurality of analog devices and digital devices may be fabricated on a single semiconductor integrated circuit die or plurality of dice in a multi-chip package.
  • ADC analog-to-digital converter
  • Figure 1 is a schematic block diagram of a controller system comprising a processor in combination with integral analog and digital peripherals, and input-output functions on a single semiconductor integrated circuit die or in a multi-chip package (MCP);
  • Figure 2 is a more detailed schematic block diagram of the analog peripheral and switch portion of the controller system illustrated in Figure 1; and
  • Figure 3 is a schematic block diagram of digital switches in combination with the embodiment of the controller system of Figure 1.
  • the invention is a configurable mixed analog and digital mode controller fabricated as a single monolithic device such as an integrated circuit semiconductor die or a multi-chip package (MCP).
  • the configurable mixed analog and digital mode controller comprises a processor, such as a microcontroller and/or a digital signal processor (DSP), in combination with both analog and digital peripherals that may be configured and connected together, both before and during operation thereof, to function as a complete mixed signal system in a single monolithic integrated circuit package.
  • a processor such as a microcontroller and/or a digital signal processor (DSP)
  • FIG. 1 a schematic block diagram of a controller system comprising a processor in combination with integral analog and digital peripherals, and input-output functions on a single semiconductor integrated circuit die or in a multi- chip package (MCP) is illustrated.
  • the block diagram of Figure 1 is illustrative of a typical controller system on an integrated circuit die or in a MCP and is generally represented by the numeral 100.
  • the controller system 100 comprises a random access memory (RAM) 102, a processor 104, a program memory 106, a non- volatile program memory 132, digital input-output (I/O) 108, a digital-to-analog converters) (DAC) 110, an analog multiplier(s) 112, a programmable voltage reference(s) 114, a sample and hold amplifier(s) 116, a programmable gain amplifier(s) (PGA) 118, a programmable switched mode controller (PSMC) 120, analog switches 122, an operational amplifier(s) (op-amp) 124, a comparator(s) 126 and an analog-to-digital converter(s) (ADC) 128.
  • RAM random access memory
  • processor 104 a program memory 106
  • non- volatile program memory 132 non- volatile program memory 132
  • digital input-output (I/O) 108 digital-to-analog converters)
  • DAC digital-to-analog converters
  • the processor 104 may control any or all of the aforementioned devices on a data and control bus 130 which may be internal to the integrated circuit die or MCP.
  • the processor 104 may also be coupled to the RAM 102 and program memory 106 on the same or other higher speed memory bus(es).
  • the program memory 106 may be for example, but limited to, electrically programmable read only memory (EPROM), read only memory (ROM), electrically erasable and programmable read only memory (EEPROM/FLASH) and the like.
  • EPROM electrically programmable read only memory
  • ROM read only memory
  • EEPROM/FLASH electrically erasable and programmable read only memory
  • These general digital peripherals may be for example, but not limited to, timers, UART/USART, I 2 C, SPI, or other types of communications peripherals well known to those skilled in the art of digital electronics.
  • the non- volatile data memory may be used, for example but limited to, storing calibration data, device/product identity, etc.
  • the controller system 100 may be fabricated on one or more integrated circuit dice and enclosed in an integrated circuit package.
  • the integrated circuit package may be, for example, but is not limited to, plastic dual in-line package (PDIP), small outline (SO), shrink small outline package (SSOP), thin shrink small outline package (TSSOP), windowed ceramic dual in-line package (CERDIP), leadless chip carrier (LCC), plastic leaded chip carrier (PLCC), plastic quad flatpack package (PQFP), thin quad flatpack package (TQFP), pin grid array (PGA), ball grid array (BGA), TO-220, TO-247, TO-263 and the like.
  • PDIP plastic dual in-line package
  • SO small outline
  • SSLOP shrink small outline package
  • TSSOP thin shrink small outline package
  • CERDIP windowed ceramic dual in-line package
  • LCC leadless chip carrier
  • PLCC plastic leaded chip carrier
  • PQFP plastic quad flatpack package
  • TQFP thin quad flatpack package
  • PGA ball grid array
  • BGA ball grid array
  • the processor 104 controls the analog switches 122 through a control bus 242.
  • the analog switches 122 may be a switch matrix or any form of switch array known to one of ordinary skill in the art of analog integrated circuits.
  • the analog switches 122 may be used to connect inputs and outputs of the analog peripherals together and/or connect the analog peripherals to analog input-output (I/O) connections of the integrated circuit die or MCP.
  • Signal buses 248 are analog outputs from the analog switch 122 and signal buses 250 are analog inputs to the analog switches 122.
  • Signal bus 246 is a digital output from the processor 104 to the DAC 110.
  • Signal bus 244 is a digital output from the ADC 128 to the processor 104. Control and data information to and from the processor 104 may also be sent on the data and control bus 130 from and to any of the analog peripherals contemplated herein.
  • Signal bus 236 is a digital output from the comparator 126 to, for example, an interrupt or digital input of the processor 104.
  • the PGA 118 may be controlled by the processor over a digital control bus 234 and/or the data and control bus 130 ( Figure 1).
  • Auto zeroing of the analog input peripherals such as op-amps 124 and programmable gain amplifiers 118 may be accomplished, for example, by connecting the output of the op-amp 124 with the bus 250f to the input of the op-amp 124 with the bus 248f, then measuring the output voltage thereof with, for example, the ADC 128 connected with the bus 248h.
  • a voltage offset equal to the measured output voltage may then be used to auto zero the analog input peripheral.
  • This voltage offset may be added or subtracted with a measured input value by calculation in the processor 104, or the voltage offset may be generated by the digital-to-analog converter 110 whose output is connected with the bus 250a to an input of the op-amp 124 with the bus 248f.
  • the op-amp 124 may be connected ahead of the ADC 128 by the analog switches 122 connecting bus 250f to bus 248h and bus 248f to bus 240. This allows signal conditioning prior to analog-to-digital conversion, i.e., gain stage, filtering, sensor interface, etc.
  • feedback components may also be attached externally through the buses 240 and 238 by means of the analog switches 122.
  • the PGA 118 may be connected ahead of the ADC 128 by the analog switches 122 connecting bus 250e to bus 248h and bus 248e to bus 240.
  • the PGA 118 in combination with the processor 104 may be adapted for auto ranging analog input applications.
  • the sample and hold amplifier 116 may be connected ahead of the ADC 128 by the analog switches 122 connecting bus 250b to bus 248h and bus 248b to bus 240. This combination may be used for sampling one or more analog signals for later ADC conversion. This may be especially advantageous to power and motor control applications.
  • the op-amp 124 may be connected ahead of the comparator 126 by the analog switches 122 connecting bus 250f to bus 248g and bus 248f to bus 240. This combination allows for signal conditioning of the signal value to be compared, and enables high resolution firmware assisted analog-to-digital conversion such as delta sigma, slope ADC, etc.
  • the op-amp 124, comparator 126 and ADC 128 are connected in combination by the analog switches 122 connecting bus 240 to bus 248f and bus 250f to bus 248g, and then only connecting bus 248h to bus 250f when needed.
  • This combination enables the comparator to be used for coarse/crude monitoring of analog signal values even during a sleep mode, wherein the ADC 128 may be used for other applications until the comparator 126 detects that a critical event has occurred on the bus 240, thereby requiring the operation of the ADC 128.
  • the ADC 128 may be used for general analog-to-digital conversion, while the op-amp 124 and comparators 126 may be used for higher resolution firmware assisted (processor 104) delta sigma or slope ADC conversion for a selected channel.
  • the comparator 126 in combination with the PSMC may be used for creating a fully functional closed control loop in hardware.
  • the processor 104 need only setup the configuration parameters and set point with minimal firmware overhead and involvement.
  • the bus 248g may be connected to bus 240 for an external analog input signal.
  • the output of the comparator may be connected to an input of the PSMC 120 by digital switches 322 connecting digital bus 350c to bus 348d.
  • the ADC 128 in combination with either the DAC 110 or PSMC 120 may connected together and adapted for creating a fully functional closed loop control system.
  • the ADC 128 in combination with the op-amp 124 can measure analog sensors (external analog inputs).
  • the processor 104 may perform a control algorithm and the DAC 110 or PSMC 120 may interface to external power actuators (not illustrated).
  • the op-amp 124 may be used in combination with the analog multiplier 112 for signal conditioning and signal multiplication in the analog domain, for example, power measurement and metering applications. This combination may also be used for signal modulation and demodulation in communications applications.
  • the input of the op-amp 124 may be connected to the external analog input 240 through the bus 248f, and the output of the op-amp 124 may be connected to the input of the analog multiplier 112 through buses 248d and 250f.
  • Many functional combinations may be utilized in communications circuits and systems by using the analog multiplier 112 as a modulator during transmission of analog information, and as a demodulator during reception of analog information.
  • the analog switches 122 in combination with the processor 104 may easily reconfigure the analog and digital peripheral interconnections during operation of the control system for a multitude of complex functions performed by a single monolithic integrated circuit die or MCP.
  • An op-amp 124 having programmable gain, is used in combination with a digital-to-analog converter (DAC) 110 as an input stage for a low level analog sensor (not illustrated) or transducer having an voltage offset.
  • the output of the DAC 110 is connected to one of the inputs of the programmable gain op-amp 124 through buses 250a and 248f.
  • the voltage offset introduced by the sensor may be cancelled out by a voltage of equal value thereto from the DAC 110 to the one of the inputs of the op-amp 124 which then combines and cancels out the offset voltage.
  • a digital offset value is sent to the input of the DAC from the processor 104 through bus 246, or from the digital I/O 108 through buses 350b and 348f.
  • the processor 104 may control digital switches 322 through a control bus 342.
  • the digital switches 322 may be a switch matrix or any form of switch array known to one of ordinary skill in the art of digital integrated circuits.
  • the digital switches 322 may be used to connect digital inputs and outputs of the peripherals together and/or connect the peripherals to the digital input- output (I/O) 108 which is adapted for connections of the integrated circuit die or MCP.
  • Signal buses 348 are digital outputs from the digital switches 322 and signal buses 350 are digital inputs to the digital switches 322.
  • the digital switches 322 in combination with the analog switches 122 allow a very flexible configuration of both the analog and digital peripheral inputs and outputs comprising the control system illustrated in Figure 1. Both internal connections between peripherals and external connections may be easily configured before or during operation of the control system.
  • the configuration flexibility of the present invention makes this integrated circuit device very attractive for high volume, low cost manufacture.
  • the low level output from an analog sensor or transducer may be amplified to an optimal voltage level by programming the gain of the programmable gain amplifier 118 over the bus 348g from an external source via the digital I/O 108.
  • the digital outputs of the ADC 128 and/or the digital input of the DAC 110 may be connected to either internal or external peripherals via the digital switches 322. Whenever the gain of the PGA 118 is changed, input offset zero calibration of the input offset voltage thereof may be performed upon demand and may be programmed to occur whenever the gain change occurs.

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Abstract

L'invention concerne un contrôleur à mode configurable mixte analogique et numérique qui peut être fabriqué sous forme d'un dispositif unique monolithique tel qu'une puce de semi-conducteur de circuit intégré ou un boîtier multipuce (MCP). Ce contrôleur à mode configurable mixte analogique et numérique peut être un microcontrôleur et/ou un processeur de signal numérique (DSP) combiné avec des périphériques analogique et numérique qui peuvent être configurés et connectés ensemble, aussi bien avant que pendant leur fonctionnement, afin de fonctionner comme un système de contrôle complet.
PCT/US2001/046750 2000-11-06 2001-11-05 Systeme de controle a mode configurable mixte analogique et numerique WO2002037298A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002220235A AU2002220235A1 (en) 2000-11-06 2001-11-05 Configurable mixed analog and digital mode controller system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70709100A 2000-11-06 2000-11-06
US09/707,091 2000-11-06

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WO2002037298A2 true WO2002037298A2 (fr) 2002-05-10
WO2002037298A3 WO2002037298A3 (fr) 2003-12-31

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2411495A (en) * 2004-02-27 2005-08-31 Cyan Holdings Ltd Method and apparatus for generating configuration data
US7096073B2 (en) 2003-09-22 2006-08-22 Creo Il, Ltd. Configurable controller
US7282927B1 (en) 2006-06-21 2007-10-16 Eastman Kodak Company Use of a configurable electronic controller for capacitance measurements and cable break detection
US7420152B2 (en) 2006-09-07 2008-09-02 Eastman Kodak Company Wide-range linear output photo sensor circuit
US7756812B2 (en) 2005-09-22 2010-07-13 Eastman Kodak Company Adaptive input-cell circuitry useful in configurable electronic controllers
CN108303696A (zh) * 2018-01-30 2018-07-20 深圳市佰誉达科技有限公司 汽车盲点监测系统通用芯片系统及监测方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499549A (en) * 1982-06-25 1985-02-12 Automation Systems, Inc. Digital computer having analog signal circuitry
WO1997011428A1 (fr) * 1995-09-19 1997-03-27 Microchip Technology Incorporated Fonction d'activation d'un microcontroleur ayant un seuil programmable numeriquement

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7096073B2 (en) 2003-09-22 2006-08-22 Creo Il, Ltd. Configurable controller
US7277763B2 (en) 2003-09-22 2007-10-02 Kodak Il, Ltd. Configurable controller
GB2411495A (en) * 2004-02-27 2005-08-31 Cyan Holdings Ltd Method and apparatus for generating configuration data
US7756812B2 (en) 2005-09-22 2010-07-13 Eastman Kodak Company Adaptive input-cell circuitry useful in configurable electronic controllers
US7282927B1 (en) 2006-06-21 2007-10-16 Eastman Kodak Company Use of a configurable electronic controller for capacitance measurements and cable break detection
US7420152B2 (en) 2006-09-07 2008-09-02 Eastman Kodak Company Wide-range linear output photo sensor circuit
CN108303696A (zh) * 2018-01-30 2018-07-20 深圳市佰誉达科技有限公司 汽车盲点监测系统通用芯片系统及监测方法

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AU2002220235A1 (en) 2002-05-15

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