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WO2003030261A1 - Dispositif de memoire a semi-conducteur et procede de fabrication correspondant - Google Patents

Dispositif de memoire a semi-conducteur et procede de fabrication correspondant Download PDF

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Publication number
WO2003030261A1
WO2003030261A1 PCT/EP2001/011344 EP0111344W WO03030261A1 WO 2003030261 A1 WO2003030261 A1 WO 2003030261A1 EP 0111344 W EP0111344 W EP 0111344W WO 03030261 A1 WO03030261 A1 WO 03030261A1
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WO
WIPO (PCT)
Prior art keywords
trenches
gate
gate structures
substrate
memory device
Prior art date
Application number
PCT/EP2001/011344
Other languages
English (en)
Inventor
Massimo Atti
Christoph Deml
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Priority to EP01274520A priority Critical patent/EP1433205A1/fr
Priority to PCT/EP2001/011344 priority patent/WO2003030261A1/fr
Publication of WO2003030261A1 publication Critical patent/WO2003030261A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Definitions

  • the present invention relates to a semiconductor memory device and a corresponding manufacturing method.
  • CCD devices are known from W. S. Boyle, G. E. Smith: Charge Coupled Semiconductor Devices. The Bell Sys- tern Technical Journal. American Telephone and Circuit
  • EEPROM devices are generally well known in the state of the art. EEPROM cells are used to store information, which should be still accessable after switching the power supply off and on again, while being able to modify the stored information multiple times by pure electrical means. EEPROM cells usually have source and drain contacts forming a MOS transistor. Information is read out by measuring the attributes of the output characteristic, which is dependent of the information stored in a gate structure having floating and control gate.
  • the overall transfer characteristic (programming conditions to read current) is highly nonlinear and strong dependent on several side effects and production fluctuations. I.e. the Fowler Nordheim tunneling current is more than exponentially dependent on the electric field across the oxide. So the programming voltage and the oxide thickness have severe influence on the programming process. Thus, these parameters must be adjusted with high precision. These accuracy problems limit the multilevel ability of known cell concepts to 2 bits per cell.
  • drain and source contacts the cell area of typical cells in embedded EEPROM modules results in 22*F 2 to 70*F 2 .
  • the world record for cells with drain and source contacts is 8.8*F 2 .
  • the idea underlying the present invention is to combine the charge shifting, receiving or providing (from now on de- noted only by shifting) ability and the possibility to store charge non-volatile in an oxide or on a floating gate (EEPROM) or a similar structure.
  • the device or memory cells according to the invention will therefore be called charge coupled EEPROM cells or CC-EEPROM cells hereinbelow.
  • CCD and EEPROM technologies it is possible to increase the density of the memory and - at the same time - to build a non-volatile memory that is sequentially addressable itself and even usable as a volatile memory.
  • CCD technique is known to operate with 8 bit resolution. In combination with the linear transfer characteristic of the charge coupled EEPROM and the self limiting programming, this should provide deep multilevel ability. Fast cells do not have any influence on the programming process, because the programming stops, when all charge carriers tunneled to the floating gate. It is possible, to shift charge carriers into the cell area and to program a huge number of wordli- nes in parallel. This cuts the programming time of some order of magnitude. There is no static current consumption during read. Minimum size cells (4F 2 ) are possible, because the cell does not have drain or source contacts. Reduction of logic in the bitline and wordline section result in less chip area. There is an additional volatile memory functionality (i.e. using the same technology, it is also possible to implement high density memory buffer) .
  • said gate structures include a stack of a tunnel oxide, a floating gate, and an isolation structure.
  • said active regions are arranged at different ends of neighboring strips.
  • said active re- gions are electrically connectable to the gate structures of said corresponding strip by means of a respective control gate structure.
  • said respective control gate structure runs in parallel with the respective outermost gate structures at the corresponding end.
  • every third of said wordlines is connected to a common wiring line.
  • said second and first directions are perpendicular to each other.
  • the doping con- centration of the substrate is varied in a surface region of the strip regions.
  • a region of the second conductivity type is buried in the substrate along the strip regions.
  • said gate structures, said wordlines and said trenches have minimum design width F forming a cell dimension of 4F 2 .
  • Fig. 1 shows a CC-EEPROM cell arrangement
  • Fig. 2 shows the erase mode for a specific gate structure of the CC-EEPROM cell arrangement
  • Fig. 3 shows the channel hot electron programming mode £ ⁇ r__a_specif1c_gate_s_trucjtur_e_oE_th.e_CC_-EEPROM__ cell arrangement
  • Fig. 4 shows the Fowler Nordheim programming mode for a specific gate structure of the CC-EEPROM cell arrangement
  • Fig. 5a, b show the adjust charge mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement
  • Fig. 6a-c show the charge shifting mode for shifting a limited charge for a specific gate structure of the CC-EEPROM cell arrangement
  • Fig. 7 shows the Fowler Nordheim programming mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement
  • Fig. 8 shows the NAND reading mode for a specific gate structure of the CC-EEPROM cell arrangement
  • Fig. 9a,b show the adjust charge mode for reading a limited charge for a specific gate structure of the CC- EEPROM cell arrangement
  • Fig.lOa-c show the charge sink and sense amplifier for a specific gate structure of the CC-EEPROM cell arrangement
  • Fig. 11 shows a_ possible two-dimensional CC-EEPROM _ . cell_ arrangement
  • Fig. 12a-j show a schematic cross-sectional illustration of processing steps for manufacturing the two- dimensional CC-EEPROM cell arrangement according to a first embodiment of the present invention in the wordline direction;
  • Fig. 13 shows a schematic cross-sectional illustration corresponding to the process status of Fig. 12j perpendicular to the wordline direction;
  • Fig. 14 shows a top view of a two-dimensional CC-EEPROM cell arrangement according to the first embodi- ment of the present invention
  • Fig. 15a, b show a schematic cross-sectional illustration of processing steps for manufacturing the two- dimensional CC-EEPROM cell arrangement according to a second embodiment of the present invention in the wordline direction;
  • Fig. 16a-c show a schematic cross-sectional illustration of processing steps for manufacturing the two- dimensional CC-EEPROM cell arrangement according to a third embodiment of the present invention in the wordline_di ⁇ ection. 1 _
  • Fig. 1 shows a CC-EEPROM cell arrangement in a schematic representation.
  • reference sign 1 denotes a p-type semiconductor substrate, f.e. a silicon substrate, having an n + -type source and drain region 10 and 20, respectively, and having a p + -type body contact 30.
  • the gate structures include floating gates FG1, FG2, ..., FGn-1, and FGn above the substrate surface and electrically isolated therefrom. Moreover, each of the floating gates FG1, FG2, ..., FGn-1, and FGn has a corresponding control gate CGI, CG2, ..., CGn-1, CGn which is electrically isolated therefrom.
  • the gate structures are similar to the gate structure of an EEPROM, however, here a plurality of gate structures each consisting of a floating and control gate pair is aligned with preferably equidistant spacing.
  • S, Gl, G2, ..., Gn-1, Gn, D, B denote respective contacts of the corresponding source, drain, bulk, and gate regions.
  • JDnly_ schematically shown in_Fig.. 1 is a voltage generation means 100 for applying individual voltages between said gate structures CGI, FG1; ...; CGn, FGn and said active regions 10, 20 and body contact 30 such that charge may be programmed, read, shifted, and erased from said gate structures CGI, FG1; ...; CGn, FGn.
  • the voltage generation means 100 is connected to the respective contacts of the corresponding source, drain, bulk, and gate regions S, Gl, G2, ..., Gn-1, Gn, D, B. The associated functions will be described later.
  • the direction SD pointing from the source region 10 to the drain region 20 along the gate structures is called shifting direction.
  • the intermediate cell gate structures are not flanked by a heavy source/drain doping like in normal EEPROM cells or MOS transistors - otherwise the charge isolating and conserving capability for the adjusted charge to be described later would vanish.
  • light source/ drain doping may be acceptable.
  • the CC-EEPROM cell arrangement of Fig. 1 is arranged in a way, that charge can be shifted from one gate structure to another, i.e. CCD like.
  • the cell arrangement contains a minimum of one non-volatile cell. Gate structures of this arrangement need not all to be non-volatile cells (f.e. there may be gates just for shifting, gates just supplying volatile memory or gates next to a heavy source or drain doping) or need not all to be used for non-volatile storing
  • the gate alignment needs not to have straight line characteristic, but meander, tree, parallel, ... structures are also possible.
  • the arrangement normally has a minimum of one contacted or uncontacted source/drain doping, which can act as a charge source or sink. This doping can be located on the beginning or end (edge) of the arrangement. There might be a bulk contact. Bulk can but needs not to be isolated from the substrate by any means (junction, oxide, insulator) . A minimum cell area is feasible due to the minimum number of drain and source contacts.
  • Doping is somehow a subject for trade off (see below) and can be done non-uniformly or differently under the tunnel oxide on the one hand and under the spacing between two gates of the other. However, also uniform doping is possible.
  • the depletion regions which are induced by these gates, must touch laterally. This is achieved at relatively low or medium voltages, when the effective doping between these gates is low. Thus, a low intrinsic bulk doping or a contra doping is preferred.
  • Programming voltage is shared by the inter poly oxide (between floating and control gate) , the tunnel oxide (both effects known from normal EEPROM cells) and an unwanted, extending_jdepletion _rs,gion..undex_the_c-@lJ-_._
  • this depletion region can be limited by a heavy doping beneath the tunnel oxide, eventually spaced to the semiconductor surface.
  • Fig. 2 shows the erase mode for a specific single gate structure CGI, FG1 of the CC-EEPROM cell arrangement.
  • Erasing is done by applying an electrical field to the tunnel oxide in the orientation, that majority charge carriers, here holes (+) , are accumulating on the semiconductor surface in an accumulation region AC. Thereby, electrons (-) stored in the floating gate FG1 may be extracted. Therefore, an erase voltage V er is applied across a minimum of one CCD cell line bulk on the one hand and a minimum or one cell control gate on the other. This erase voltage V er of typically 16-18 V physically adds to the source-bulk- voltage V SB of typically > -0,7 V. It should be mentioned that here and in the following description all voltages are referred to the source voltage, however, this is just one of several possibilities. Erase is not self-limiting and cells behave differently, so one or more read verify plus program cycles may complete the erase step.
  • programming of the CC-EEPROM cells will be explained.
  • programming was always performed with unlimited charge for a predetermined time period.
  • programming can either be done with unlimited charge or with limited charge.
  • Programming voltage and/or programming time adjust the amount of charge, which is tunneling from the inversion layer through the tunnel oxide to the floating gate (Fowler Nordheim tunneling) or is injected into the tunnel oxide (channel hot electron) .
  • Fig. 3 shows the channel hot electron programming mode for a specific gate structure of the CC-EEPROM cell arrangement.
  • This structure is operated somehow similar to a NAND CHE (channel hot electron) EEPROM.
  • the source/drain doping in- between two cells is functionally substituted by supplying an appropriate V se ⁇ to all cells, which should not be programmed, so that the gaps between cells have a continuous inversion layer INV.
  • the cell having the gate structure FG3, CG3 to be programmed is supplied with a programming voltage V pr which is smaller than V se ⁇ , while V se ⁇ is greater than V DS . These voltages add to the source-bulk-voltage V SB .
  • a charge density CDE is cre- ated below the gate structure FG3, CG3.
  • a channel hot electron region CHE is created from where hot electrons can enter into the floating gate FG3.
  • Fig. 4 shows the Fowler Nordheim programming mode for a specific gate structure of the CC-EEPROM cell arrangement with unlimited charge source.
  • An inversion layer INV is built up from the source 10 to the cell having the gate structure FG3, CG3 which should be programmed. This can be done by selecting and deselecting other cells in an appropriate manner or by another special gate structure, which is placed near by every cell (f.e. in the third dimension) .
  • the select voltage V se ⁇ is applied to the two left hand cells and a deselect voltage V deSe i is applied to the right hand neighbor cell.
  • the cell having the gate structure FG3, CG3 to be programmed is supplied with a programming voltage V' pr which is greater than V pr in the case of channel hot electron programming.
  • Fowler Nordheim program- ming mode has the advantage that it is current saving in comparison to channel hot electron programming, because no current flow exists between source and drain 10, 20.
  • Adjusting and shifting charge can be done in parallel, so that a huge fraction of the sector can be filled with this information carrying charge quantities, which can finally be programmed in parallel (burst programming) .
  • burst programming In other words, having a two-dimensional array of CC EEPROM cells, first the information of all cells may be shifted under the array, and then all the information may be programmed in a single step. Because programming is time consuming (several milliseconds for Fowler Nordheim tunneling) , this parallel programming dramatically speeds up the memory filling with a continuous data stream (burst) .
  • Fig. 5a, b show the adjust charge mode for programming a limited charge for a specific gate structure of the CC- EEPROM cell -arrangement .
  • CCD filters charge coupled devices
  • a continuous inversion layer INV is built up from the source 10 to the adjusting gate structure CG2, FG2 by selecting the gate structure CGI, FG1 inbetween. Moreover, the right hand neighbor gate structure CG3, FG3 is deselected.
  • the amount of charge Q Ipr is adjusted by the program adjust voltage V prad which is linearly related by the following formula:
  • ⁇ F is the Fermi potential
  • V FB the flatband voltage
  • V SB the source-bulk voltage
  • this adjusted charge is separated from the source 10 by deselecting the gate structure CGI, FG1 between the source 10 and the adjusting gate structure CG2, FG2.
  • the desired charge amount could also be brought in via the source contact S (see Fig. 1) which would not be at a fixed potential in this case.
  • the charge can also be delivered by a charge adjusting circuitry which is connected to the source contact.
  • the cell having the gate structure CGI, FG1 next to the source 10 is a dummy cell (no information storage is possible in limited charge programming mode) and in principle needs not to have a floating gate.
  • the next cell, to which V prad is applied, could also be a dedicated transistor.
  • Adjusting can be done in parallel to reading another word- line as explained later.
  • Fig. 6a-c show the charge shifting mode for shifting a limited charge for a specific gate structure of the CC-EEPROM cell arrangement. Charge shifting from one cell to another is well known and vastly documented for charge coupled devices (CCD camera, CCD filter) .
  • Fig. 6a the starting situation is identical with the situation of Fig. 5b. Additionally shown is the gate structure having control gate CG4 and floating gate FG4 which is also deselected.
  • the gate structure CG3, FG3 is then selected by applying selection voltage V se ⁇ .
  • inversion layer INV expands to the gate structure CG3, FG3.
  • the gate structure CG2, FG2 is deselected by applying deselection voltage V dese ⁇ -
  • inversion layer INV contracts to the gate struc- ture CG3, FG3 which remains selected.
  • Fig. 7 shows the Fowler Nordheim programming mode for programming a limited charge for a specific gate structure of the CC-EEPROM cell arrangement.
  • Non-volatile programming is done by applying programming voltage V pr to the control gates of cell having the gate structure CG3, FG3 which should be programmed, leaving the neighbor cells deselected.
  • the limited charge programming procedure may also be done in two steps, namely first program adjust beneath the cell to be programmed (like read adjust in Fig. 5) and secondly program the charge to the floating gate as mentioned above.
  • first program adjust beneath the cell to be programmed like read adjust in Fig. 5
  • secondly program the charge to the floating gate as mentioned above.
  • the NAND mode reading provides a random access.
  • the situation of reading in NAND mode is very similar to channel hot electron programming. Only the applied read voltage V rea d is different.
  • Fig. 8 shows the NAND reading mode for a specific gate structure of the CC-EEPROM cell arrangement.
  • the CCD reading mode consists of three operation procedures: adjusting read charge, shifting charge towards the output and sensing the charge. There is no static current consumption. As a consequence of the shifting procedure, there is only a burst reading without a random access possibility.
  • the charge density CDE in the reading region RR depends on the information stored in the cell.
  • Fig. 9a, b show the adjust charge mode for reading a specific gate structure of the CC-EEPROM cell arrangement. Adjusting the reading charge is a preparation phase for the reading. It can be done in parallel to reading another wordline.
  • an inversion layer INV is built up from the source 10 to the cell having gate structure CG3, FG3 which is to be prepared. This can be done by selecting and deselecting other cells in an appropriate manner or by another special gate structure, which is placed near by every cell.
  • the select voltage V se ⁇ is applied to the two left hand cells and a deselect voltage V d ⁇ S ei is applied to the right hand neighbor cell.
  • the cell having the gate struc- ture FG3, CG3 to be prepared is supplied with a read adjust voltage V rea dad such that the charge of the inversion layer INV under the cell is a function of the charge on the floating gate.
  • V se ⁇ is greater than V rea dad f so that the depletion region under the shifting cell is independent of the stored charge on the floating gate of other cells.
  • the inversion layer charge is finally separated from the continuous inversion layer INV to the source 10 by deselecting the neighbour gate having the gate structure CG2, FG2.
  • Fig. lOa-c show the charge sink and sense amplifier for a specific gate structure of the CC-EEPROM cell arrangement.
  • Sensing is done in parallel to the charge shifting.
  • the sense amplifier SA is connected to the output node, which acts as a charge sink for the shifted charge.
  • the output node either the drain 20 or the source 10 can be used.
  • the cell next to the drain 10 is a dummy cell and needs not to have a floating gate (i.e. floating gate may be omitted or floating gate and control gate may be shorted) .
  • Sensing is well known and documented for charge coupled devices such as CCD camera, CCD filter etc.. These known sensing devices proved to be capable sensing at an 8 bit resolution, and facilitate deep multilevel sensing ability for CC-EEPROM cells according to this example.
  • the cell having gate structure CG2, FG2 is deselected, and the cells having gate structures CG3, FG3 and CG4, FG4 are selected. So, the charge to be read is shifted to the drain 20 from the gate structure FG3, CG3.
  • the cell having gate structure CG4, FG4 is selected, and the cells having gate structures CG2, FG2 and CG3, FG3 are deselected. So, the charge to be read is isolated at the drain 20 from the gate structure FG3, CG3.
  • the cell having gate structure CG2, FG2 is selected, and the cells having gate structures CG3, FG3 and CG4, FG4 are deselected. So, new charge to be read coming from gate structure CGI, FGl (not shown in Fig. 10c) is transferred to the gate structure FG2, CG2.
  • V CG V ad j USt - V F B + V b + V SB control gate potential
  • Vadj ust is the respective adj ust voltage
  • Equation (8) is rewritten to be
  • Equations (6), (7), (9) and (10) inserted in equation (5) result in
  • a volatile memory functionality of unused memory sectors is achieved by the following steps: adjusting charge quantity, shifting this charge under the desired gate structure, storage phase, shifting the charge to the output node and finally sensing the charge.
  • This storage mode has either a first in first out or a first in last out behaviour, namely dependent on what the output node is, i.e. source or drain. It can be used e.g. for storing the data to be programmed in another sector in order to realize a target programming algorithm.
  • Fig. 11 shows a possible two-dimensional top view of a CC- EEPROM cell arrangement.
  • reference signs WL1-W5 denote five different wordlines arranged in parallel and equidistantly.
  • S1-S4 and D1-D4 denote respective source and drain regions.
  • source SI and drain Dl there are five gate structures each consisting of a floating gate and a control gate, the control gates being formed by the wordlines L1- WL5 at overlapping points Kll, K21, K31, K41, K51 with the floating gates.
  • gate structures each consisting of a floating gate and a control gate, the control gates being formed by the wordlines WL1- WL5 at overlapping points K12, K22, K32, K42, K52 with the floating gates.
  • source S3 and drain D3 there are five gate structures each consisting of a floating gate and a control gate, the control gates being formed by the wordlines WL1- WL5 at overlapping points K13, K23, K33, K43, K53 with the floating gates.
  • gate struc- tures each consisting of a floating gate and a control gate, the control gates being formed by the wordlines WL1- L5 at overlapping points K14, K24, K34, K44, K54 with the floating gates. Not shown in Fig. 11 for simplification are isolation structures between shifting channels.
  • Fig. 12a-j show a schematic cross-sectional illustration of processing steps for manufacturing the two-dimensional CC- EEPROM cell arrangement according to a first embodiment of the present invention in the wordline direction.
  • reference sign 21 denotes a P-type silicon substrate, f. e. a silicon wafer substrate.
  • a thermal pad oxide layer 25 and a pad nitride layer 28 are provided on said substrate 21.
  • the pad nitride layer 28 and pad oxide layer 25 are structured into the form of a hard mask by a conventional photolithographic process.
  • said hard mask is used as a mask in an etching process for forming trenches 29 in said substrate 21.
  • the etching process is for example an anisotropic plasma etching process.
  • the structure shown in Figure 12b is ob- tained.
  • a thermal oxidation is performed to build up a trench oxide layer 102 in the interior of said trenches 29 in order to relax the silicon stress after the trench etch. This results to the structure shown in Figure 12c.
  • the trenches 29 in said substrate 21 run in parallel in a first direction (y in Figure 14) and define a plurality of strip regions (220 a-f in Figure 14) of said substrate 21 lying between each pair of adjacent trenches 29.
  • the width of the trenches 29 and the width of the intervening strip regions can be equal and amount to the minimum design width F of the used process.
  • said pad nitride layer 28 is removed by means of an appropriate wet etch process.
  • a first implantation step II is performed, using said pad oxide layer 25 as a scattering layer.
  • This first implantation step II is a p-type implantation to enhance the doping concentration of said substrate 21 in a surface re- gion 220 of said strip regions (220 a-f in Figure 14) be- tween said trenches 29 filled with said isolation oxide 215.
  • a second implantation step 12 is performed with n- type ions.
  • the second implantation step 12 provides a buried region 225 in said substrate 21, the depths of which approximately equals to or is less than the depths of said trenches 29, as also illustrated in Figure 12f, forming an insulated region 301.
  • Figure 12h illustrates that a tunnel oxide layer 230 is grown on the strip regions 220 in order to form the tunnel oxide of gate structures to be built up between the field isolation trenches 29.
  • a first conductive polysilicon layer 240 is deposited on the resulting structure which serves as floating gate polysilicon layer.
  • said first polysilicon layer 240 is partly removed by means of a chemical mechanical polishing step using the trench isolation 215 as stopping layer or using a combination between process time and chemical stop as stopping layer. Anyhow, the STI height can be calibrated to adjust this step. This results to the structure shown in Figure 12i.
  • an insulation structure 250 in form of an ONO layer (ONO Oxide-Nitride-Oxide) and thereafter a second conductive polysilicon layer 260 are deposited over the resulting structure. Then, a not shown mask is formed on the resulting structure, and the layers 230, 240, 250, 260 are patterned to form strips STI, ST2, ST3 running in parallel to a second direction (x in Figure 14) which perpendicularly crosses said strip regions 220 and accordingly said isolated trench regions 215.
  • ONO Oxide-Nitride-Oxide
  • Fig. 13 shows a schematic illustration corresponding to the process status of Fig. 12j perpendicular to the wordline direction.
  • Figure 13 illustrates the result of said etching steps.
  • gate structures comprising a tunnel oxide, floating gate, and isolation structure having worldlines on top in form of strips are obtained, where is clear that region 301 (p silicon) is insulated from the substrate 21 by the n- type layer 225 and is adjacent to two parallel STI trenches 215.
  • Fig. 14 shows top view of a two-dimensional CC-EEPROM cell arrangement according to the first embodiment of the pres- ent invention.
  • the widths of the trench isolation regions 220 a-f and the distance of the wordlines WL1'-WL9' has been depicted with doubled width in order to enhance clarity. This leads to a cell size of 9 F 2 , as shown in cell Z in Fig. 14.
  • the said gate structures 230, 240, 250, said wordlines WL1'-WL9' and the space therebetween, and said trenches 29 may have minimum design width F which enables forming a minimum cell dimension of 4F 2 .
  • a plurality of active regions SI'- S6' of the n + -type is provided at the end of a corresponding strip 220 a-f and is electrical connectable to the gate structures of the corresponding strip by means of an intervening control gate line CLl, CL2.
  • Said control gate lines CLl, CL2 are formed as normal MOSFET- gates, and not as gates including a floating gate.
  • Said ac- tive regions Sl'-S6' are arranged at different ends of neighbouring strips 220 a-f and connected to wiring lines LSl'-LS ⁇ 1 . This arrangement also helps to realize the connection.
  • every third wordline of the wordlines denoted as WL1'-WL9' is connected to a common wiring line L147, L369, L258, respectively.
  • This connection scheme for the wordlines which are made of the second polysilicon layer 260 in Figure 12a-j and 13 is in accordance with the shifting scheme for operation of said semiconductor memory device as explained above.
  • crosses in Figure 14 denote contact holes for connecting the wirings to the respective semiconductor regions.
  • p + -type bulk contacts at the end of the strips for electrically connecting said regions 301.
  • Fig. 15a, b show a schematic cross-sectional illustration of processing steps for manufacturing the two-dimensional CC- EEPROM cell arrangement according to a second embodiment of the present invention in the wordline direction.
  • the chemical mechanical polishing step shown in Figure 12i is replaced by a photolithographic patterning step resulting in the structure shown in Figure 15a.
  • This photolithographic patterning step provides an overlay of the floating gate regions 240' over the isolating regions 215, i.e. a floating gate having a larger width.
  • the process flow according to the second embodiment increases the minimum achievable cell size, namely to 6F 2 .
  • it exhibits the advantage of a simple process flow and the advantage that the area of the junction between the wordline 260' and the ONO isolation structure 250' is larger than the area between the floating gate 240' and the tunnel oxide. The latter results in electrical advantages during operation of said semiconductor memory device.
  • Fig. 16a-c show a schematic cross-sectional illustration of processing steps for manufacturing the two-dimensional CC- EEPROM cell arrangement according to a third embodiment of the present invention in the wordline direction.
  • the process is modified after the CMP step used to form the floating gate regions of the first polysilicon layer 240.
  • a third polysilicon layer 270 is depos- ited over the resulting structure of Figure 12i, as illustrated in Figure 16a.
  • Said third polysilicon layer 270 is patterned for forming an extension of said floating gate regions of said first polysilicon layer, as illustrated in Figure 16b.
  • the isolation regions 215 due to the presence of the isolation regions 215, a certain offset of the photomask of said process for patterning said third polysilicon layer 270 is not detrimental to the manufacture process.
  • the ONO isolation structure 250'' and the second polysilicon layer 260'' for forming the worldlines WL1'-WL9' are deposited and structures as explained above.
  • the third embodiment exhibits the above men- tioned electrical advantage of the second embodiment and furthermore the advantage that cell dimensions as small as 4F 2 may be obtained.
  • CC-EEPROM cells or arrangements can also be mixed with other, well known EEPROM cells or cell elements in order to bring in their functionality.
  • CC-EEPROM cell can be routed out of the cell shifting area and can be connected to other structures (gate, flanked doping, transistor, tunnel oxide, ... ) , in order to provide additional functionality or to combine known NVM (non-volatile memory) principles (channel hot electron, Fowler Nordheim tunneling, reading via MOS- FET, ...) or charge shifting principles (CCD) with the CC- EEPROM cell principle. So, a minimum of one CCD principle is used in order to erase, program, read non-volatile mem- ory.
  • NVM non-volatile memory

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  • Non-Volatile Memory (AREA)

Abstract

L'invention concerne un dispositif de mémoire à semi-conducteur et un procédé de fabrication correspondant. Ce dispositif de mémoire à semi-conducteur comprend un substrat semi-conducteur (21) présentant un premier type de conductivité (p); une pluralités de tranchées (29) situées dans ledit substrat (21) et s'étendant parallèlement dans une première direction (y), lesdites tranchées étant remplies d'une matière d'isolation (215; 215a-e); lesdites tranchées (29) définissant une pluralité de zones de bandes (220a-f, 301) dudit substrat (21) s'étendant entre chaque paire de tranchées adjacentes (29) ; une pluralité de structures de grille (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250'') permettant de stocker une charge de manière non volatile, disposée au-dessus de la surface du substrat semi-conducteur (21) et électriquement isolée de celle-ci; ladite pluralité de structures de grille (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250'') étant disposées en bandes (ST1-3) s'étendant parallèlement dans une seconde direction (x), et traversant lesdites zones de bandes (220a-f, 301); une pluralité de lignes de mot (WL1'-WL9'; 260, 260', 260''), une ligne de mot correspondante étant disposée sur chaque structure de grille (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250''); et une pluralité de zones actives (S1'-S6') du second type de conductivité (n+), chaque zone active (S1'-S6') étant disposée à une extrémité d'une bande correspondante (220a-f, 301), et pouvant être électriquement connectée aux structures de grille (230, 240, 250; 230, 240', 250'; 230, 240, 270, 250'') de la bande correspondante (220a-f, 301).
PCT/EP2001/011344 2001-10-01 2001-10-01 Dispositif de memoire a semi-conducteur et procede de fabrication correspondant WO2003030261A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP01274520A EP1433205A1 (fr) 2001-10-01 2001-10-01 Dispositif de memoire a semi-conducteur et procede de fabrication correspondant
PCT/EP2001/011344 WO2003030261A1 (fr) 2001-10-01 2001-10-01 Dispositif de memoire a semi-conducteur et procede de fabrication correspondant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2001/011344 WO2003030261A1 (fr) 2001-10-01 2001-10-01 Dispositif de memoire a semi-conducteur et procede de fabrication correspondant

Publications (1)

Publication Number Publication Date
WO2003030261A1 true WO2003030261A1 (fr) 2003-04-10

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PCT/EP2001/011344 WO2003030261A1 (fr) 2001-10-01 2001-10-01 Dispositif de memoire a semi-conducteur et procede de fabrication correspondant

Country Status (2)

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EP (1) EP1433205A1 (fr)
WO (1) WO2003030261A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008112A (en) * 1998-01-08 1999-12-28 International Business Machines Corporation Method for planarized self-aligned floating gate to isolation
US20010018253A1 (en) * 1998-09-29 2001-08-30 Takuya Nakamura Semiconductor device and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008112A (en) * 1998-01-08 1999-12-28 International Business Machines Corporation Method for planarized self-aligned floating gate to isolation
US20010018253A1 (en) * 1998-09-29 2001-08-30 Takuya Nakamura Semiconductor device and manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LAHIRI S K: "MNOS/FLOATING-GATE CHARGE COUPLED DEVICES FOR HIGH DENSITY EEPROMS:A NEW CONCEPT", PHYSICS OF SEMICONDUCTOR DEVICES, XX, XX, vol. 3316, no. 2, December 1997 (1997-12-01), pages 951 - 956, XP001035171 *

Also Published As

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