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WO2003030522A1 - Synchroniseur de video numerique a sorties analogique non decodee et numerique decodee - Google Patents

Synchroniseur de video numerique a sorties analogique non decodee et numerique decodee Download PDF

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Publication number
WO2003030522A1
WO2003030522A1 PCT/US2002/002676 US0202676W WO03030522A1 WO 2003030522 A1 WO2003030522 A1 WO 2003030522A1 US 0202676 W US0202676 W US 0202676W WO 03030522 A1 WO03030522 A1 WO 03030522A1
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WO
WIPO (PCT)
Prior art keywords
video
digital
signal
synchronizer
circuit
Prior art date
Application number
PCT/US2002/002676
Other languages
English (en)
Inventor
Virgil L. Lowe
Original Assignee
Fortel Dtv, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/969,415 external-priority patent/US7046299B1/en
Application filed by Fortel Dtv, Inc. filed Critical Fortel Dtv, Inc.
Publication of WO2003030522A1 publication Critical patent/WO2003030522A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H04N5/067—Arrangements or circuits at the transmitter end

Definitions

  • the present invention relates generally to an apparatus for synchronization of digital video and, more particularly, to a digital video synchronizer providing parallel and coordinated synchronization paths for decoded and undecoded video.
  • video synchronizers are constructed primarily as decoders to create a digital video signal from the composite analog signal, and only secondarily as synchronizers to bring the signal into time synchronization with the other signals in the TN studio.
  • These video synchronizer devices digitize the input composite video signal and separate it into its luminance and chrominance components. The chroma is then demodulated to R-Y and B-Y components to provide a digital video signal. This digital video signal is then synchronized to bring it into time synchronization with the studio signals.
  • Such devices provide an analog output, they do so by using an encoder to convert the digital component signal back to an analog composite signal to feed the analog equipment in the studio.
  • the video decoder/synchronizers that generate an analog output using an encoder and a digital-to-analog converter (DAC) after the synchronizer create errors in the composite video output.
  • the errors are caused by the problems inherent in the operation of a comb filter and the decoding and encoding process. These errors cause visible defects in the output signal, particularly after several generations of processing.
  • Today's video studios and broadcast stations are in a transition period where most studios are equipped with both composite analog equipment and digital equipment. The true need in this situation is to have a synchronizer that can operate both ways - without decoding the signal so there is maximum transparency and with decoding so that there can be a digital output.
  • the purpose of this invention is to meet the need identified above without the cost associated with two independent synchronizers.
  • There are also other benefits that come from combining the two operating modes including high quality freeze for still frames and hot switch, and the ability to switch between the fully transparent and the re-encoded outputs depending on the source of the video being synchronized.
  • This invention uses the circuitry of the "Composite Video Decoder” patent application serial number 09/523,889, filed March 13, 2000; the “Time Base Corrector” patent application serial number 09/523,884, filed March 13, 2000; U.S. Patent No. 6,278,495B1, for "Digital Comb Filer for Decoding Composite Video Signals", which issued on August 21, 2001; and "Digital Comb Filter” patent application serial number 09/637,140, filed August 11, 2000, which is a continuation-in-part of patent application serial number 09/523,888, which issued as U.S. Patent No. 6,278,495B1.
  • the issue fee for the "Composite Video Decoder" patent application has been paid.
  • Each of these commonly assigned, co-pending patent applications and issued patents are hereby incorporated by reference into this description as fully as if here represented in full.
  • processing is added for a parallel path in the synchronization memory that bypasses the comb filter and video decoder, and allows the digitized composite video to pass through unchanged.
  • This path is coordinated with the decoder path to provide the most desirable features of both a composite video synchronizer and a digital component decoder/synchronizer and time base corrector (TBC).
  • TBC digital component decoder/synchronizer and time base corrector
  • a digital encoder is also incorporated for some output modes and to generate a synchronizing and color burst signal to replace the sync and burst signals of the composite signal.
  • the synchronized composite and synchronized encoded signals are adjusted in timing, gain and direct current (DC) offset to match one another so they can be faded, mixed or multiplexed without detectable differences.
  • the invention is a unique digital video synchronizer that provides a clean path composite video synchronizer and component digital synchronizer with a decoder and following encoder for both analog composite and digital component video inputs and outputs. It provides the best features and specifications of composite and component processing for television broadcasters and studios during the transition from analog to digital television.
  • the video synchronizer described herein provides a clean composite video output that has not been decoded and re-encoded while simultaneously providing a decoder to produce a serial digital component output and an encoder to produce a composite signal from a serial digital input.
  • Several new circuits were invented as well as unique ways of sharing circuits to reduce the overall circuitry and cost of the device.
  • Several functions common to composite synchronizers and some digital component synchronizers such as chroma gain, hue control, freezing video, hot switch, vertical interval data and test signal processing and sync and burst regeneration or pass are also processed in a unique way.
  • This invention accepts two forms of input signals and generates two forms of output signals.
  • One set of input and output signals corresponds to the Society of Motion Pictures Television Engineers (SMPTE) 259 specification for serial digital component signals.
  • SMPTE 259M is a standard which describes the serial digital interface for system M (525/60) digital television equipment, operating at either 4:2:2 component video signal or 4:xFsc NTSC composite video signal.
  • the standard proposed by the SMPTE is intended for 10 bit digitization schemes.
  • the other set of input and output signals is for analog composite input and analog composite output signals.
  • the digital component signal is processed for Y gain, R-Y gain, B-Y gain, hue, and black level. Other processing functions such as black stretch, and further luma and chroma combing can optionally be added.
  • FIG. 1 is the system block diagram of the digital video synchronizer showing the interconnection of the video decoder, synchronizer and time base corrector subsystems in accordance with an exemplary embodiment of the invention
  • the unique aspect of this invention is the provision of parallel and coordinated synchronization paths for decoded and undecoded video. While simple, this provision is unique as is evidenced by the wide variety of competing products presently on the market that have no such provision or capability.
  • the present invention coordinates the two synchronization paths and provides parallel control of the common synchronizer functions:
  • Fig. 1 illustrates a general block diagram of an exemplary embodiment of the invention.
  • Block 1 represents a serial digital input receiver and equalizer.
  • the SDI input normally conforms to the SMPTE 259 standard.
  • Block 2 represents a serial to parallel converter that produces a parallel digital component signal conforming to the CCTR-601 standard.
  • CCTR now ITU-R
  • Block 3 represents an analog composite input circuit that includes a differential analog input receiver with a DC clamp circuit for removing hum and DC offsets to correct the input to the proper DC level and gain to drive the analog to digital converter (ADC).
  • ADC analog to digital converter
  • ADC analog to digital converter
  • Block 4 represents an analog to digital converter that samples the analog video at 27 MHz so the output can be digitally filtered and processed before being decimated to the standard 13.5 MHz luma clocking frequency of the CCIR-601 standard.
  • Block 5 represents the digital sync stripper, digital clamp circuit, the digital portion of the analog clamp circuit and the digital PLL (phase locked loop) circuit.
  • Block 6 represents an advanced comb filter circuit that uses both three line adaptive comb filtering, adaptive field combing and adaptive frame combing in varying combinations according to the pixel-by-pixel video content of the analog input. Its operation is fully described in U.S. Patent No. 6,278,495B1, incorporated by reference herein.
  • the output of block 6 is a decoded component Y, R-Y and B-Y signal.
  • a unique composite video circuit is also incorporated to make the invention possible.
  • Block 7 represents a set of field memories and block 8 represents a set of line delay memories.
  • These memories may be incorporated in an field-programmable gate array (FPGA) or application specific integrated circuit (ASIC) with the decoder or they may be any form of static random access memory (SRAM), synchronous dynamic RAM (SDRAM), first- in-first out (FIFO) memory or other type of high-speed memories.
  • FPGA field-programmable gate array
  • ASIC application specific integrated circuit
  • SRAM static random access memory
  • SDRAM synchronous dynamic RAM
  • FIFO first- in-first out
  • Block 9 represents the synchronizer and its time base corrector (TBC) function.
  • Block 10 represents the array of field memories necessary for synchronization. Eight fields of memory are necessary if phase alternating line (PAL) signals are to be synchronized with full transparency since the PAL color field sequence only repeats every eight fields.
  • PAL phase alternating line
  • Blocks 11, 12, and 13 are similar to blocks 3, 4 and 5 except that they operate on the station reference genlock signal.
  • Block 14 represents the genlock logic that tracks the location of the genlock horizontal and vertical synchronization periods and controls the reading of the video out of the synchronization memory and the phase of the subcarrier for the encoder represented in block 19.
  • Block 15 provides the control necessary to shift the phase, both horizontally and vertically, of the output relative to the genlock signal.
  • Block 16 represents the point in the system at which digital audio from an outside audio subsystem can be embedded into the digital video stream.
  • Block 17 represents the parallel to serial converter that takes the CCTR-601 parallel video and streams it out in the SMPTE-259 format.
  • Block 18 represents the point at which any audio embedded in the incoming serial digital video can be stripped out and sent to an outside audio subsystem.
  • Block 19 represents the encoder that transforms the component video back into modulated composite video. This encoder can function on component video regardless of whether it was obtained from an analog or digital source. This block is also used to generate the sync and burst signals that are reinserted into the undecoded analog signal when it is being used. Block 20 is used to rescale the undecoded analog signal to calibrate the system and compensate for variations in analog circuitry.
  • Block 21 represents a multiplexer that switches between the (re-)encoded version of the video signal and the undecoded version. When sync and burst signals are being reinserted into undecoded video, this multiplexer switches at the end of video and at the start of video on each line. Whenever this switch is operated, the switch point should be targeted at points in the signal at which both signals should have the same value. Since as a practical matter they cannot be relied upon to be exactly the same value, this switch must fade between them over the course of several clock cycles.
  • Block 22 represents the digital to analog converter with its associated reconstruction filters and cable drive amplifiers.
  • Block 23 represents the circuitry that generates a pulse proportional to the delay of the video synchronizer. The normal use of this pulse is to signal a companion audio synchronizer so that the relative timing between audio and video can be maintained.
  • Video gain control can be accomplished by a subtractor, a multiplier and an adder.
  • the subtractor offsets the values so that gain is applied relative to the black level instead of being relative to an arbitrary zero point.
  • the multiplier applies the gain, and the adder restores the video back to offset form. A difference between the number subtracted and the number added will also accomplish black level control.
  • Another portion of the delay can be obtained from the comb filter subsystem 6.
  • the comb filter subsystem 6 Immediately after the digitized video data is received into the decoder, it is separated into high band and low band components for use in the comb filter.
  • These band-split components are individually delayed through line 8 and field memories 7 to provide the various reference lines for the comb, systems that use both the line above and the line below the current line for combing, there is a net delay through the comb filter of a little more than a line. Taking the two band split components and adding them back together after the first line of delay will perfectly recover the original composite signal delayed by the length of the band split filter plus the line of delay for the comb.
  • This delay plus the composite processing amplifier (proc amp) processing delay leaves only a small delay that must be added to the composite path to bring it in time synchronization with the combed and demodulated video.
  • This delay is easily provided using a small FIFO memory such as is readily available in an FPGA or ASIC.
  • the delay could also be created with a single, independent, larger FIFO.
  • the data must be passed through a field memory system 10.
  • the required paths through the memory are a 10-bit path for luma, a 10-bit path for chroma and a 12-bit path for composite video.
  • the luma and chroma word sizes are dictated by CCIR-601
  • the 12-bit path for composite video is dictated by the need to keep the same level of accuracy on the composite path that is available on the decoded path.
  • the sum of these word sizes is 32 bits which is an even multiple of 8. This happens to fit well into readily available memory parts because they are commonly organized in eight bit bytes, so the needed storage fits evenly into common memory chips with no wasted bits.
  • DAC digital to analog converter
  • the coordination strategy for each operating mode is as follows: 1. Full Pass-Through - In this mode, the multiplexer 21 remains switched to the composite side full time.
  • the multiplexer 21 sends the composite side to the digital-to-analog converter (DAC) 22 during active video time and sends the encoded video to the DAC 22 during the horizontal and vertical interval time.
  • DAC digital-to-analog converter
  • Chroma Gain Control This mode operates in conjunction with either of the previous modes.
  • chroma gain control was accomplished by treating all high pass data as being chroma. Since a fully separated chroma is available in a combined device such as provided by this invention, it is a superior source of data for use in chroma gain control. Since the multiplexer 21 is not a simple switch, but instead is a cross-fader, chroma gain control can be combined with the multiplexer 21 by providing a variable coefficient set to the cross-fader in the chroma path.
  • Time Base Correction In this mode, the multiplexer 21 remains switched to the encoder side 19 full time because the digital output from the system must also be time base corrected, and it is more efficient to have a single time base corrector 9. hi addition, since there is rarely a need for multi-generation time base correction in a modern video studio, the minor signal distortion caused by decoding and re- encoding does not have a chance to accumulate. As an alternate, a separate analog time base corrector could be provided for the composite path, but the quality of results would be similar, at best, to the decode, time-base-correct, reencode method.
  • Minimum Delay For minimum delay, it is not desirable to use the entire color field sequence for synchronization. In this case, the multiplexer 21 remains switched to the encoded side 19 full time and there is at most a two-field delay inherent in the synchronization.
  • Hue control, image position control and SCH phase control interact with each other.
  • Image position is controlled by adjusting the relative timing of the video data coming from the memory to the sync generated by the encoder 19.
  • any such moves will change the hue of the video. This could be compensated by changing the phase of the generated burst to match, but that would change the SCH relationship, which should normally remain constant.
  • changing the phase of the input data sample clock relative to the incoming color burst will change the hue and this is the preferred method of controlling the hue whether for production reasons or to compensate for video position moves. Note that none of these control functions are available without the Sync and Burst Reinsertion mode of operation.
  • Genlock fine phase control is achieved by adjusting the phase of the DAC clock relative to the color burst on the genlock signal.
  • Genlocking is a system of synchronizing two video signals to the same timing and color phase in order to coordinate their colors and syncs. Genlocking permits mixing, cross-fading, keying, and special effects generation between the two video signals. This allows the analog output of the system to be precisely phase aligned with other analog equipment in a studio without having any noticeable effect on the digital output.
  • Field and frame freeze are accomplished by write protecting a field or frame of memory and playing it back continuously through the encoder 19 to the DAC 22. This represents a significant improvement to the method previously used on undecoded synchronizers in which the high band data was interpreted as chroma and its sign inverted in alternate fields to simulate the construction of the appropriate color field.
  • Hot switch is a technique familiar to one of ordinary skill in the art of conventional video synchronizers.
  • a hot switch is an abrupt change of the video input from one source to another source that may be different in horizontal, vertical or subcarrier phase.
  • the typical compensation to such a disruption is to freeze the last good field until the write clock servo and memory write sequence control can lock to the new input signal and write one or more fields into the unfrozen portion of the memory without error.
  • hot switch is considerably more complex than provided by either previous decoders or previous undecoded synchronizers.
  • the first step of a hot switch is to detect a disruption in the timing of the incoming video signal. Once such a disruption is detected, that field must be marked as bad and inappropriate for display, the playback of video must be frozen on the last known good field, and the undecoded mode of operation must be disabled.
  • the last known good field then must be protected from being overwritten and all other fields must be marked as containing old data.
  • writing to all fields except the last known good field can be re- enabled.
  • At the end of each field as it is rewritten it must be marked as new.
  • the synchronizer timing calls for a field which has been marked as new, the freeze of the last known good field is released and that field is re-enabled for writing. Playback of each field in its sequence can then proceed unless an old field is encountered. In that case, the previous field is repeated until a field marked new has been encountered. Once eight new fields have been played back, the undecoded mode can be re-enabled.
  • An alternate embodiment of the hot switch is to move the write side of the memory addressing to another section of the larger memory that is used in this invention.
  • the out-of-sequence playback problem is largely eliminated because it is the protection of the last good field while writing new data that raises the greatest potential for getting fields out of sequence.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

L'invention concerne un synchroniseur de vidéo numérique destiné à fournir des voies de synchronisation parallèles et coordonnées pour de la vidéo codée et non décodée (Fig.1). Un traitement de voie parallèle dans une mémoire de synchronisation, en dérivation du filtre à peigne et du circuit de décodage vidéo (6), permet à un signal vidéo composite numérisé de passer inaltéré. Cette voie parallèle est coordonnée à la voie du décodeur afin de d'obtenir à la fois des caractéristiques de synchroniseur de vidéo composite et de synchroniseur/décodeur de composant numérique, avec un correcteur de base temporelle. Un encodeur numérique (19) retransforme une composante vidéo en vidéo composite modulée. L'encodeur numérique (19) produit un signal de salve de couleur et de synchronisation afin de remplacer les signaux de couleur et de synchronisation du signal de vidéo composite. Le signaux composites synchronisé et encodé synchronisé sont réglés en cadence, gain et décalage CC (20) afin d'être accordés l'un à l'autre de façon qu'ils puissent être fondus, mélangés ou multiplexés sans différence détectable. Un multiplexeur (21) permet de commuter entre la version non codée et la version décodée du signal vidéo.
PCT/US2002/002676 2001-10-01 2002-01-29 Synchroniseur de video numerique a sorties analogique non decodee et numerique decodee WO2003030522A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/969,415 US7046299B1 (en) 2000-09-29 2001-10-01 Digital video synchronizer with both decoded digital and undecoded analog outputs
US09/969,415 2001-10-01

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WO2003030522A1 true WO2003030522A1 (fr) 2003-04-10

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060129728A1 (en) * 2004-12-09 2006-06-15 Hampel Craig E Memory interface with workload adaptive encode/decode
RU2606567C2 (ru) * 2015-02-16 2017-01-10 Общество С Ограниченной Ответственностью "Яндекс" Способ сравнения первого входящего аудиотрека с индексированным аудиотреком
US9558272B2 (en) 2014-08-14 2017-01-31 Yandex Europe Ag Method of and a system for matching audio tracks using chromaprints with a fast candidate selection routine
US9881083B2 (en) 2014-08-14 2018-01-30 Yandex Europe Ag Method of and a system for indexing audio tracks using chromaprints

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000134584A (ja) * 1998-10-26 2000-05-12 Sony Corp インターフェース装置及び映像信号処理方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000134584A (ja) * 1998-10-26 2000-05-12 Sony Corp インターフェース装置及び映像信号処理方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060129728A1 (en) * 2004-12-09 2006-06-15 Hampel Craig E Memory interface with workload adaptive encode/decode
US8356127B2 (en) * 2004-12-09 2013-01-15 Rambus Inc. Memory interface with workload adaptive encode/decode
US9558272B2 (en) 2014-08-14 2017-01-31 Yandex Europe Ag Method of and a system for matching audio tracks using chromaprints with a fast candidate selection routine
US9881083B2 (en) 2014-08-14 2018-01-30 Yandex Europe Ag Method of and a system for indexing audio tracks using chromaprints
RU2606567C2 (ru) * 2015-02-16 2017-01-10 Общество С Ограниченной Ответственностью "Яндекс" Способ сравнения первого входящего аудиотрека с индексированным аудиотреком

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