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WO2003036699A3 - Lateral semiconductor-on-insulator structure and corresponding manufacturing methods - Google Patents

Lateral semiconductor-on-insulator structure and corresponding manufacturing methods Download PDF

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Publication number
WO2003036699A3
WO2003036699A3 PCT/GB2002/004738 GB0204738W WO03036699A3 WO 2003036699 A3 WO2003036699 A3 WO 2003036699A3 GB 0204738 W GB0204738 W GB 0204738W WO 03036699 A3 WO03036699 A3 WO 03036699A3
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WO
WIPO (PCT)
Prior art keywords
bandgap semiconductor
manufacturing methods
insulator structure
corresponding manufacturing
lateral semiconductor
Prior art date
Application number
PCT/GB2002/004738
Other languages
French (fr)
Other versions
WO2003036699A2 (en
Inventor
Florin Udrea
Original Assignee
Cambridge Semiconductor Ltd
Florin Udrea
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cambridge Semiconductor Ltd, Florin Udrea filed Critical Cambridge Semiconductor Ltd
Priority to AU2002337297A priority Critical patent/AU2002337297A1/en
Publication of WO2003036699A2 publication Critical patent/WO2003036699A2/en
Publication of WO2003036699A3 publication Critical patent/WO2003036699A3/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/657—Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/421—Insulated-gate bipolar transistors [IGBT] on insulating layers or insulating substrates, e.g. thin-film IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02376—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02447—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

A semiconductor structure (10) has a low bandgap semiconductor layer (11), a buried insulator layer (12) below the low bandgap semiconductor layer (11), and a wide bandgap semiconductor substrate (13). The low bandgap semiconductor layer (11) may be for example silicon, SiGe, GaAs or a heterojunction. The wide bandgap semiconductor layer (13) may be for example silicon carbide or diamond. A semiconductor device may be made by bonding a wide bandgap semiconductor wafer (13) via an insulator layer (12) to a low bandgap semiconductor wafer (11) and subsequently forming a semiconductor device in the low bandgap semiconductor wafer (11).
PCT/GB2002/004738 2001-10-23 2002-10-21 Lateral semiconductor-on-insulator structure and corresponding manufacturing methods WO2003036699A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002337297A AU2002337297A1 (en) 2001-10-23 2002-10-21 Lateral semiconductor-on-insulator structure and corresponding manufacturing methods

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33050601P 2001-10-23 2001-10-23
US60/330,506 2001-10-23

Publications (2)

Publication Number Publication Date
WO2003036699A2 WO2003036699A2 (en) 2003-05-01
WO2003036699A3 true WO2003036699A3 (en) 2003-09-25

Family

ID=23290061

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/004738 WO2003036699A2 (en) 2001-10-23 2002-10-21 Lateral semiconductor-on-insulator structure and corresponding manufacturing methods

Country Status (2)

Country Link
AU (1) AU2002337297A1 (en)
WO (1) WO2003036699A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
US7612390B2 (en) 2004-02-05 2009-11-03 Cree, Inc. Heterojunction transistors including energy barriers
US9923059B1 (en) 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7033912B2 (en) 2004-01-22 2006-04-25 Cree, Inc. Silicon carbide on diamond substrates and related devices and methods
US7594075B2 (en) * 2004-10-20 2009-09-22 Seagate Technology Llc Metadata for a grid based data storage system
US7560322B2 (en) * 2004-10-27 2009-07-14 Northrop Grumman Systems Corporation Method of making a semiconductor structure for high power semiconductor devices
JP5017926B2 (en) 2005-09-28 2012-09-05 株式会社デンソー Semiconductor device and manufacturing method thereof
US20130154049A1 (en) * 2011-06-22 2013-06-20 George IMTHURN Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology
EP2880688B1 (en) * 2012-07-31 2020-07-15 Silanna Asia Pte Ltd. Power device integration on a common substrate
US10290702B2 (en) 2012-07-31 2019-05-14 Silanna Asia Pte Ltd Power device on bulk substrate
US9412881B2 (en) 2012-07-31 2016-08-09 Silanna Asia Pte Ltd Power device integration on a common substrate
CN104425257A (en) * 2013-08-30 2015-03-18 无锡华润上华半导体有限公司 Insulated gate bipolar transistor and manufacturing method thereof
FR3079662B1 (en) * 2018-03-30 2020-02-28 Soitec SUBSTRATE FOR RADIO FREQUENCY APPLICATIONS AND MANUFACTURING METHOD THEREOF
CN115706046A (en) * 2021-08-10 2023-02-17 苏州龙驰半导体科技有限公司 Composite structure of semiconductor wafer, semiconductor wafer and its manufacturing method and application

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1114497A (en) * 1965-06-28 1968-05-22 Dow Corning Improvements in or relating to semiconductor devices
US5441911A (en) * 1993-02-22 1995-08-15 Texas Instruments Incorporated Silicon carbide wafer bonded to a silicon wafer
EP0905767A1 (en) * 1997-09-26 1999-03-31 Shin-Etsu Handotai Company Limited Method of fabricating an SOI wafer and SOI wafer fabricated thereby
US6127243A (en) * 1998-03-12 2000-10-03 Siemens Aktiengesellschaft Method for bonding two wafers
EP1081748A2 (en) * 1999-08-30 2001-03-07 Lucent Technologies Inc. Etch stops and alignment marks for bonded wafers
US20010016399A1 (en) * 1999-02-22 2001-08-23 Harris Corporation Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1114497A (en) * 1965-06-28 1968-05-22 Dow Corning Improvements in or relating to semiconductor devices
US5441911A (en) * 1993-02-22 1995-08-15 Texas Instruments Incorporated Silicon carbide wafer bonded to a silicon wafer
EP0905767A1 (en) * 1997-09-26 1999-03-31 Shin-Etsu Handotai Company Limited Method of fabricating an SOI wafer and SOI wafer fabricated thereby
US6127243A (en) * 1998-03-12 2000-10-03 Siemens Aktiengesellschaft Method for bonding two wafers
US20010016399A1 (en) * 1999-02-22 2001-08-23 Harris Corporation Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method
EP1081748A2 (en) * 1999-08-30 2001-03-07 Lucent Technologies Inc. Etch stops and alignment marks for bonded wafers

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612390B2 (en) 2004-02-05 2009-11-03 Cree, Inc. Heterojunction transistors including energy barriers
US9035354B2 (en) 2004-02-05 2015-05-19 Cree, Inc. Heterojunction transistors having barrier layer bandgaps greater than channel layer bandgaps and related methods
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
US9923059B1 (en) 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
US10192989B2 (en) 2017-02-20 2019-01-29 Silanna Asia Pte Ltd Integrated circuit connection arrangement for minimizing crosstalk
US10249759B2 (en) 2017-02-20 2019-04-02 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
US10424666B2 (en) 2017-02-20 2019-09-24 Silanna Asia Pte Ltd Leadframe and integrated circuit connection arrangement
US10446687B2 (en) 2017-02-20 2019-10-15 Silanna Asia Pte Ltd Integrated circuit connection arrangement for minimizing crosstalk
US10546804B2 (en) 2017-02-20 2020-01-28 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
US11335627B2 (en) 2017-02-20 2022-05-17 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
US12159815B2 (en) 2017-02-20 2024-12-03 Silanna Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact

Also Published As

Publication number Publication date
WO2003036699A2 (en) 2003-05-01
AU2002337297A1 (en) 2003-05-06

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