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WO2003103035A1 - Procede pour produire un transistor a double grille - Google Patents

Procede pour produire un transistor a double grille Download PDF

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Publication number
WO2003103035A1
WO2003103035A1 PCT/DE2003/001726 DE0301726W WO03103035A1 WO 2003103035 A1 WO2003103035 A1 WO 2003103035A1 DE 0301726 W DE0301726 W DE 0301726W WO 03103035 A1 WO03103035 A1 WO 03103035A1
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WIPO (PCT)
Prior art keywords
layer
silicon
gate
double
forming
Prior art date
Application number
PCT/DE2003/001726
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German (de)
English (en)
Inventor
Richard Johannes Luyken
Franz Hofmann
Gürkan Ilicali
Wolfgang RÖSNER
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Infineon Technologies Ag
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Publication of WO2003103035A1 publication Critical patent/WO2003103035A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs

Definitions

  • the invention relates to a method for producing a double-gate transistor and in particular to a method for producing a self-aligned double-gate transistor.
  • a bulk transistor is a transistor in which the transistor is constructed by means of doping in the low-doped region of the complementary doping in each case.
  • a p-substrate is used, into which the NMOS transistor is implemented directly.
  • One possibility for a transistor with a channel length of 20 nm to 30 nm is the use of substrates which have a layer which is completely depleted of charge carriers (FD substrates).
  • double-gate transistor represents further scaling.
  • short-channel effects can be drastically reduced by the control action of two gates or a comprehensive gate (so-called “surrounded gate”). It is therefore assumed that double Gate transistors are essential components for terrabit integration [1], however, no simple manufacturing processes have yet been established for the production of double gate transistors.
  • a difficulty in the manufacture of a planar double-gate transistor is to ensure exact adjustment of the two respective gates in a double-gate transistor, in other words, that the two gates of the transistor are arranged in a fixed spatial relationship to one another.
  • the two gates of the transistor are arranged on both sides of a channel region of the transistor, which is arranged between the source and drain connection. In the case of a planar double-gate transistor, this means that the two gates of the transistor are arranged one above the other at the same location on the substrate are, the channel region being arranged between the two gates.
  • DE 692 26 687 T2 discloses a method for producing a double-gate transistor.
  • a gate is applied to a first substrate, a second substrate is bonded, the first substrate is polished on the exposed surface, and a second gate is then formed on this polished surface.
  • US 5 899 710 discloses a method of manufacturing a transistor with at least three gates and DE 100 52 131 AI discloses a method of manufacturing a field effect transistor using a self-adjusting technique.
  • the invention is based on the problem of creating a simple production method for a planar double-gate transistor, in which known and simple method steps of silicon technology can be used.
  • a first gate region of a double-gate transistor is formed on a silicon-on-insulator (SOI) substrate of a first wafer.
  • the wafer preferably has a carrier layer made of silicon.
  • the SOI substrate which preferably has an insulator layer made of silicon oxide and a silicon layer formed thereon, is arranged on this carrier layer.
  • An additional step of the method is the formation of a layer with a flat surface over the SOI substrate and the formed first gate area. To this tarpaulin
  • a second wafer preferably a silicon wafer, is then bonded to the surface.
  • the second gate region is formed in the SOI substrate of the first wafer. This is opposite the first gate area and, together with the first gate area, forms the double gate of the double gate transistor.
  • a planar double-gate transistor is produced in a simple and inexpensive manner using known method steps in silicon technology.
  • the method according to the invention for producing a double-gate transistor preferably has the following sub-steps.
  • An active region is defined on the silicon layer of the SOI substrate by means of photolithography and etching the layer of silicon of the SOI substrate.
  • a first gate insulating layer is formed on the silicon of the SOI substrate. Silicon oxide is preferably used as the material of the first gate-insulating layer, which is preferably formed by means of thermal oxidation of a part of the layer of silicon of the SOI substrate.
  • a first layer of electrically conductive material is subsequently formed on the first gate insulating layer.
  • Doped polysilicon which is deposited on the first gate insulating layer, is preferably used as the material of the first electrically conductive layer.
  • a first layer made of an electrically non-conductive material preferably silicon nitride, is formed on the first layer made of electrically conductive material. This first layer of electrically non-conductive material is part of an insulation and encapsulation of the first gate region.
  • An additional sub-step of the method is a photolithographic definition of the gate region with subsequent structuring of the first layer made of an electrically conductive material and the first layer made of an electrically non-conductive material. This structuring is preferably carried out by means of anisotropic etching.
  • first side wall layers are formed on the remaining layer made of electrically conductive material and the remaining layer made of electrically non-conductive material.
  • the first sidewall layers are preferably also formed from silicon nitride and are a second part of the insulation and encapsulation of the first Gate region.
  • the first side wall layers are preferably formed by conformal deposition of an electrically non-conductive layer and subsequent anisotropic recessing of this electrically non-conductive layer.
  • the following sub-steps essentially serve to prepare the first wafer for the subsequent wafer bonding.
  • the layer of silicon of the SOI substrate and the insulator layer of the SOI substrate are structured. Structuring the
  • Silicon layer which is preferably a layer completely depleted of charge carriers (FD layer), of the SOI substrate and the insulator layer of the SOI substrate is preferably carried out by means of anisotropic etching.
  • the encapsulation of the first gate is used as a mask for this anisotropic etching.
  • a surface area of the silicon layer of the SOI substrate is exposed by means of this anisotropic etching.
  • the exposed surface area of the silicon layer is subsequently oxidized in an additional sub-step.
  • an auxiliary layer is applied, which is preferably made of undoped polysilicon and which is subsequently planarized.
  • the planarization is preferably carried out by means of chemical mechanical polishing (CMP).
  • a second layer of an electrically non-conductive material is applied to this flat surface. Silicon oxide is preferably used as the material of the second layer made of an electrically non-conductive material.
  • An additional sub-step of the method for producing a double-gate transistor is the bonding of a second wafer to the second layer made of an electrically non-conductive material.
  • the second wafer is preferably made of silicon.
  • the carrier layer of the first wafer is subsequently removed.
  • a surface of the insulator layer of the SOI substrate is exposed for further processing, which exposed surface was coupled to the carrier layer before the carrier layer of the first wafer was removed.
  • a sub-step for forming the second gate is structuring the exposed surface of the
  • Insulator layer of the SOI substrate This structuring is preferably carried out by means of etching, particularly preferably by means of wet chemical etching. This structuring exposes the silicon layer of the SOI substrate.
  • a subsequent sub-step of the method is to define the active area by structuring the exposed silicon layer of the SOI substrate. The structuring of the exposed silicon layer of the SOI substrate is preferably carried out by means of photolithography and subsequent etching of the exposed silicon layer of the SOI substrate.
  • a next sub-step is the formation of a thin layer of electrically non-conductive material, as which material silicon oxide is preferably used. Below are second Sidewall layers of an electrically non-conductive material are formed in the active area on the thin layer of electrically non-conductive material.
  • the second side wall layers are preferably formed from an electrically non-conductive material by means of conformal deposition and subsequent anisotropic etching back of a layer of silicon nitride.
  • a next sub-step of the method is the partial removal of the thin layer from an electrically non-conductive material.
  • the formation of the second gate insulating layer is preferably carried out by means of thermal oxidation of parts of the exposed silicon layer of the SOI substrate. With the partial steps described, the exposure of the area for the second gate is essentially completed.
  • a second layer of electrically conductive material is formed in the active region.
  • the second layer of electrically conductive material is preferably formed by depositing a layer of doped polysilicon and forms the second gate of the double gate transistor. Planarization is then carried out. The planarization is preferably carried out by means of chemical mechanical polishing. An additional sub-step is etching back the second layer from an electrically conductive material.
  • a second passivation layer is formed from an electrically non-conductive material over the active area.
  • the second passivation layer serves to encapsulate the second gate of the double-gate transistor.
  • the second passivation layer is preferably formed by depositing silicon nitride. Planarization is then carried out. Chemical mechanical polishing is preferably used for this planarization.
  • the separation and encapsulation of the second gate is essentially completed with the partial steps described.
  • the oxidized exposed surface area of the silicon layer of the SOI substrate is subsequently removed. Parts of the silicon layer of the SOI substrate, which silicon layer forms a channel region of the double-gate transistor, are thereby exposed.
  • source / drain connections are produced by forming a third layer made of electrically conductive material.
  • Doped polysilicon is preferably used as the material of the third layer made of electrically conductive material.
  • Subareas of the third layer made of electrically conductive material represent the source / drain connections of the double gate transistor according to the invention.
  • a surface of the double gate transistor, which was produced by means of a method according to the invention is planarized. The planarization is preferably carried out by means of chemical mechanical polishing.
  • the source / drain connections are produced by third sidewall layers made of electrical on the first gate and the second gate conductive material are formed.
  • the third side wall layers are preferably formed from an electrically conductive material by means of deposition of polysilicon.
  • a metal is then sputtered on.
  • the metal is preferably titanium.
  • a third passivation layer is then formed.
  • the third passivation layer is preferably formed by depositing silicon oxide.
  • a surface of the double gate transistor, which was produced by means of a method according to the invention is planarized. The planarization is preferably carried out by means of chemical mechanical polishing.
  • silicidation is carried out after the metal has been sputtered on.
  • the first and / or second gate insulating layer can be formed as a charge storage layer (charge trapping layer).
  • the first and / or the second gate insulating layer are particularly preferably formed as ONO layers.
  • the first gate area and the second gate area are preferably electrically decoupled from one another, so that they can be controlled separately from one another.
  • Standard processes of back-end technology are used for subsequent contacting of the double-gate transistor, which was produced by means of a method according to the invention.
  • An additional subject of the application relates to a double gate memory transistor with two Charge storage layers (charge trapping layers), a method for producing a double-gate storage transistor with two charge-storage layers and the arrangement of such double-gate storage transistors in an array.
  • memory transistors are created which have a so-called floating gate for storing information.
  • One bit per memory transistor can be stored by means of these memory transistors.
  • memory transistors are created which have an ONO layer as gate-insulating layer, ie a layer sequence of a first silicon oxide layer Si0 2 , a silicon nitride layer Si 3 N 4 and a second silicon oxide layer Si0 2 .
  • This ONO layer is used to store charge carriers and forms a charge storage layer (charge trapping layer).
  • ONO layer When a so-called ONO layer is used as the charge storage layer, it is possible to store two bits in a memory transistor, the two SiO 2 regions being able to be used separately for storing one bit each.
  • a problem in the course of constant further development in the area of memory transistors is the memory power per required area of the memory transistor, i.e. increasing the storage density and simplifying the current manufacturing processes.
  • a method for producing a memory transistor has the following steps.
  • a first gate area on one Silicon-on-insulator substrate of a first wafer is formed, with a first gate-insulating layer being formed as a charge storage layer.
  • a layer with a flat surface is formed over the silicon-on-insulator substrate and the first gate region and a second wafer is bonded to the flat surface of the first wafer.
  • a second gate region opposite the first gate region is formed in the silicon-on-insulator substrate, a second gate-insulating layer being formed as a charge storage layer and the first and second gate regions being decoupled from one another.
  • a double gate memory transistor has two gates lying on opposite sides of a channel region, each gate insulating layer being designed in such a way that it can be used as a charge storage layer, the two gates of the double gate memory transistor being different from one another are decoupled that they can be controlled separately.
  • An arrangement of double-gate memory transistors has a memory cell array with double-gate memory transistors according to the invention, which are arranged in an array.
  • the first gates of the double gate memory transistors of the array are electrically coupled to one another row by row on a first main side of the array, first word lines being formed, while the second gates of the double gate memory transistors on the second main side of the array are row by row are coupled to one another, second word lines being formed.
  • the Silicon technology produced a planar double-gate memory transistor in a simple and inexpensive manner.
  • this double-gate storage transistor it is possible to achieve a storage density which is doubled compared to the prior art, since the two gates can be controlled separately from one another and thus the charge storage layers can be used separately as storage devices.
  • the charge storage layer is understood to be a so-called charge trapping layer, as is used, for example, in floating gate transistors for storing charge.
  • Forming the first gate region on the silicon-on-insulator substrate can have the substep of forming the first gate-insulating layer on the silicon-on-insulator substrate. Furthermore, it can comprise the formation and structuring of a first layer made of an electrically conductive material on the first gate-insulating layer and the partial encapsulation of the first gate region with an electrically non-conductive material.
  • the method preferably has the partial encapsulation of the first gate region, the formation of a first passivation layer and the formation of first side wall layers from an electrically non-conductive material.
  • Silicon nitride is particularly preferably used as the electrically non-conductive material of the partial encapsulation of the first gate region.
  • the first gate insulating layer is preferably produced from silicon oxide.
  • the first layer is preferably produced from an electrically conductive material made of doped polysilicon.
  • the method for forming a layer with a flat surface preferably has the following sub-steps. Structuring the silicon layer of the silicon-on-insulator substrate and the insulator layer of the silicon-on-insulator substrate, whereby an exposed surface area of the silicon layer of the silicon-on-insulator substrate is obtained, oxidizing the exposed surface area, forming an auxiliary layer with a flat surface, and forming a first layer of electrically non-conductive material at least on the flat surface of the auxiliary layer.
  • the partial encapsulation of the first gate region is preferably used as a mask for structuring the silicon layer of the silicon-on-insulator substrate and the insulator layer of the silicon-on-insulator substrate.
  • the bonding of the second wafer can comprise the steps of bonding the second silicon wafer on the first layer made of a non-conductive material and removing a carrier layer of the first wafer.
  • the formation of the second gate region can have the following steps, structuring the insulator of the silicon-on-insulator substrate and exposing the silicon layer of the silicon-on-insulator substrate, structuring the silicon of the silicon-on-insulator substrate as an active region, forming a thin non-conductive layer, forming second side wall layers from a non-conductive material and forming the second gate insulating layer as a charge-adhering layer.
  • the second sidewall layers can be made from silicon nitride.
  • the method for forming the second gate preferably further comprises the following sub-steps, forming a second layer from an electrically conductive material in the active region, forming a second passivation layer over the active region and then planarizing.
  • the third layer can be made of an electrically conductive material made of doped polysilicon.
  • the method may further include the steps of removing a portion of the thin non-conductive layer, Removing the auxiliary layer, removing the oxidized, exposed surface area of the silicon layer of the silicon-on-insulator substrate, forming two source / drain regions by forming third side wall layers from an electrically conductive material on the first gate and on the second gate, sputtering a metal onto the third sidewall layers made of a conductive material, forming a third passivation layer and then planarizing.
  • Polysilicon which is silicided after sputtering on the metal, is preferably used as the conductive material of the third side wall regions.
  • the first and / or the second gate insulating layer are particularly preferably formed as ONO layers.
  • the storage density of the double-gate storage transistor can be increased compared to a storage transistor with a floating gate.
  • the first gate area and the second gate area are preferably electrically decoupled from one another.
  • the two charge storage layers can be controlled independently of one another by means of the gate belonging to the respective charge storage layer.
  • a separation of gate leads (word lines) at different levels of the double gate memory transistor is possible with wafer bonding technology without difficulty. This results in an additional increase in storage density.
  • a double gate Memory transistor four bits of information can be stored.
  • the first word lines are preferably fed in a first direction, while the second word lines are fed in the opposite direction to the first direction.
  • the source / drain connections of the double-gate memory transistors of one column of the arrangement are preferably coupled to one another such that the source connection of a double-gate memory transistor is connected to the drain connection of an adjacent one Double gate memory transistor is coupled to the same column of the arrangement.
  • the source connections of the double-gate memory transistors of one column of the arrangement can be coupled by means of a bit line to the source connections of other double-gate memory transistors of the same column of the arrangement, while the drain connections the double-gate memory transistors of a column of the arrangement are coupled by means of a bit line to the drain connections of other double-gate memory transistors of the same column of the arrangement.
  • each double-gate memory transistor of the arrangement can be individually programmed. Programming is possible using Fowler Nordheim Tunnels as well as Channel Hot Electron Tunnels. This enables NROM-like operation of the double-gate memory transistors of the arrangement. 1 o
  • the source connections of the double-gate memory transistors in one column of the arrangement are coupled to the drain connections of the double-gate memory transistors in an adjacent column of the arrangement by means of coupling lines, the coupling lines of double gate memory transistors of the same columns are coupled by means of a bit line.
  • Possible methods of deposition which can be used according to the invention are e.g. Epitaxy, Chemical Vapor Deposition, Plasma Enhanced Chemical Vapor Deposition, Sputtering and Molecular Beam Epitaxy.
  • a planar, self-aligned double-gate transistor is created by means of simple, known, proven and inexpensive process steps.
  • the method is a self-aligning method and the first gate region and the second gate region lie exactly opposite one another.
  • FIG. 1 is a schematic cross-sectional illustration of a
  • FIG. 2 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional sub-steps for preparing a wafer bonding of a method according to an exemplary embodiment of the invention
  • FIG. 3 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional
  • Fig. 4 is a schematic cross-sectional illustration of a layer arrangement according to the invention after additional
  • FIG. 5 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional sub-steps of a method according to an exemplary embodiment of the invention, which serve to separate and encapsulate the second gate;
  • FIG. 6A shows a schematic cross-sectional illustration of a layer arrangement according to the invention after partial steps of a method according to a Embodiment of the invention, which are used to form source / drain connections of the double gate transistor;
  • 6B shows a schematic cross-sectional illustration of a layer arrangement according to the invention after partial steps of an additional method according to an exemplary embodiment of the invention, which serve to form source / drain connections of the double-gate transistor.
  • Fig. 7 is a schematic cross-sectional illustration of a
  • Embodiment was formed, which layer arrangement has a first gate
  • FIG. 8 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional
  • FIG. 9 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional sub-steps of a method according to the additional exemplary embodiment
  • FIG. 10 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional sub-steps of a method according to the additional exemplary embodiment, which a Expose an area for a second gate;
  • FIG. 11 shows a schematic cross-sectional illustration of a layer arrangement according to the invention after additional
  • FIG. 12A shows a schematic cross-sectional illustration of a layer arrangement according to the invention after partial steps of a method according to the additional exemplary embodiment, which serve to form source / drain connections of the double-gate memory transistor;
  • FIG. 12B shows a schematic cross-sectional illustration of a layer arrangement according to the invention after partial steps of an additional method according to a second additional exemplary embodiment, which serve to form source / drain connections of the double-gate memory transistor;
  • Fig. 13 is a schematic cross-sectional illustration of a layer arrangement according to the invention, which the
  • 17 shows a third arrangement in which double-gate memory transistors can be arranged.
  • FIG. 1 shows a layer arrangement according to the invention which has a first gate.
  • the layer arrangement has an SOI substrate applied to a first silicon wafer 100.
  • the SOI substrate has an insulator layer made of silicon oxide 101 and a silicon layer 102.
  • An active region is defined on the silicon layer 102 for a subsequent formation of the first gate.
  • the active region is defined by means of photolithography and subsequent etching of the silicon layer 102 of the SOI substrate.
  • a first gate insulating layer 103 made of silicon oxide is formed by means of thermal oxidation of the silicon layer 102 of the SOI substrate.
  • a first layer 104 of doped is subsequently
  • Polysilicon is formed on the first gate insulating layer 103.
  • the first layer 104 of doped polysilicon is the layer which forms the first gate of the double-gate transistor after further sub-steps.
  • a first passivation layer 105 made of silicon nitride is formed on the layer 104 made of doped polysilicon.
  • the first passivation layer 105 made of silicon nitride forms part of an encapsulation of the first gate.
  • An additional sub-step of the method is the photolithographic definition of the first gate area.
  • the first passivation layer 105 made of silicon nitride and the first layer 104 made of doped polysilicon are then etched back in the regions which should not belong to the first gate region by means of anisotropic etching.
  • first sidewall layers 106 i.e. Spacer 106, produced from silicon nitride, which represent a further part of the encapsulation of the first gate.
  • Figure 2 shows the layer arrangement according to the invention after additional sub-steps, which serve to prepare a wafer bonding.
  • FIG. 2 shows the layer arrangement of FIG. 1 after partial areas of the layer 102 made of silicon of the SOI substrate and partial areas of the insulator layer 101 made of silicon oxide of the SOI substrate have been removed by means of anisotropic etching.
  • the anisotropic etching mask for removing the partial areas of the layer 102 made of silicon and the insulator layer 101 of the SOI substrate uses the encapsulation of the first gate, which has the first passivation layer 105 made of silicon nitride and the first side wall layers 106 made of silicon nitride.
  • partial regions 207 of the layer 102 made of silicon of the SOI substrate are exposed.
  • these exposed partial areas 207 of the layer 102 made of silicon are oxidized.
  • An additional substep is the deposition of an auxiliary layer 208 made of undoped polysilicon in the areas of the layer arrangement which do not belong to the active area. Then a surface 219 of the auxiliary layer 208, which is at the top in FIG. 2, is
  • a first layer 209 of silicon oxide is subsequently deposited on the planarized surface 219 of the auxiliary layer and on the upper surface of the encapsulation, in other words on the exposed surface of the first passivation layer 105.
  • FIG. 3 shows the layer arrangement according to the invention after additional sub-steps which relate to wafer bonding.
  • FIG. 3 shows the layer arrangement of FIG. 2 after a second silicon wafer 310 has been bonded to the planarized surface.
  • the first silicon wafer 100 was removed.
  • FIGS. 3 to 5, 6A and 6B show the layer arrangement of FIGS. 1 and 2 rotated through 180 ° in the paper plane.
  • the two thermally oxidized silicon wafers which are pressed against each other under pressure and thereby have weak adhesion, are mechanically firmly coupled to one another.
  • the mechanically strong coupling takes place according to this embodiment by means of a
  • Temperature step are carried out.
  • thermal oxidation is carried out in a pure oxygen atmosphere at about 1000 ° C.
  • anionic bonding the coupling of the wafers is assisted by means of an electrical field and is carried out at a relatively low temperature of approximately 500 ° C.
  • FIG. 4 shows the layer arrangement according to the invention after additional sub-steps to expose an area for a second gate.
  • FIG. 4 shows the layer arrangement of FIG. 3 after the insulator layer 101 made of silicon oxide of the SOI substrate has been removed by means of wet chemical etching.
  • An additional sub-step is the definition of the active area by means of photolithography and subsequent etching of the layer 102 made of silicon of the SOI substrate.
  • a thin layer 411 made of silicon oxide is then applied to the layer arrangement according to the invention.
  • second side wall layers 412 made of silicon nitride are produced by means of conformal deposition of silicon nitride and subsequent anisotropic etching back of the conformally deposited silicon nitride.
  • the thin layer 411 of silicon oxide is then removed in the active region.
  • An additional substep is the formation of a second gate insulating layer 413 for the second gate.
  • the layer 102 made of silicon of the SOI substrate is thermally oxidized.
  • FIG. 5 shows the layer arrangement according to the invention after further sub-steps which relate to deposition and encapsulation of the second gate.
  • FIG. 5 shows the layer arrangement of FIG. 4 after a second layer 514 of doped in the active region
  • This second layer 514 of doped polysilicon forms the second gate of the planar double-gate transistor. It is then chemically and mechanically polished and the second layer 514 made of doped polysilicon is etched back. An additional sub-step is the deposition of a second passivation layer 515 made of silicon nitride. The surface, which is shown in FIG. 5 above, is then planarized by means of chemical mechanical polishing. The separation and encapsulation of the second gate is completed with these method steps according to the invention.
  • FIG. 6A shows the layer arrangement according to the invention after additional sub-steps of a first exemplary embodiment of the invention, which sub-steps form an embodiment of
  • FIG. 6A shows the layer arrangement of FIG. 5 after the thin layer 411 of silicon oxide has been removed in the regions which do not belong to the active region.
  • An additional substep is the removal of the auxiliary layer 208 from undoped polysilicon and the removal of the exposed, oxidized partial regions 207 of the layer 102 from silicon of the SOI substrate.
  • a third layer 616 made of doped polysilicon is applied to source / drain connections.
  • the surface arranged at the top in FIG. 6A is then planarized by means of chemical mechanical polishing.
  • FIG. 6B shows the layer arrangement according to the invention after additional sub-steps of a second exemplary embodiment of the invention, which sub-steps relate to the formation of source / drain connections.
  • FIG. 6B shows the layer arrangement of FIG. 5 after the thin layer 411 made of silicon oxide has been removed in the regions which do not belong to the active region.
  • An additional sub-step is the removal of the auxiliary layer 208 from undoped polysilicon and the removal of the exposed, oxidized partial regions 207 of the layer 102 from silicon of the SOI substrate.
  • third side wall layers 617 made of polysilicon are deposited in the second exemplary embodiment. Titanium is subsequently sputtered onto the third sidewall layers 617 made of polysilicon.
  • parts of the third side wall layers 617 are silicided. Silicidized areas 618 of the third side wall layers are formed.
  • a layer of silicon oxide (not shown in FIG. 6B) is subsequently deposited and the layer arrangement is then planarized by means of chemical mechanical polishing.
  • the invention relates to a method for
  • FIGS. 7 to 13B the essential sub-steps of a method that is independent of the previously described method are described.
  • the figures relate to the additional subject matter of the application, a method for producing a double-gate memory transistor, in which method steps of the method described with reference to FIGS. 1 to 6B are slightly modified.
  • a method for producing a self-aligned planar double-gate memory transistor according to an additional exemplary embodiment is described and explained in more detail.
  • FIG. 7 shows a layer arrangement according to the invention which has a first gate.
  • the layer arrangement has an SOI substrate applied to a first silicon wafer 700.
  • the SOI substrate has an insulator layer made of silicon oxide 701 and a silicon layer 702.
  • An active region of the double-gate memory transistor is defined on the silicon layer 702.
  • the active region is defined by means of a first photolithography process and subsequent etching of the silicon layer 702 of the SOI substrate.
  • the area in which the definition of the first active area is shown in FIG. 14 and is identified by reference numeral 1460.
  • a silicon nitride layer 1350 (only visible in FIG. 13) is deposited, which is then planarized, preferably by means of chemical mechanical polishing.
  • the silicon layer 702 is preferably used as a stop layer.
  • the silicon nitride layer 1350 is used for the electrical decoupling of the double-gate memory transistors.
  • a first ONO layer 703 is then formed in a substep. For this purpose, a first silicon oxide layer 720 of the ONO layer is first formed, on which a silicon nitride layer 721 of the ONO layer is then formed, on which in turn a final second silicon oxide layer 722 of the ONO layer is formed.
  • a first layer 704 of doped polysilicon is subsequently formed on the first ONO layer 703.
  • the first layer 704 made of doped polysilicon is the layer which forms the first gate of the double-gate memory transistor after further sub-steps.
  • a first passivation layer 705 made of silicon nitride is formed on the layer 704 made of doped polysilicon.
  • Passivation layer 705 has a sufficient thickness that it is not completely removed in a subsequent etching to form spacers.
  • the first passivation layer 705 made of silicon nitride forms part of an encapsulation of the first gate.
  • Part of the method is defining the first gate area, which is carried out with a second photolithographic process step.
  • the area of this 14 is denoted by reference numeral 1461 in FIG.
  • the first passivation layer 705 made of silicon nitride and the first layer 704 made of doped polysilicon are then etched back in the regions which do not belong to the first gate region by means of anisotropic etching.
  • the etching is carried out in such a way that partial regions of the ONO layer 703 and the silicon nitride layer 1350 which are located on the buried silicon oxide layer 702 are removed.
  • FIG. 8 shows the layer arrangement according to the invention after additional sub-steps, which serve to prepare a wafer bonding.
  • FIG. 8 shows the layer arrangement of FIG. 7 after partial regions of the ONO layer 703, the layer 702 made of silicon of the SOI substrate and partial regions of the insulator layer 701 made of silicon oxide of the SOI substrate have been removed by means of anisotropic etching.
  • the mask is used as the mask for the anisotropic etching to remove the partial regions of the layer 702 made of silicon and the insulator layer 701 of the SOI substrate
  • Encapsulation of the first gate which has the first passivation layer 705 made of silicon nitride and the first side wall layers 706 made of silicon nitride, is used.
  • partial areas 807 of the layer 702 made of silicon of the SOI substrate are exposed.
  • the etching of the silicon oxide layers 720, 722 and 702 is preferably carried out selectively with respect to silicon nitride.
  • these exposed partial areas 807 of the layer 702 made of silicon are oxidized.
  • An additional substep is the deposition of an auxiliary layer 808 made of undoped polysilicon in the areas of the layer arrangement which do not belong to the active area. Then a surface 819 of the auxiliary layer 808, which is at the top in FIG. 8, is
  • a first layer 809 of silicon oxide is subsequently deposited on the planarized surface 819 of the auxiliary layer and on the upper surface of the encapsulation, in other words on the exposed surface of the first passivation layer 705.
  • FIG. 9 shows the layer arrangement according to the invention after additional sub-steps which relate to wafer bonding.
  • FIG. 9 shows the layer arrangement of FIG. 8 after a second silicon wafer 910 has been bonded to the planarized surface.
  • the first silicon wafer 700 was removed.
  • FIGS. 9 to 11, 12A and 12B show the layer arrangement of FIGS. 7 and 8 rotated by 180 ° in the paper plane.
  • the two thermally oxidized silicon wafers which are pressed against each other under pressure and thereby have weak adhesion, are mechanically firmly coupled to one another.
  • the mechanically strong coupling takes place according to this embodiment by means of a
  • thermal oxidation is carried out in a pure oxygen atmosphere at about 1000 ° C.
  • anionic bonding the coupling of the wafers is assisted by means of an electrical field and is carried out at a relatively low temperature of approximately 500 ° C.
  • FIG. 10 shows the layer arrangement according to the invention after additional sub-steps to expose an area for a second gate.
  • FIG. 10 shows the layer arrangement of FIG. 9 after the insulator layer 701 made of silicon oxide of the SOI substrate has been removed by means of wet chemical etching.
  • An additional sub-step is the definition of the active area by means of photolithography and subsequent etching of the layer 702 made of silicon of the SOI substrate.
  • a thin layer 1011 of silicon oxide is then applied to the layer arrangement according to the invention.
  • second side wall layers 1012 made of silicon nitride are produced by means of conformal deposition of silicon nitride and subsequent anisotropic etching back of the conformally deposited silicon nitride.
  • the thin layer 1011 of silicon oxide is then removed in the active region.
  • An additional substep is the formation of a second gate insulating layer 1013 for the second gate, which as second ONO layer 1013 is formed from a first silicon oxide layer 1023 of the second ONO layer, a silicon nitride layer 1024 of the second ONO layer and a second silicon oxide layer 1025 of the second ONO layer.
  • second ONO layer 1013 is formed from a first silicon oxide layer 1023 of the second ONO layer, a silicon nitride layer 1024 of the second ONO layer and a second silicon oxide layer 1025 of the second ONO layer.
  • FIG. 11 shows the layer arrangement according to the invention after further sub-steps which relate to deposition and encapsulation of the second gate.
  • FIG. 11 shows the layer arrangement of FIG. 10 after a second layer 1114 made of doped polysilicon has been deposited in the active region. This second layer 1114 of doped polysilicon forms the second gate of the planar
  • Double-gate storage transistor It is then chemically and mechanically polished and the second layer 1114 made of doped polysilicon is etched back. Sub-regions of the second silicon oxide layer 1025 of the second ONO layer 1013 are then etched back, so that sub-regions of the side wall layers 1012 made of silicon nitride are exposed.
  • An additional sub-step is the deposition of a second passivation layer 1115 made of silicon nitride.
  • the surface, which is shown in FIG. 11 above, is then planarized by means of chemical mechanical polishing.
  • the auxiliary layer made of polysilicon layer 808 preferably serves as a stop layer.
  • An additional third photolithographic step is also carried out.
  • the area in which the third photolithography step is carried out is provided with the reference number 1462 in FIG. 14.
  • This photolithography step serves to decouple the two gates of the double-gate memory transistor.
  • the active area is covered and the auxiliary layer made of polysilicon 808 is subsequently etched.
  • a second layer of silicon oxide is then deposited in the etched-back regions and then planarized, preferably by means of chemical mechanical polishing.
  • the second passivation layer made of silicon nitride 1115 is preferably used as a stop layer during planarization.
  • FIG. 12A shows the layer arrangement according to the invention after additional sub-steps of an additional one
  • FIG. 12A shows the layer arrangement of FIG. 11 after the thin layer 1011 of silicon oxide has been removed in the regions which do not belong to the active region.
  • An additional substep is the removal of the auxiliary layer 808 from undoped polysilicon and that
  • a third layer 1216 made of doped polysilicon is applied to form the source / drain connections.
  • the surface arranged at the top in FIG. 12A is then planarized, preferably by means of chemical mechanical polishing.
  • FIG. 12B shows the layer arrangement according to the invention after additional sub-steps of a second additional one Embodiment of the invention, which substeps relate to the formation of source / drain connections.
  • FIG. 12B shows the layer arrangement of FIG. 11 after the thin layer 1011 made of silicon oxide has been removed in the regions which do not belong to the active region.
  • An additional sub-step is the removal of the auxiliary layer 808 from undoped polysilicon and the removal of the exposed, oxidized partial regions 807 of the layer 702 from silicon of the SOI substrate.
  • third side wall layers 1217 made of polysilicon are deposited to form the source / drain connections. Titanium is subsequently sputtered onto the third side wall layers 1217 made of polysilicon.
  • parts of the third side wall layers 1217 are silicided. This produces silicided areas 1218 of the third side wall layers.
  • a layer of silicon oxide (not shown in FIG. 12B) is subsequently deposited and then the layer arrangement is preferably planarized by means of chemical mechanical polishing.
  • FIG. 13 shows the layer arrangement of FIG. 12A or FIG. 12B in a cross section perpendicular to the representation in these figures.
  • the second silicon wafer 910 can be seen.
  • the first layer of silicon oxide 809 is on the second silicon wafer 910 educated.
  • the layers of the first ONO layer 703, ie the second silicon oxide layer 722 of the ONO layer, the silicon nitride layer 721 of the ONO layer and the first silicon oxide layer 720 of the ONO layer are shown.
  • the silicon layer 702 of the SOI substrate, which forms the channel region of the double-gate memory transistor, can be seen in partial regions on the first ONO layer 703. Subsequently, in FIG.
  • the silicon nitride layer 1350 serves to decouple the two gates of the double-gate memory transistor.
  • the second ONO layer 1013 which is formed from the first silicon oxide layer 1023 of the second ONO layer 1013, the silicon nitride layer 1024 of the second ONO layer 1013 and the second silicon oxide layer 1025 of the second ONO layer , educated.
  • the second layer of doped polysilicon 1114 which forms the second gate of the double-gate memory transistor, is shown. This in turn shows the second passivation layer 1115 made of silicon nitride.
  • FIG. 14 the various areas in which photolithographic process steps are carried out and the cutting lines along which the cross sections of FIGS. 7 to 13 are carried out are shown to illustrate the various areas.
  • the area denoted by reference numeral 1460 represents the area in which the process steps of the first photolithographic process, ie the definition of the active area of the double-gate memory transistor, are carried out.
  • the one designated by reference numeral 1461 Area represents the area in which the process steps of the second photolithographic process, ie the definition of the gate region of the double-gate memory transistor, are carried out.
  • the region denoted by reference numeral 1462 represents the region in which the process steps of the third photolithographic process, ie the covering of the active region of the double-gate memory transistor, are carried out.
  • FIG. 14 the section line along which the cross sections of FIGS. 7 to 12B are shown is designated A-A, while the section line along which the cross section of FIG. 13 is shown is designated B-B.
  • FIG. 15 shows a first arrangement in which double-gate memory transistors can be arranged.
  • the arrangement has a plurality of double-gate memory transistors in accordance with a so-called NAND arrangement of memory transistors.
  • the gate connections of each row of double-gate memory transistors are usually coupled to one another by means of a word line 1570, 1571 and 1572.
  • a word line 1570, 1571 and 1572 In the arrangement of double-gate memory transistors according to the invention, however, it should be noted that only the gates of a first main page, located at the top in FIG. 15, of the arrangement are coupled to one another.
  • bit lines 1576, 1577 and 1578 are formed in that the source connection of a double-gate memory transistor in one column is coupled to the drain connection of a double-gate memory transistor adjacent in the column. All source / drain connections of the double-gate memory transistors in a column of the arrangement are thus driven by means of a bit line.
  • FIG. 16 shows a second arrangement in which double-gate memory transistors can be arranged.
  • the arrangement has a plurality of double-gate memory transistors in accordance with a so-called AND arrangement of memory transistors.
  • the gate connections of each row of double-gate memory transistors are coupled to one another by means of a word line 1670, 1671 and 1672.
  • a word line 1670, 1671 and 1672 In the arrangement of double-gate memory transistors according to the invention, however, it should be noted that only the gates of a first main page, located at the top in FIG. 16, of the arrangement are coupled to one another.
  • Lines of the opposite second main side of the arrangement, lying at the bottom in FIG. 16, are coupled to one another by means of additional word lines 1673, 1674 and 1675.
  • the source and drain connections of the double-gate memory transistors of a column are coupled to one another in a manner customary for an AND arrangement.
  • Bit lines 1676, 1677 and 1678 are formed by the source connection each double-gate memory transistor of a column is coupled by means of a bit line to the source of every other double-gate memory transistor arranged in the column. All source connections of the double-gate memory transistors in a column of the arrangement are thus driven by means of a bit line.
  • bit lines 1679, 1680 and 1681 are formed in that the drain connection of each double gate memory transistor of a column is coupled by means of a bit line to the drain connection of each other double gate memory transistor arranged in the column. All drain connections of the double-gate memory transistors in a column of the arrangement are thus driven by means of a bit line.
  • each double-gate memory transistor can be controlled individually. Programming of the individual double-gate memory transistors is possible both by means of so-called Fowler Nordheim tunnels and by means of so-called channel hot electron tunnels. This also enables NROM-like operation of the double-gate memory transistors of the arrangement.
  • FIG. 17 shows a second arrangement in which double-gate memory transistors can be arranged.
  • the arrangement has a plurality of double-gate memory transistors in accordance with a so-called AND arrangement of memory transistors with virtual ground.
  • the arrangement is similar to the arrangement shown in FIG. 16, except that one bit line of the source connections of the double gate memory transistors of one column is combined with one bit line of the drain connections of the double gate memory transistors of an adjacent column.
  • the gate connections of each row of double-gate memory transistors are coupled to one another by means of a word line 1770, 1771 and 1772.
  • a word line 1770, 1771 and 1772 In the arrangement of double-gate memory transistors according to the invention, however, it should be noted that only the gates of a first main page, located at the top in FIG. 17, of the arrangement are coupled to one another.
  • Rows of the opposite second main side of the arrangement, lying at the bottom in FIG. 17, are coupled to one another by means of additional word lines 1773, 1774 and 1775.
  • the source and drain connections of the double-gate memory transistors of a column are coupled to one another in a manner customary for an AND arrangement with virtual grounding.
  • Bit lines 1776, 1777, 1778 and 1779 are formed in that the source terminal of a double-gate memory transistor in one column is coupled to the source terminal of a double-gate memory transistor adjacent in the column.
  • the drain connections of the double-gate memory arrays arranged in the adjacent column are Transistors coupled to the same bit line.
  • the word lines are fed to a main side of the arrangement in a first direction, while the word lines are fed to the opposite main side in the direction opposite to the first direction.
  • the additional subject matter of the application creates a double-gate memory transistor, which can be produced using known and simple process steps.
  • the double-gate memory transistor By means of the double-gate memory transistor, the memory density can be doubled compared to a conventional memory transistor.
  • the double gate memory transistor with ONO layers four bits per individual double gate memory transistor can thus be stored. It should be noted, however, that no formation of ONO layers is necessary, but that any formation of a so-called charge trapping layer can be used.
  • first passivation layer made of silicon nitride
  • first passivation layer made of silicon nitride
  • first side wall layers made of silicon nitride

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Abstract

La présente invention concerne un procédé pour produire un transistor à double grille. Ce procédé consiste à former une première région de grille sur un substrat silicium-sur-isolant d'une première plaquette, à former une couche de surface plane sur le substrat silicium-sur-isolant et la première région de grille, à métalliser une seconde plaquette sur la surface plane de la première plaquette et à former une seconde région de grille opposée à la première région de grille dans le substrat silicium-sur-isolant.
PCT/DE2003/001726 2002-05-28 2003-05-27 Procede pour produire un transistor a double grille WO2003103035A1 (fr)

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DE10223709A DE10223709B4 (de) 2002-05-28 2002-05-28 Verfahren zum Herstellen eines Doppel-Gate-Transistors
DE10223709.3 2002-05-28

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WO2006005321A3 (fr) * 2004-07-08 2006-02-23 Infineon Technologies Ag Procede de production d'un circuit integre et substrat comprenant une couche enterree
FR2899381A1 (fr) * 2006-03-28 2007-10-05 Commissariat Energie Atomique Procede de realisation d'un transistor a effet de champ a grilles auto-alignees

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DE102004033147B4 (de) * 2004-07-08 2007-05-03 Infineon Technologies Ag Planarer Doppel-Gate-Transistor und Verfahren zum Herstellen eines planaren Doppel-Gate-Transistors
DE102004033148B4 (de) 2004-07-08 2007-02-01 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung und Schicht-Anordnung zur Verwendung als Doppelgate-Feldeffekttransistor

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US5899710A (en) * 1995-01-20 1999-05-04 Sony Corporation Method for forming field effect transistor having multiple gate electrodes surrounding the channel region
US6365465B1 (en) * 1999-03-19 2002-04-02 International Business Machines Corporation Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
JP2001102590A (ja) * 1999-09-29 2001-04-13 Agency Of Ind Science & Technol 半導体製造方法
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WO2006005321A3 (fr) * 2004-07-08 2006-02-23 Infineon Technologies Ag Procede de production d'un circuit integre et substrat comprenant une couche enterree
FR2899381A1 (fr) * 2006-03-28 2007-10-05 Commissariat Energie Atomique Procede de realisation d'un transistor a effet de champ a grilles auto-alignees
WO2007110507A3 (fr) * 2006-03-28 2007-11-29 Commissariat Energie Atomique Procede de realisation d'un transistor a effet de champ a grilles auto-alignees
US7709332B2 (en) 2006-03-28 2010-05-04 Commissariat A L'energie Atomique Process for fabricating a field-effect transistor with self-aligned gates

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