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WO2006000987A1 - Dispositif de conversion de signaux analogiques en signaux numeriques avec une precision non homogene - Google Patents

Dispositif de conversion de signaux analogiques en signaux numeriques avec une precision non homogene Download PDF

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Publication number
WO2006000987A1
WO2006000987A1 PCT/IB2005/052031 IB2005052031W WO2006000987A1 WO 2006000987 A1 WO2006000987 A1 WO 2006000987A1 IB 2005052031 W IB2005052031 W IB 2005052031W WO 2006000987 A1 WO2006000987 A1 WO 2006000987A1
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WO
WIPO (PCT)
Prior art keywords
section
output terminal
output
common
sections
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PCT/IB2005/052031
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English (en)
Inventor
Peter C. S. Scholtens
Original Assignee
Koninklijke Philips Electronics N.V.
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Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2006000987A1 publication Critical patent/WO2006000987A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H03M1/0643—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the spatial domain
    • H03M1/0646—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the spatial domain by analogue redistribution among corresponding nodes of adjacent cells, e.g. using an impedance network connected among all comparator outputs in a flash converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
    • H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
    • H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string

Definitions

  • the present invention relates in general to an analog-to-digital converter, hereinafter briefly indicated as ADC.
  • FIG. 1A is a block diagram schematically illustrating the principle of operation of a flash ADC 1, capable of converting an analogue signal to one of a predetermined plurality of discrete signal levels, indicated as quantisation levels.
  • the flash ADC 1 comprises a reference stage 2 for generating a plurality of N discrete reference levels, typically and illustratively implemented as a plurality of resistors 3 connected in series between two lines 7 and 8 carrying basic reference voltages VH and VL, respectively, VL having a lower level than VH.
  • VH is positive and VL is negative.
  • the flash ADC 1 further comprises an amplification stage 40, comprising an array of low gain differential amplifiers 4. Each node 5 is connected to one input terminal of an associated differential amplifier 4.
  • the flash ADC 1 further comprises an input terminal 6, for receiving an analogue input signal Si, which input terminal 6 is connected to another input terminal of all differential amplifiers 4.
  • Each differential amplifier 4 has an output terminal 14 coupled to a respective input terminal of a signal processor 9. The output voltages at output terminals 14 depend on the value of the input signal Si received at input terminal 6.
  • Each amplifier 4 effectively compares the input signal Si with the associated node reference potential, and provides to the processor 9 an output signal, indicating whether the input signal Si is above or below the corresponding node reference potential, the processor 9 generating a digital output signal Sd on the basis of its input signals.
  • the differential amplifiers will now be treated as ideal comparators. It is noted that it is possible to consider the N output signals of the N comparators 4 as constituting a digital output signal of N digits. Although having N digits, there are only N possible values for the output signal; which one of these N possibilities is actually taken can be coded with less than N digits, as will be clear to a person skilled in the art.
  • the accuracy of operation of the individual comparators 4 should be doubled, which involves increasing the surface area of each comparator by approximately a factor 4. Further, if the bandwidth of the device is to be maintained, the current consumption increases by a factor 8. Thus, in a practical design, there is a trade-off between desired accuracy and IC surface area / power consumption.
  • high accuracy is not particularly necessary over the entire range of possible input signal values, but only over a relatively small portion of such range.
  • a typical example of such situation may arise when it is important to accurately know the timing of the zero-crossings of the input signal.
  • One example of such situation is the processing of the read output signal of an optical detector of an optical disc drive.
  • FIG. 1C schematically illustrates an example where the range 10 of possible input signal values is divided in three subranges 11, 12, 13.
  • the node reference potentials are equidistantly spaced very close together at equal mutual distances dl.
  • the node reference potentials are equidistantly spaced at equal mutual distances d2, d2 being larger than dl.
  • a third subrange 13 at the ends of the input range 10, on opposite sides of the second subrange 12 the node reference potentials are equidistantly spaced at equal mutual distances d3, d3 being larger than d2.
  • Another problem of ADCs relates to possible offset of amplifiers of the comparators 4, which adds to the quantisation error.
  • offset averaging A technique for mitigating these problems has already been proposed, and is known as "offset averaging".
  • offset averaging For an elaborate discussion on offset averaging, reference is made to the article "A Technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters" by K. Kattmann et al in ISSCC Digest of Technical Papers, February 1991, p. 170-171.
  • Figure 2 is a block diagram schematically illustrating this technique.
  • Figure 2 shows three differential amplifiers 4(1), 4(2) and 4(3), with relatively low gain, each having an output terminal 14(1), 14(2) and 14(3), respectively.
  • Each differential amplifier has an output resistance RO(I), RO(2) and RO(3), respectively.
  • a first averaging resistor RA(1,2) is connected between output terminals 14(1) and 14(2).
  • a second averaging resistor RA(2,3) is connected between output terminals 14(2) and 14(3).
  • Each differential amplifier may suffer from some offset, resulting in an error output voltage component. Due to averaging currents resulting in the averaging resistors RA, the error output voltage components are averaged over neighbouring output terminals.
  • an objective of the present invention is to suitably match a first array of differential amplifiers with a second array of differential amplifiers, such that disadvantageous effects caused by differences between said two arrays are compensated.
  • the present invention aims to provide a flash ADC comprising a reference stage for generating a plurality of discrete reference voltages, the reference stage having at least a first section where the difference between successive reference voltages has a first value and at least a second section where the difference between successive reference voltages has a second value, the flash ADC further comprising a linear amplification stage having the following features: one signal input; a plurality of reference inputs for receiving the reference voltages; an array of differential amplifiers, each having one input coupled to the signal input and having another input coupled to one of the reference inputs; a plurality of outputs; - the differential amplifiers having mutually the same gain, at least substantially; wherein the linearity requirement of the amplification stage means that the difference between the output voltages at two successive outputs is independent from the value of the input
  • a match is obtained by suitably selecting the output resistances of the differential amplifiers.
  • a match is obtained by suitably selecting the resistances of averaging resistors.
  • Figure IA is a block diagram schematically illustrating the principle of operation of a flash ADC
  • Figure IB is a graph illustrating quantisation errors in the case of equidistant reference levels
  • Figure 1C is a graph illustrating reduced quantisation errors around zero in the case of non-equidistant reference levels
  • Figure 2 is a block diagram schematically illustrating the technique of averaging
  • Figure 3 is a block diagram schematically showing an ADC
  • Figure 4A is a block diagram schematically illustrating an equivalent replacement circuit for a section comprising two differential amplifiers
  • Figure 4B is a block diagram schematically illustrating the problem to be solved
  • Figures 5 - 8 are a block diagrams schematically illustrating part of a circuit of an embodiment of an ADC according to the present invention.
  • FIG. 3 schematically shows a block diagram of an ADC 100 having 11 reference levels which are not equidistantly spaced.
  • the ADC 100 comprises a reference stage 2 comprising an array of seven resistors 31-37 connected in series between high voltage source VH and low voltage source VL.
  • the nodes between successive resistors provide reference voltages, the voltage levels of these reference voltages depending on the resistance values of the resistors 31-37, as should be clear to a person skilled in the art. If the seven resistors 31-37 have mutually equal resistance value, the reference voltage levels are substantially equidistant.
  • the ADC 100 comprises an amplification stage 40 comprising an array of six low gain differential amplifiers 41-46, each having a non- inverting input connected to ADC input 6 for receiving the input signal Si, and each having an inverting input connected to a respective one of said nodes between two adjacent resistors 31-37.
  • Output resistors of the differential amplifiers 41-46 are indicated as RO 41 to RO 46 , respectively.
  • the output of each differential amplifier 41-46 is connected to an input of a buffer amplifier 101-106, respectively. It is noted that the output of each differential amplifier 41-46 may also be coupled to a further processing stage.
  • the outputs of two adjacent differential amplifiers are connected by averaging resistor arrangements, as will be explained in more detail.
  • Each averaging resistor arrangement may comprise only one single resistor (e.g. 51), or a plurality of resistors connected in series (e.g. 61, 62), the node between such resistors providing interpolation output terminals.
  • an ADC section 50, 60, 70, 80, 90 is defined by a pair of two adjacent differential amplifiers, together with the one reference resistor 32-36 associated with said pair of two adjacent differential amplifiers.
  • such pair of two adjacent differential amplifiers constitutes a voltage source for such ADC section, as will be explained later in more detail.
  • the output terminals of the first two differential amplifiers 41 and 42 are coupled together via a resistor 51, which has an offset averaging effect.
  • resistor 91 coupling together the output terminals of the last two differential amplifiers 45 and 46.
  • the output terminals of the two differential amplifiers 42 and 43 are coupled together via two resistors 61, 62 connected in series.
  • the node between these two resistors 61, 62 is connected to the input of a seventh comparator 111.
  • the series combination of the two resistors 61, 62 has an offset averaging effect.
  • the node between these two resistors 61, 62 effectively constitutes an interpolation reference level between the two reference levels associated with the two differential amplifiers 42 and 43, respectively.
  • a fourth ADC section 80 which node is connected to the input of an eighth comparator 131, effectively constituting an interpolation reference level between the two reference levels associated with the two differential amplifiers 44 and 45, respectively.
  • the output terminals of the two differential amplifiers 43 and 44 are coupled together via four resistors 71-74 connected in series.
  • the three nodes between these four resistors 71-74 are connected to the inputs of respective ninth to eleventh comparators 121-123.
  • the series combination of the four resistors 71-74 has an offset averaging effect.
  • the three nodes between these four resistors 71-74 effectively constitute three interpolation reference levels between the two reference levels associated with the two differential amplifiers 43 and 44, respectively.
  • the averaging resistor arrangements in general will simply be indicated as RAV-
  • the amplifiers in each section, together with the associated reference resistors at their inputs, will be considered as constituting a voltage source, as explained in figure 4A.
  • a reference resistor is shown (compare one of the resistors 31-37 in figure 3) having a voltage drop ⁇ V ref over its terminals, which are connected to inputs of two amplifiers (compare two adjacent amplifiers 41-46 in figure 3), each amplifier having a relatively low gain A in the order of, for example, approximately 1.5 - 10.
  • the output voltage differences over the output terminals of the voltage sources in the ADC sections 50-90 of the ADC 100 depend only on the resistance values of the resistances 32-36. According to the invention, the resistance values of adjacent resistances 32-36 do not need to be identical. From the above, it should be clear that there are differences between adjacent ADC sections. It is noted that the ADC 100 in the embodiment of figure 3 comprises at least one set of two sections which are mutually at least substantially identical: for instance, compare sections 60 and 80. It is further noted that in some embodiments the ADC may have two substantially identical sections adjacent each other.
  • an important aspect of the ADC according to the present invention is that it contains at least one pair of adjacent ADC sections which are mutually different. In the embodiment shown in figure 3, this applies to each pair of the four pairs of sections 50, 60; 60, 70; 70, 80; 80, 90.
  • One possible difference of the adjacent sections may concern the number of interpolation reference levels. For instance, second section 60 has one interpolation reference level, whereas third section 70 has three interpolation reference levels. Another possible difference may relate to the design of the amplifiers 41-46. As mentioned, the third section 70 has more interpolation reference levels in order to achieve a higher quantisation accuracy.
  • the amplifiers 43 and 44 associated with the third section 70 preferably have higher accuracy than amplifiers 42 and 45, which in turn have higher accuracy than amplifiers 41 and 46.
  • amplifiers typically have larger size and reduced output resistance.
  • Another possible difference may relate to the voltage references at the inputs of the amplifiers 41-46. Two adjacent resistors 31-37 may have mutually different resistance values, such that the voltage difference between the two reference inputs of a section may differ from one section to another.
  • Another possible difference relates to the degree of averaging, which is determined by the ratio between averaging resistors and output resistances of the corresponding amplifiers. Other differences are possible, too.
  • Figure 4B is a block diagram illustrating the problem to be solved.
  • Figure 4B shows part of an AD converter 400, comprising a first quantisation array 410 and a second quantisation array 420.
  • the first quantisation array 410 comprises three ADC differential amplifiers shown as two voltage sources 401 and 402, respectively, (compare figure 4A) providing output voltages Ul and U2, respectively.
  • a first output terminal of the first voltage source 401 has a first output resistance ROl.
  • a common output terminal of the first voltage source 401 and second voltage source 402 has a second output resistance RO2.
  • a first averaging resistor RAVI connects the said output resistances ROl and RO2.
  • the second quantisation array 420 comprises three ADC differential amplifiers shown as two voltage sources 403 and 404, respectively, providing output voltages U3 and U4, respectively, and having output resistances RO3 and RO4, respectively.
  • a first output terminal of the fourth voltage source 404 has a fourth output resistance RO4.
  • a common output terminal of the fourth voltage source 404 and third voltage source 403 has a third output resistance RO3.
  • a fourth averaging resistor RAV4 connects the said output resistances RO3 and RO4.
  • a common output resistance of the second voltage source 402 and the third voltage source 403 is indicated as Rx.
  • a second averaging resistor parallel to the second voltage source 402 is indicated as Ry, while a third averaging resistor parallel to the third voltage source 403 is indicated as Rz.
  • the output voltage of a first ADC section, corresponding to the first voltage source 401, i.e. the voltage over the first averaging resistor RAVI ? is indicated as Wl; likewise, the output voltage of a second ADC section, corresponding to the second voltage source 402, i.e. the voltage over the second averaging resistor Ry, is indicated as W2; likewise, the output voltage of a third ADC section, corresponding to the third voltage source 403, i.e.
  • the voltage over the third averaging resistor Rz is indicated as W3; likewise, the output voltage of a fourth ADC section, corresponding to the fourth voltage source 404, i.e. the voltage over the fourth averaging resistor RAV4 > is indicated as W4.
  • the sections of the ADC 400 are mutually matched, i.e. the output voltages Wi depend on the input reference voltages Vref,i in a linear manner, i.e.
  • Example 1 Figure 5 shows two sections A and B of a first embodiment of an ADC 500 according to the invention, having respective voltage sources 501 and 502 with output voltages A- ⁇ Vi and A-AV 2 and having respective averaging resistors RAVI and RAV2- It is assumed that the respective gains are equal, so that differences in the output voltages are attributed to differences in the corresponding reference resistors, as will be clear to a person skilled in the art. Further, it is noted that the averaging resistors may have interpolation taps, as described with reference to figure 3.
  • An output side of the output resistance 521 of the first voltage source 501 is connected to a first output 541.
  • an output side of the common output resistance 522 is connected to a second output 542.
  • an output side of the output resistance 524 of the second voltage source 502 is connected to a third output 544.
  • the first output 541 is connected to the second output 542 by a first averaging resistor 531 having resistance value RAVI-
  • the second output 542 is connected to the third output 544 by a second averaging resistor 532 having resistance value RAV2-
  • the first section A has a neighbouring section A 1 identical to the first section A (i.e.
  • Example 2 Figure 6 shows two sections A and B of a second embodiment of an ADC 600 according to the invention, which is substantially identical to ADC 500 of figure 5, with the exception that the first averaging resistor 531 (Ry) is sub-divided into a first partial averaging resistor 63 Ia having resistance value R A vi a and a second partial averaging resistor 613b having resistance value RAVU D -
  • the common output terminal 622 of Rx is connected to the node 630 between these two resistors 631a and 631b, while the output tap 542 is at the node between said series arrangement and Rz.
  • A- ⁇ V1 / R A vi (1)
  • A- ⁇ V2 / R AV2 (2)
  • R A vi a can be selected equal to zero.
  • Example 3 Figure 7 shows two sections A and B of a third embodiment of an ADC 700 according to the invention, which is substantially identical to ADC 500 of figure 5, with the exception that the output voltages of the voltage sources 701 and 702 of sections A and B are adapted, so that the output voltage of the voltage source 701 of section A is increased somewhat to yield A- ⁇ Vr(l+ki) whereas the output voltage of the voltage source 702 of section B is decreased somewhat to yield A- ⁇ V 2 -(l-k 2 ).
  • These shifts of output voltages can for instance be obtained by changing the gains of the corresponding amplifiers; accordingly, the voltage source 701 of section A may have a gain A-(l+kl) and the voltage source 702 of section B may have a gain A-(l-k2).
  • the shifts of output voltages can for instance be obtained by changing the corresponding reference resistors (32-35 in figure 3), such that the voltage source 701 of section A receives an input reference voltage while the voltage source 702 of section B receives an input reference voltage AV 2 -(I-Ic 2 ).
  • Example 4 Figure 8 is a block diagram of an ADC 800 substantially identical to ADC 500 of figure 5, with the exception that in this case the second averaging resistor 532 between the second output 542 and the third output 544 is omitted. Instead, the output side of the third output resistance 524 of the second voltage source 502 is connected to the second output 542, and the output side of the common output resistance 522 is connected to the third output 544.
  • a third section adjacent the second section B is indicated at C.
  • This third section C has a fourth voltage source 504, a fourth output resistance 525, a fourth output terminal 545, and a fourth averaging resistor 534 connected between the fourth output terminal 545 and the third output terminal 544.
  • the common output resistance 522 has the second output resistance value R2
  • the third output resistance 524 has the first output resistance value Rl.
  • the first averaging resistance value RAVI is selected to be equal to the first output resistance value Rl
  • the second averaging resistance value RAV2 is selected to be equal to the second output resistance value R2.
  • a more general solution can be obtained by taking the output voltage of second voltage source 502 as an independent parameter, to be written as A-AV 3 .
  • the resistance value of the third output resistor 524 will be indicated as Ry, while the resistance value of the second or common output resistor 522 will be indicated as Rx.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Amplifiers (AREA)

Abstract

Un CAD (100) comprend: une pluralité d'amplificateurs différentiels (41,46) possédant chacun une première entrée connectée à une entrée de signal (6) et une seconde entrée connectée à une tension de référence parmi plusieurs; une pluralité de résistors de moyennage connectés chacun entre deux sorties de deux amplificateurs différentiels respectifs. Ce CAD possède une première partie (A) comprenant un premier amplificateur différentiel et un deuxième amplificateur différentiel adjacent parmi plusieurs, et une seconde partie (B) comprenant ledit deuxième amplificateur différentiel et un troisième amplificateur différentiel parmi plusieurs, chaque amplificateur différentiel possédant une résistance de sortie. Au moins une des résistances de sortie diffère d'au moins une autre desdites résistances de sortie. Les valeurs de résistance des résistors de moyennage et les valeurs de résistance desdites résistances de sortie sont sélectionnées les unes par rapport aux autres, si bien que lesdites deux parties sont adaptées l'une à l'autre.
PCT/IB2005/052031 2004-06-24 2005-06-21 Dispositif de conversion de signaux analogiques en signaux numeriques avec une precision non homogene WO2006000987A1 (fr)

Applications Claiming Priority (4)

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EP04102932 2004-06-24
EP04102932.3 2004-06-24
EP04103470.3 2004-07-21
EP04103470 2004-07-21

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EP1811671A1 (fr) * 2006-01-13 2007-07-25 Sony Corporation Convertisseur analogique-numerique
WO2007138512A3 (fr) * 2006-05-30 2008-02-14 Nxp Bv Convertisseur analogique/numérique flash
WO2009115990A2 (fr) 2008-03-19 2009-09-24 Nxp B.V. Convertisseur flash analogique/numérique

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US10116319B2 (en) * 2017-03-03 2018-10-30 Texas Instruments Incorporated Resistive interpolation for an amplifier array
CN114079468B (zh) * 2020-08-20 2024-09-24 瑞昱半导体股份有限公司 快闪式模拟数字转换器

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1811671A1 (fr) * 2006-01-13 2007-07-25 Sony Corporation Convertisseur analogique-numerique
US7405691B2 (en) 2006-01-13 2008-07-29 Sony Corporation Analog-to-digital conversion circuit
WO2007138512A3 (fr) * 2006-05-30 2008-02-14 Nxp Bv Convertisseur analogique/numérique flash
WO2009115990A2 (fr) 2008-03-19 2009-09-24 Nxp B.V. Convertisseur flash analogique/numérique
WO2009115990A3 (fr) * 2008-03-19 2009-11-12 Nxp B.V. Convertisseur flash analogique/numérique
US8284091B2 (en) 2008-03-19 2012-10-09 Integrated Device Technology, Inc. Flash analog-to-digital converter

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