WO2006006842A2

WO2006006842A2 - Digital processor and method of processing digital data

Info

Publication number: WO2006006842A2
Application number: PCT/NL2004/000505
Authority: WO
Inventors: Halil Kilic
Original assignee: Halil Kilic
Priority date: 2004-07-12
Filing date: 2004-07-12
Publication date: 2006-01-19
Also published as: CN101091157B; WO2006006842B1; CN101091157A; EP1831782A2; WO2006006842A3

Abstract

The present invention describes a new computer architecture. A digital processor comprises processing units which comprise decoders for decoding a first part of the N- bit data word into digital code with only one bit high. These bits are processed in arithmetic modules, which receive outputs from two processing units, and an activation signal produced by an instruction circuit. The instruction circuit receives knowledge on the data to be processed by reading the second part of the N-bit data words. This second part may be divided into several so-called DNA groups. The DNA group contain information on the type of symbols/values of the data to be processed. Using this knowledge on the data, very fast and simple parallel processing can be executed.

Description

Digital processor and method of processing digital data

Field of the invention

The present invention relates to digital processing. The invention particularly relates to a digital processor arranged to process data words coded in a specific genetics based way.

Background of the invention

There are three main developments in the field of digital computing at this moment. 1. The improvement of VLSI technology, e.g. decreasing the t-cycle and increasing the available number of transistors per chip; 2. Architectural developments like pipelining instructions, parallel instruction fetching, influencing t-cycle, number of instructions (Ninstr) and CPI etc.; 3. Compiler and or assembler developments especially the exploitation of instruction level parallelism, which influences Ninstr and CPI as well.

At this moment we are reaching the maximum abilities of VLSI technology, below 10 nm electrons happen to tunnel (a quantum dynamics effect) through the isolation between on-chip wires. Increased power dissipation forces the use of lower supply voltage (3.3 V) and VLSI processes with lower voltages become available. However, the design complexity and binary incompatibility are increasing exponentially. This is one of the reasons why extensibility of the developments are reaching its maximum. Besides those factors, the question of compatibility at different levels and extensibility of the existing soft- and hardware makes the implementation of new product types exponentially complex and difficult. Furthermore, the amount of logical operations needed to execute a simple decimal operation is relatively high.

The number of translations from decimal data to binary data, and back requires a certain amount of effective computing power-output (ECO). Compared to the amount of effective computing power-input (ECI), the ECO is very low, i.e. the Return On Computing power (ROC), wherein ROC = ECO/ECI, is very small. The ROC in the calculation of the example above is less than 1/256. When compiling a 4-th or 5-th level computer language to a machine language (for example hexadecimal or BCD or ASCII code), the number of bits will increase even further, leading to even lower (i.e. worse) values for the ROC.

Summary of the invention

It is an object of the invention to introduce another type of computer architecture which provide higher computation speed. The object is achieved by providing a digital processor comprising:

- a first processing unit arranged to receive a first N-bit data word, and comprising:

- a first decoder arranged to receive a first part of said first N-bit data word and to decode said first part of said first N-bit data word into a first D-bit data word, wherein N, D are positive integers, and

- a first read out circuit arranged to read out specific bits of a second part of said first N-bit data word so as to produce a first knowledge signal;

- a second processing unit arranged to receive a second N-bit data word, and comprising:

- a second decoder arranged to receive a first part of said second N-bit data word and to decode said first part of said second N-bit data word into a second D-bit data word, and

- a second read out circuit arranged to read out specific bits of a second part of said second N-bit data word so as to produce a second knowledge signal;

- a plurality of arithmetic modules, each arithmetic module being arranged to receive said first and said second D-bit data word, and arranged to perform a predefined arithmetic operation on said first and said second D-bit data word;

- at least one instruction circuit arranged to receive an input instruction signal, and arranged to convert said input instruction signal into an activation signal using said first and said second knowledge signal, and arranged to activate one arithmetic module out of said plurality of arithmetic modules, so as to produce an output data word. The processor according to the invention has a new architecture enabling a fast and parallel processing of data, with minimal number of logical gate operation per calculation.

This new architecture requires another way of thinking about the design of computer architecture. With the invention, it is possible to make superscalar and super pipelined processors (VLIW) which operate with a new type of computer architecture. The invention is based on the insight that the density of a dye (which can be MOS/CMOS) is not the most important problem of the main developments mentioned in the preamble. The limitation of the computing power (i.e. the amount of logical operations per second) is the key issue to be solved. As was shown in the example above, the ROC values in current processors is very low. In a processor according to the invention, the ROC value is improved dramatically, as will become apparent form the examples shown.

In another aspect of the invention, a computer is provided comprising a digital processor as described above. hi yet another aspect, a method of processing digital data according to claim 8 is provided.

Brief description of the drawings

Below, the invention will be explained with reference to some drawings, which are intended for illustration purposes only and not to limit the scope of protection as defined in the accompanying claims, wherein:

Fig. 1 shows a part of a digital processor according to an embodiment of the invention, Fig. 2 is a simple example of a calculation, executed by a processor according to an embodiment,

Fig. 3 is another example of a calculation, Fig. 4 shows an example of the multiplication of 254 x 2, Fig. 5 schematically depicts the relation between the I/O Bus and the digital processor, Fig. 6 shows an example of a axiom for multiplying decimal values, Fig. 7 is a table listing of a possible coding used in an embodiment of the invention, an Fig. 8 is an example of a hardware implementation of a decoder comprised in an embodiment of the invention.

Description of preferred embodiments

In figure 1, a part of a digital processor according to an embodiment of the invention is shown. The digital processor comprises at least a first processing unit 1 and a second processing unit 2. Processing units 1, 2 each comprise a decoder 3, 4 arranged to decode a first part of an input data word comprising N bits, see arrows 6, 8, into a D-bit data word depicted as 5, 7 respectively. Processing units 1, 2 further comprise a read out circuit 9, 11 (also referred to as DNA decoder) for receiving a second part of an input data word. The read out circuits 9, 11 convert the second part of the N-bit data words into so-called knowledge signals 13, 15 which are led to a instruction circuit 17. The instruction circuit is arranged to receive an input instruction signal 19 and convert the input instruction signal 19 into an activation signal depending on said knowledge signals 13, 15. The digital processor further comprises a plurality of arithmetic modules 25, 27, 29, 31 arranged to perform arithmetic operations on the D-bit data words 5, 7, received from the decoders 3, 4 of the first and second processing unit. Each of the arithmetic modules 25, 27, 29, 31 may embody a different arithmetic operation, such as multiplying, adding, subtracting, comparing, etc. The instruction circuit 17 is arranged to produce an activation signal 33, which is sent to the different arithmetic modules 25, 27, 29, 31. The arithmetic modules 25, 27, 29, 31 will perform their specific arithmetic operation, only if they receive an activation signal from the instruction circuit 17. The outcomes 35 of the specific arithmetic operations are represented in a format using the same coding as the one which is used to code the input data words, hi this way, the output of the arithmetic modules can be input for other processing units, for further processing.

In an embodiment of the invention the decoders 3, 4 are arranged to convert binary code into D-bit data word, which is coded in a format wherein only one bit is active at a time. Decoders 3, 4 may for example comprise 10 output gates, each output gate representing one decimal value. Each of the output gates of the decoders can be routed to a specific arithmetic module which then only needs to perform a calculation on two bits. This results in very simple architecture of the arithmetic modules 25, 27, 29, 31, which in turn is favourable for the speed of the digital processor.

In figure 2 a simple example of a calculation is shown. In this example a very simple multiplication of 1 x 3 (decimal) is described. The value 1 is stored in a register 40, which may be part of the first processing unit 1. It should be noted that this register may well be part of an I/O bus, providing the processing units 1, 2 with data. The decimal value 3 is stored in register 41. Both decimal values are binary coded. The first part of a first N-bit data word 40 is input for a decoder 3, which converts the digital value into a first D-bit data word wherein only one output gate is high, in this case output gate labelled "1" is high. The other output gates are low and are not of interest for this example. The first part of a second N-bit data word 41 is input for decoder 4, which convert it to a second D-bit data word wherein only an output gate "3" is high. Output of the decoders 3, 4 is sent to a multiplier 43, which comprises an AND gate and two OR gates 46, 47. Figure 2 also shows an example of an instruction circuit 17, which receives an instruction signal 19, having a value <0>. In this case the instruction circuit 17 comprises one NAND 51, which receives the instruction signal 19 and data from a specific bit in the knowledge data part of the two N-bit data words. Both bits are indicative for whether the cell cores contain numerical values or not. Here, they both contain a <0>, which in this case means that both values are numeric. The instruction circuit 17 will sent an activation signal 53 to the multiplier 43, such as to activate the multiplier. The result of this multiplication is that a digital code 00011 is produces, see output buffer 54. It is noted that the output buffer 54 may be an input buffer of a further processing unit, not shown. In the example of figure 2, the multiplier 43 may also comprise an inverter 57, which is connected to an input gate of the output buffer 54 to fill the bit concerning information on the output value being a numeric value, in this case a <0> will stored in the appropriate position of the second part 55 of the output buffer 54. It should be noted that this filling of knowledge data into the output buffer 54 may well be performed by the instruction circuit 17.

Another example will be explained with reference to figure 3. In this example, the N- bit data words which are processed are coded in a special format, referred to as ABGED code. Details of this ABGED code will be explained in more detail later on in the description, with reference to figure 5 and 7.

Figure 3 shows a calculation of 10² x 10³ (i.e. 100 x 1000 decimal). The value 10² is stored in an ABGED code format in a register 60, which means that the cell core contains <00010> and that a specific bit in the knowledge data (i.e. the second part of the data word) is <1>, representing the fact that the cell core contains an exponential value. The value 10³ is stored in a register 61, see figure 3. Each of the decoders 3, 4 will decode the digital cell core data into a D-bit data word, which are input for both a multiplier 63 and an adder 65. The instruction circuit 17 receives knowledge information from the second parts of the input N-bit data words, via a read out circuit, which is not shown. The instruction circuit 17 receives a multiplication instruction signal 19 and converts it into an activation signal 75. In this case, the activation signal 75 is sent to an adder 65, but not to the multiplexer 63. This is a result of the knowledge present in the second part of the input data words. This knowledge is represented by specific bits, which in turn activate adequate logical gates in the instruction circuit. This will lead to activation signals, which indirectly embody the arithmetic knowledge that multiplying two exponential values with the same base, can be performed by adding the exponent and keeping the base unchanged. The adder 65 will fill an output register 77 wherein a cell core will be filled with the value <00001> and the second part of the data word, representing the knowledge of the output data word (e.g. the outcome has base 10 (decimal)), will be filled in such a way that the exponent bit El is <1>.

According to the invention, a decimal value with more than one decimal is represented by a plurality of cells, referred to as 'cell chain'. For example, the decimal value 254 is represented by a cell chain of three cells. Each of the three decimal values is coded into a binary code and stored in a first part of a data word. Preferably, the N-bit data word contains at least 26 bits. A second part of a cell contains bits representing additional knowledge on the value present in the cell core (i.e., the first part of the data word). According to an embodiment, each cell is represented (i.e. processed) by one active processing unit, so a cell chain is represented by a number of processing units. These processing unit may be implemented in one single IC (integrated circuit) or in a plurality of ICs. According to an embodiment of the invention the digital processor comprises a plurality of processing units, and a plurality of arithmetic modules and at least one instruction circuit, wherein each of said plurality of processing units is arranged to decode a first part of a N-bit data word into a D-bit data word, and arranged to output said D-bit data word to at least one of said plurality of arithmetic modules, said plurality of arithmetic modules being arranged to be activated by activation signals produced by said at least one instruction circuit depending on knowledge signals produced by read out circuits comprised in said plurality of processing units.

This embodiment is explained using a simple example with reference to figure 4. hi figure 4 an example is shown of a multiplication of 254 x 2. This value 254 is represented by three cells and the decimal value 2 is represented by one cell. Each of the cells is processed by one processing unit. In figure 4 only information stored in the cell cores is discussed, hi figure 4, a cell core 80 <00010> is input for a decoder 85. A cell core 81 with value <00101> is input for a decoder 86 and a cell core 82 with value <00100> is input for a decoder 87. Furthermore, a cell core 90 with value <00010> is input for a decoder 91. As can be seen from figure 4, decoders 85, 86, 87, 91 are connected to arithmetic modules. Decoder 85 and decoder 91 are connected to arithmetic module 93, decoder 86 and decoder 91 are connected to arithmetic module 95. Decoder 87 and decoder 91 are connected to arithmetic module 97. As was explained in figure 2, the arithmetic modules will produce an outcome, which will be sent to inputs of following processing units 100, 104, 101, 102. Figure 4 only shows part of these following processing units. Arithmetic module 93 outputs its data to processing unitlOO, arithmetic module 95 outputs its value to processing unitlOl and arithmetic module 97 outputs its value to processing unitlO2. The arithmetic module 95 is processing the multiplication of 5 x 2, which results in the decimal value 10. Since this decimal value cannot be represented by one processing unit (note: one processing unit can only represent one symbol, i.e. one decimal number), a further arithmetic module 94 and processing unit 104 are activated. This activation signal is realized by some kind of 'overflow' signal coming from arithmetic module 95, possibly coming via a separate instruction circuit, not shown. Due to the specific structure of arithmetic module 94 and processing unit 104, an output value <0001> will be realized at the outputs of processing unit 104. Processing unit 104 is connected to another processing unit 107 via an adder. Note that in this case the adder comprises two wires connected to the adequate input gates of the processing unit 107. This adder also receives input from processing unit 100. Now, the adder will be activated as a result of the activation of processing unit 104 and an activation signal from an instruction circuit having knowledge about the fact that processing unit 101 did not represent (i.e. contains) the most left number of a cell-chain. The result of the adding of adder (i.e. the decimal value 5) is represented by processing unit 107. The final results of this multiplication are three active processing units 107, 101 and 102, containing ABGED code representing the decimal value 508.

According to a preferred embodiment of the invention, the second part comprises three groups, i.e., DNA-A group, DNA-B group and DNA-C group. In table 1, a diagram is shown wherein the structure of a cell is explained and in particular the relation between the different DNA groups and the cell core.

Table 1:

As can been seen from table 1, in the preferred embodiment the cell core comprising five bits representing a alphanumeric symbol. The DNA-A group contains values representing the length of the bit strings of the DNA-C group and the DNA-B group. Besides this length information, the DNA-A group may also comprise a set of bits indicating the beginning or the end of a specific amount of data to be processed, or of a specific operation. A possible coding of this third helix in the DNA-A group is:

first bit is equal to 0, then the cell core contains data, if equal to 1, then the cell core is operation code:

001 begin of data

010 end of data

101 begin of operation

110 end of operation.

The DNA-B group contains information on what kind of data is contained in the cell core.

In a preferred embodiment the DNA-C group has variable length. Since a cell can have a variable length, so more than 26 bits, more than one unit is needed to store a cell. There are several registers units (I call this DNA-map-registers) which contains information about the length of DNA-A, DNA-B and DNA-C and its positions of each cell. The mapping of data can be serial and/or parallel executed.

The processing circuits 25, 27, 29, 31 shown in figure 1 each perform certain arithmetic operations. It should be noted that the number of processing circuits is not limited to four, but can be much more.

Figure 5 shows an example of a configuration of an I/O Bus 600 which may be used in a processor according to the invention. The function of an I/O Bus manager, see 601, is to analyse the structure of the incoming data by reading the DNA-A group and saving this information. For example, a specific cell begins from bit no. 1 end it ends at bit no. 26 from right to left. The size of the I/O bus 600 is relatively flexible. The external I/O bus 602 has one size (this depends of the number of pins used. The flexibility of the I/O bus 600 is realized by the I/O Bus manager 601, which reads and calculates the next begin position of the next cell within a cell chain. This information is stored in a position register, not shown. When all the positions are stored in the position register, a map of the cells and cell chains can be created by the I/O bus 600.

Figure 6 shows an example of a axiom for multiplying decimal values, which may be implemented by a processing circuit in the digital processor. The axiom is implemented in a processing circuit by connecting certain input gates via logical gates to output gates of the processing circuits. This means that the table shown in figure 6 with multiplier and multiple values is hard wired in a processing circuit. It will be clear to the skilled reader how an adder, divider, comparing will be implemented.

Using the digital processor according to the invention, it is possible to process letters at machine level. This means that a word like MOV can be coded in for example ABGED code and be processed by the processor, wherein the processor will process the cell chain containing the cells "M₅O₅V". The processing characters are stored (represented) by the processing units as a character of a high level computer language (such as Assembler or C)₅ and they are directly interpretable by the hardware of the digital processor. Natural languages, such as English or Turkish can be used to execute the digital processor. A combination of one or more programming characters will be executed by one or more processing units. The process letters can be organized like a sentence structure, e.g. subject, verbs, time, place and time etc. For example, the sign of the processing command "contr-p" will be stored by the DNA-A group, using the first 3 bits, this is helix 1 (followed by helix 2: the length_A and followed by helix 3: length_B).

Figure 7 shows a table of a possible coding used in an embodiment of the invention. The table shows the digital coding of symbols varying from the numeric values to capital letters. Each row of the table contains a simple cell with fixed length. The length of a cell may vary, as was described above. The bits of a cell core are referred to as

C(a), C(e), C(d), C(c), C(b). The DNA-C group contains information on the position of a symbol represented by the cell core. The bits in DNA-C group are referred to as DNA-C(a), DNA-C(d), DNA-C(c), DNA-C(b). Furthermore, the table of figure 7 contains a DNA-B group and a DNA-A group comprising the bits DNA-B (a), DNA- B(d), DNA-B(c), DNA-B(b) and DNA-A(a), DNA- A(c), DNA-A(b). Below, the meaning of the bits will be explained in more detail.

C(a) the key bit, this a sign bit which supplies the DNA-C processor information on the position of the cell in a cell chain, which can be (when the cell core is a number according to DNA-B) at the front or at the back of a comma or a fraction. This notation allows positions of 10 ^Λ30 (this means we can make a number like for example: "123 (which has 10^Λ30 digits), 1233 08" (which has 10^Λ30 digits after the comma)

C(e), C(d), C(c), C(b) a binary code representing a symbol or an exponential value, examples Core = <00011> represents the decimal value 3,

Core = <01101> represents a comma, Core = <>

The DNA-B group informs an arithmetic module about which position the cell has within a cell chain. A cell chain may for example be 543, representing a decimal value, hi the ABGED code, this decimal value may be represented by three cells in the cell chain. The position within the cell chain is encoded in the DNA-B group. The first bit of this group DNA-B(a) is the key bit. If this key bit is equal to 0, then the position of this cell in a cell chain is before the decimal comma. Please note that in English notation, the decimal point is used instead of the comma. So, if in this description the term decimal comma is used, it can also be read as decimal point. If the key bit of the cell core, i.e. C(a), is equal to 1, then the position of the cell in a cell chain is after the decimal comma. If there is no comma in the decimal value, depending on what kind of processing there has to be done, a comma will be created by a DNA-B manager in order to be able to execute the arithmetic instruction fetch. This is explained using an example:

25,5 [input A] added by 1 [input B] (both numbers are in decimal notation). Input B has no comma; but to be able to make the correct calculation the digital processor will introduce two new cells at input B and these cells have the following cell-chain codes:

DNA-A: helix l:<001> helix 2:<001> helix3 <001>; DNA-B: <000>; DNA-C: <00000>; Cell-core: <01101> which means a comma,

DNA-A: helix l:<001> helix 2:<001> helix3 <001>; DNA-B: <000>; >; DNA-C: <10001>; Cell-core: <00000> which means a zero.

The number of zeros required, depends of the number of positions that the input A has. This means that if the number of positions after the comma is two, the DNA-B has to introduce a same number of zeros (i.e. two zeros). After creation of additional cells, (i.e. activating additional processing units), it is now possible to perform the correct instruction, in this example: Input 1 25,5 ^■ Input 2 1.0 + The sum = 26,5

hi ABGED code the knowledge part of the N-bit data words also comprises a group called the DNA-B group, comprising coding for knowledge about the type of the symbol encoded in the core. This DNA-B group may, for example, comprise four bits, as shown in the table of figure 7. The first bit DNA-B(a) is the key bit. If this key bit is equal to 0, then the cell core contains a numeric value.

The DNA-B group may comprises several helixes. A helix is defined as a group of genes (i.e. bits) within a DNA-group, which are related to each other and are representing a specific interpretation of the DNA part of the cell. For reasons of simplicity, in the following example, the DNA-B group only comprises one helix with four bits.

DNA-B group first set of bits (i.e. helix) means positive number <0000> = + number. DNA-B Helixno. 1 Key bit a = 0 numerical <a d c b> following order of the genes 0 0 0 0 = + number

0 0 0 1 = constant base 10 (ratio = 10) exponential = 10^Λ+n [n = positive] 0 0 1 1 = constant base 10 (ratio = 10) exponential = 10 ^A-n [n = negative] 0 1 0 0 = variable base x^Λn (BCD) [x = positive] {in this DNA the x - value is stored} 0 1 0 1 = variable base -x^Λn (BCD) [x = negative] {in this DNA the x - value is stored}

0 1 1 0 = variable base x^Λn (BCD) [x = positive] {in this DNA the n — value is stored} 0 1 1 1 - variable base x^Λ-n (BCD) [n = negative] {in this DNA the n- value is stored}

If the key bit DNA-B (a)is equal to 1, then the cell core contains a letter, character or logical function.

Key bit a = 1 letter/character/ logical functions

<a d c b> following order of the genes

1 0 0 0 = Capital letter

1 0 0 1 = Small letter 1 0 1 0 = Arabic letter

1 0 1 1 = Special arabic letter

1 1 0 0 = Operational functions

1 1 0 1 = Characters

A third DNA group, called the DNA-A group, comprises three helixes, see table 1. In a first helix, information is stored on the number of helixes in the DNA-B group. In a second helix, information is stored on the number of helixes in the DNA-C group. In a third helix, information is stored at the start and end of an operation or of data, as was described above. Using this DNA-A group creates the possibility to process encoded data words with flexible length, making it possible to represent a very large number of values and/or symbol strings. If the second helix of DNA-A is <0010>, see table 1, it means that the position of the cell-core in a cell chain is represented by 2 digits, so in this case it can vary from 10 to 99.

hi figure 9, an example of a hardware implantation of a decoder is shown. A decoder comprises several logical gates receiving data form input gates and/or other logical gates.

The ABGED code contains "knowledge at bit level", i.e. what kind of value or symbol is stored in the cell core. By analyzing the bits in the different DNA groups, the knowledge on the data to be processed can be used. This makes it possible to perform mathematical operations on relatively short data words.

By introducing the concept of a chain of genes (the helix) and cells one can 'create a textbook' within a processor. The result is for example that 'the memory map can be addressed from 0 - 9 decimal, exponential from 0 to 9 and logarithmic scale 0 to 9.

Those memory maps can also be negative values.

As compared to the hexadecimal system (for example 000000H or FFFFFFH), in ABGED code the range of values can be 000....00000 - 999 99999 (64 numbers of 9) AAA.... AAAAA-ZZZ... ZZZZZ (also

64 characters)

Addressing can be done in a sequential order, or a register address can be given a specific name that defines the specific meaning of said cell represented by said register in a verb. Those verbs can be organized like the natural language grammar, so that addressing in a sequence of verbs (i.e. sentences) is possible.

If we want to make use of all the register addresses available then those are e.g. from 0 to 9; A to Z; a to z; 0 to -9 ; 0 to 9 at exponential scale; 0 to 9 at "+" or "-" LOG scale.

The addressing can be done in alphabetic vocabulary words combined with Extended Decimals. Even computer operation instructions as such can be represented by a specific sentence (i.e. chain of words) at the machine level, without the need for a translation from higher computer language to machine code, as is necessary when using for example Assembler.

By processing ABGED code, knowledge about an operand (e.g. is it a decimal value or an exponential value) is used before the actual calculation is performed. In an embodiment, the digital data in a core of a cell is decoded into a decimal value. With that value it is possible to process it in the decimal system. Besides the decimal system, different scales are used, like for example exponential or logarithmic scales, hi the processor according to the invention the basic algebra rules are implemented hardwired. Below, some examples are shown of decimal calculations which are processed by the invention using the same algebra rule as normally is done by a person.

300 + 1200 = 1500

3* 10 ^Λ2 + 12 * 10 ^Λ2 = (3+ 12) * (10^Λ2) = 15 * 10^A2 5,24*10 ^A5 - 3,12* 10 ^Λ2 = (5240) (10^Λ2)- (3,12) (10^Λ2)= (5240 - 3,12 )*10^Λ2 = 5236,88 *10^Λ2 = 52366 another possibility is 524000 - 312 = 52388

300* 1200 => (3* 10 ^Λ2 )*(12 * 10 ^Λ2) = (3* 12) * (10 ^Λ(2 +2 )) = 36 * 10^Λ4= 360.000

In the digital processor according to the invention, the number of logical operations for one calculation is small as compared to the state of the art. This will be explained using an example, hi this example the decimal operation 32*234 is executed using a BCD code.

32 00110010 234 001000110100

00000000 00000000 00110010 00000000

00110010 00110010 00000000 00000000 00000000 00110010 00000000 00000000

7488 = 0110010001000100 (BCD)

The ROC for this calculation is 0,0641 (way of calculation: 5 numbers/ above counted flip-flops 780 = 0,0641. If the values increases with 5 BCD-numbers, this calculation will increase exponential.

Using the digital processor according to the invention, developing artificial intelligence at bit level with extended decimal system (ABGED) the amount of calculation will decrease to

234 32* 468 702 7488 (ABGED) 10 flip-flop. ROC (ABGED) = 5/10 => 0,5

ABGED compared with the BCD is 0,5/0,000641= 780 % better than the existing systems. But, this ROC-value will increase if the amount of flip-flops operations for the translation from the compiler level to the binary level at the processor are included.

List of abbreviations

BCD Binary Coded Decimal

DNA Dynamic Numeric Access ABGED Artificial knowledge based Binary Coded extended exponential Decimal (ABCD written in Arabic language is read as AB-GED).

Claims

1. A digital processor comprising:

- a first processing unit (1) arranged to receive a first N-bit data word, and comprising: - a first decoder (3) arranged to receive a first part of said first N-bit data word and to decode said first part of said first N-bit data word into a first D-bit data word (5), wherein N₃ D are positive integers, and

- a second processing unit (2) arranged to receive a second N-bit data word, and comprising:

- a second decoder (4) arranged to receive a first part of said second N-bit data word and to decode said first part of said second N-bit data word into a second D-bit data word (7), and

- at least one instruction circuit arranged to receive an input instruction signal, and arranged to convert said input instruction signal into an activation signal using said first and said second knowledge signal, and arranged to activate one arithmetic module out of said plurality of arithmetic modules, so as to produce an output data word.

2. Digital processor according to claim 1, wherein said decoders (3,4) are arranged to convert binary code into an output code wherein only one bit is active at a time.

3. Digital processor according to any of the preceding claims, wherein each of said decoders comprises ten output gates, each output gate representing one decimal value.

4. Digital processor according to any of the preceding claims, wherein said processor comprises a plurality of processing units, and a plurality of arithmetic modules and at least one instruction circuit, wherein each of said plurality of processing units is arranged to decode a first part of a N-bit data word into a D-bit data word, and arranged to output said D-bit data word to at least one of said plurality of arithmetic modules, said plurality of arithmetic modules being arranged to be activated by activation signals produced by said at least one instruction circuit depending on knowledge signals produced by read out circuits comprised in said plurality of processing units.

5. Digital processor according to any of the preceding claims, wherein said second part of said first and second N-bit data word comprises three functional groups of bits.

6. Digital processor according to any of the preceding claims, wherein N is at least 26 bits.

7. A computer comprising a processor according to any of the preceding claims.

8. A method of processing digital data, comprising the steps of: - reading a first N-bit data word;

- decoding a first part of said first N-bit data word into a first D-bit data word, wherein N, D are positive integers;

- reading specific bits of a second part of said first N-bit data word so as to produce a first knowledge signal; - reading a second N-bit data word;

- decoding a first part of said second N-bit data word into a second D-bit data word;

- reading specific bits of a second part of said second N-bit data word so as to produce a second knowledge signal;

- converting an input instruction signal into an activation signal using said first and said second knowledge signal;

- performing one specific arithmetic operation out of a plurality of predefined arithmetic operations on said first and said second D-bit data word so as to produce an outcome, depending on said activation signal.