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WO2007010595A1 - Dispositif semi-conducteur et son procédé de fabrication - Google Patents

Dispositif semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2007010595A1
WO2007010595A1 PCT/JP2005/013238 JP2005013238W WO2007010595A1 WO 2007010595 A1 WO2007010595 A1 WO 2007010595A1 JP 2005013238 W JP2005013238 W JP 2005013238W WO 2007010595 A1 WO2007010595 A1 WO 2007010595A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
module substrate
manufacturing
chip
substrate
Prior art date
Application number
PCT/JP2005/013238
Other languages
English (en)
Japanese (ja)
Inventor
Hirotaka Nishizawa
Tamaki Wada
Junichiro Osako
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2005/013238 priority Critical patent/WO2007010595A1/fr
Priority to JP2007525462A priority patent/JPWO2007010595A1/ja
Publication of WO2007010595A1 publication Critical patent/WO2007010595A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09127—PCB or component having an integral separable or breakable part
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10598—Means for fastening a component, a casing or a heat sink whereby a pressure is exerted on the component towards the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0169—Using a temporary frame during processing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path

Definitions

  • the present invention relates to a semiconductor device and a manufacturing technique thereof, and particularly to a technique effective when applied to the manufacture of an IC card.
  • Card-type information media such as IC cards and memory cards are small, thin, and lightweight, and thus are excellent in portability, portability, and convenience, and are widely used in various fields.
  • An IC card is a card-type information medium in which an IC card chip is embedded in a cash card-sized plastic thin plate and information can be recorded, and is excellent in authenticity and tamper resistance.
  • IC cards are, for example, credit cards, cash cards, ETC (Electronic Toll Collection system) system cards, commuter passes, mobile phone card or authentication cards, etc., such as finance, transportation, communication, distribution and authentication. It is becoming increasingly popular in fields where high security is required.
  • FIG. 9 of Japanese Patent Laid-Open No. 2001-357376 has a configuration in which a SIM (Subscriber Identify Module) type card is fixed by providing a bridge at the opening of the frame card. It is disclosed.
  • SIM Subscriber Identify Module
  • a memory card is a card type information medium that employs a non-volatile memory (EEPROM, flash memory, etc.) as a storage medium, and is smaller than an IC card and writes large-capacity information at high speed. Can be read.
  • memory cards are widely used as recording media for portable information devices that require portability such as digital cameras, notebook personal computers, portable music players, and portable telephones.
  • Typical memory card standards include SD (Secure Digital) memory cards (standardized by the SD card association), miniSD, MMC (registered trademark of Multi Media Card, Infineon Technologies AG), RS — MMC (Reduced Size MMC).
  • a memory card is described in, for example, International Publication No. 02Z099742A1 (Patent Document 2).
  • Patent Document 2 For the purpose of improving security, a nonvolatile memory chip and a security card are described.
  • a configuration of a memory card is disclosed that includes an IC card chip that can execute processing and a controller chip that controls the circuit operation of these chips.
  • Patent Document 1 Japanese Patent Laid-Open No. 2001-357376
  • Patent Document 2 Pamphlet of International Publication No. 02Z099742A1
  • the present inventors have studied to improve the function of the IC card by mounting a nonvolatile memory chip on the IC card. As a result, the present inventors have found that how to efficiently manufacture an IC card is an important issue in the manufacturing process of an IC force loaded with a non-volatile memory chip! .
  • An object of the present invention is to provide a technique capable of efficiently manufacturing an IC card on which a nonvolatile memory chip is mounted.
  • a method of manufacturing a semiconductor device includes: (a) preparing a sheet-like multilayer printed circuit board (Print Circuit Board) in which a plurality of module boards are integrated; and (b) A step of mounting a semiconductor chip on a module substrate, (c) a step of electrically connecting the module substrate and the semiconductor chip, and (d) an individual module including the sheet-like laminated printed wiring board And a step of dividing the substrate into individual pieces.
  • the step (d) is characterized in that the module substrate force is divided into pieces including the protruding holding portion.
  • the module substrate divided into pieces is held on a tape substrate.
  • a semiconductor device includes (a) a module substrate, (b) a semiconductor chip mounted on the module substrate, and (c) a holding portion protruding from the module substrate cover.
  • the semiconductor chips mounted on the module substrate are connected in a tape shape.
  • An IC card equipped with a nonvolatile memory chip can be efficiently manufactured.
  • FIG. 1 is a plan view showing a manufacturing process of an IC card mounted with a nonvolatile memory chip in an embodiment of the present invention.
  • FIG. 2 is a plan view showing the manufacturing process of the IC card on which the nonvolatile memory chip is mounted following FIG. 1.
  • FIG. 3 is a plan view showing the manufacturing process of the IC card on which the nonvolatile memory chip is mounted following FIG. 2.
  • FIG. 4 is a plan view showing the manufacturing process of the IC card on which the nonvolatile memory chip is mounted following FIG. 3.
  • FIG. 5 is a plan view showing a module substrate provided with a holding portion.
  • FIG. 6A is a plan view showing one surface of a module substrate provided with a holding portion
  • FIG. 6B is a plan view showing the other surface of the module substrate provided with a holding portion.
  • FIG. 7 is a perspective view showing a module substrate provided with a holding portion.
  • FIG. 8 is a plan view showing a manufacturing process of the IC card on which the nonvolatile memory chip is mounted in the embodiment.
  • FIG. 9 is a perspective view showing the manufacturing process of the IC card on which the nonvolatile memory chip is mounted following FIG. 8.
  • FIG. 10 is a perspective view showing the manufacturing process of the IC card on which the nonvolatile memory chip is mounted following FIG. 9.
  • FIG. 11 is a perspective view showing a manufacturing process of the IC card on which the nonvolatile memory chip is mounted following FIG. 10.
  • FIG. 12 is a perspective view showing a manufacturing process of the IC card on which the nonvolatile memory chip is mounted following FIG. 11.
  • FIG. 13 is a perspective view showing the manufacturing process of the IC card on which the nonvolatile memory chip is mounted following FIG. 12.
  • FIG. 14 is a plan view showing one surface of an IC card on which a nonvolatile memory chip is mounted.
  • FIG. 15 is a plan view showing the other surface of the IC card on which the nonvolatile memory chip is mounted.
  • FIG. 16 is a diagram showing an example of a circuit configuration of an IC card chip.
  • FIG. 17 is a diagram showing an example of a circuit configuration of a controller chip.
  • FIG. 18 is a diagram for explaining an example in which the method for connecting the separated module substrate and the tape substrate is changed.
  • FIG. 19 is a diagram illustrating an example in which the shape of the holding portion provided on the separated module substrate is a T-shape.
  • FIG. 20 is a cross-sectional view showing a cross section taken along line AA in FIG.
  • FIG. 21 (a) is a cross-sectional view showing one process for realizing the connection shown in FIG. 19, and (b) is a cross-sectional view showing a process following (a).
  • FIG. 22 is a perspective view showing an example in which a step (offset) is provided in the holding portion of the tape substrate.
  • FIG. 23 is a perspective view showing another connection method of the module substrate holding unit and the tape substrate holding unit.
  • the number of elements when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly limited to a specific number when clearly indicated and in principle. Except in some cases, the number is not limited to the specific number, and may be a specific number or more.
  • a rigid substrate 2 is prepared in which a plurality of module substrates 1 (hatched /!) Are integrated.
  • a laminated printed circuit board is referred to as a rigid board.
  • the rigid substrate 2 is excellent in the formation of multilayer wiring and fine wiring, and is formed of, for example, glass epoxy resin.
  • the nonvolatile memory chip 3 and the controller chip 4 are stacked and mounted on the individual module substrates 1 formed on the rigid substrate 2.
  • the non-volatile memory chip 3 is formed with a rewritable non-volatile memory such as a flash memory
  • the controller chip 4 is formed with a circuit for controlling a write operation and a read operation of the non-volatile memory. Yes.
  • the nonvolatile memory chip 3 and the controller chip 4 are mounted at a position according to one side of the module substrate 1 that is not in the center of the module substrate 1. This is because the IC card chip is also efficiently mounted on the module substrate 1 as described later. For example, as shown in FIG.
  • the nonvolatile memory chip 3 and the controller chip 4 are mounted in a region opposite to the region where the corner portion chamfered with respect to the center of the module substrate 1 is provided.
  • the area for mounting the IC card chip is secured on the top. By securing an area for mounting an IC card chip in this way, a large-sized nonvolatile memory chip can be efficiently arranged.
  • the nonvolatile memory chip 3 and the module substrate 1 are electrically connected using a bonding wire 5.
  • the controller chip 4 and the module substrate 1 are electrically connected using the bonding wires 5.
  • the nonvolatile memory chip 3 and the controller chip 4 are electrically connected using bonding wires 5.
  • bonding pads are formed on the non-volatile memory chip 3, the controller chip 4 and the module substrate 1, and the bonding wires 5 are connected to these bonding pads.
  • the non-volatile memory chip 3 disposed in the lower layer does not use the bonding wire 5 but uses, for example, a bump substrate to form the module substrate 1 You may make it electrically connect with.
  • the bonding wire 5 is made of, for example, a gold wire.
  • the nonvolatile memory chip 3 and the controller chip 4 mounted on the module substrate 1 are sealed with a resin 6.
  • the minimum area required for sealing the nonvolatile memory chip 3, the controller chip 4 and the bonding wire 5 is not limited to forming the resin 6 so as to cover the entire module substrate 1. Sealed with 6. That is, the module substrate 1 is partially sealed by the resin 6.
  • components different from the nonvolatile memory chip 3 and the controller chip 4 such as an IC card chip are mounted on the module substrate 1, so that the IC card chip mounting area is sealed with the resin 6. This is because it is necessary to ensure it.
  • an IC card chip is exemplified as a component different from the nonvolatile memory chip 3 and the controller chip 4.
  • the present invention is not limited to this, and a passive element such as a capacitor may be provided as appropriate.
  • a plurality of module substrates 1 formed integrally with the rigid substrate 2 are separated into individual module substrates 1.
  • each module substrate 1 is cut so that the protruding holding portions 7 remain.
  • one feature is that the module board 1 is separated into pieces including the projecting holding portions 7 at the upper and lower portions of the module board 1 rather than the individual module board 1 alone. is there.
  • a rigid substrate with an integrated module substrate is used. And after mounting a non-volatile memory chip on each module substrate of a rigid substrate, it seals and separates into each module substrate.
  • the separated module board is shipped as a product to the IC card manufacturer. In this way, when using the existing non-volatile memory production line, it is desirable to ship individual module boards.
  • an IC card is manufactured using a tape-shaped substrate.
  • the IC card production line has a COT (Chip On Tape) structure in which an IC card chip is mounted on the continuous tape substrate.
  • COT Chip On Tape
  • the existing IC card production line even if an individual module board is carried in, an IC card chip cannot be mounted on the individual module board. In other words, it is desirable not to divide the module board into individual IC card production lines. Thus, the product form of the product delivered between the manufacturing companies becomes a problem.
  • the module substrate 1 on which the nonvolatile memory chip 3 is mounted when the module substrate 1 on which the nonvolatile memory chip 3 is mounted is separated, the module substrate 1 including the protruding holding portions 7 at the upper and lower portions is separated. Like to do. By doing so, as will be described later, it is possible to solve the problem of the product form of the product delivered between the manufacturing companies. For this reason, it is possible to efficiently manufacture an IC card equipped with the nonvolatile memory chip 3 using an existing manufacturing line at each manufacturing company.
  • FIG. 6 is a diagram showing the external appearance of the module substrate 1 that is separated into pieces including the holding unit 7. Fig 6
  • FIG. 6 (a) is a view of the surface of the module substrate 1 in the present embodiment.
  • a mold region covered with a resin 6 and an electrode (IC card chip mounting pattern) 8 are formed on the surface of the module substrate 1 in the present embodiment.
  • IC card chip mounting area on the surface of the module substrate 1 in the present embodiment.
  • FIG. 6B is a view of the back surface of the module substrate 1 in the present embodiment.
  • an IC card back electrode (ISO electrode 9) connected to the electrode 8 is formed on the back surface of the module substrate 1 in the present embodiment.
  • an extended electrode 10 connected to the nonvolatile memory chip 3 and the controller chip 4 covered with the resin 6 is formed.
  • FIG. 7 is a perspective view showing the module substrate 1 singulated including the holding unit 7. As shown in FIG.
  • a non-volatile memory chip 3 is mounted on the module substrate 1, and a controller chip 4 is mounted on the non-volatile memory chip 3.
  • the nonvolatile memory chip 3 and the controller chip 4 are connected to the module substrate 1 via bonding wires 5.
  • a resin 6 is formed so as to cover the nonvolatile memory chip 3 and the controller chip 4.
  • an electrode 8 is formed in a region not covered with the resin 6.
  • An IC card chip mounting area 11 is formed between the electrodes 8.
  • a conductor pattern 12 made of a conductor film is formed on the holding portion 7 on the IC card chip mounting area 11 side.
  • the conductor pattern 12 is formed of, for example, a gold film, and is formed to improve the releasability of the resin formed on the gate when the IC card chip described later is molded. Further, the conductor pattern 12 is provided so as to extend to the inner side (center side of the module substrate 1) than the outer periphery of the module substrate 1 excluding the holding portion 7. By forming the conductor pattern 12 in this way, the above-described exfoliation of the resin can be further prevented.
  • the electrical characteristic inspection of the nonvolatile memory chip 3 and the like takes a long test time, but by processing a plurality of separated module substrates 1 in parallel, the non-defective product or defective product is selected. This improves the efficiency of the inspection of physical characteristics.
  • the holding unit 7 is provided on the singulated module substrate 1.
  • the holding unit 7 is provided, and an existing characteristic test for inspecting the electrical characteristics of the module substrate is performed.
  • the electrical characteristics of the module substrate 1 provided with the holding portion 7 can be inspected by using a handler or test socket for transferring the module substrate in common or by making small changes. For this reason, the electrical property inspection can be efficiently performed using the existing production line.
  • a heat-resistant tape substrate 13 such as stainless steel is prepared.
  • the tape substrate 13 is provided with a plurality of module substrate mounting areas, for example, by punching a hoop material to provide a space.
  • a holding portion 14 is provided so as to protrude into the module substrate mounting area of the tape substrate 13.
  • the separated module substrate 1 is connected to the tape substrate 13 configured as described above.
  • the holding portion 7 provided on the module substrate 1 is disposed on the holding portion 14 provided on the tape substrate 13, and the holding portion 14 is bent (see FIG. 9).
  • the holding part 7 and the holding part 14 are mechanically connected by caulking. As a result, a plurality of individual module substrates 1 can be connected to the tape substrate 13.
  • a plurality of individual module substrates 1 can be mounted on one tape substrate 13. That is, by providing the holding portion 7 on the module substrate 1 that has been separated, the module substrate 1 that has been separated once can be easily mounted on the tape substrate 13 again.
  • the steps up to here are performed on a manufacturing line of a manufacturing company that manufactures a nonvolatile memory. In a production line in which the nonvolatile memory chip 3 is mounted on the module substrate 1, the module substrate 1 is separated into individual pieces, and then the module is mounted on the tape substrate 13 again using the holding portion 7 provided on the module substrate 1. Board 1 is connected.
  • the module substrate 1 By mounting the module substrate 1 on the tape substrate 13 in this manner, the module substrate 1 can be shipped in the form of a tape to the production line of the manufacturer that manufactures the IC card. As a result, the problem of the product form of the product delivered between the manufacturing companies can be solved.
  • the module substrate 1 is connected to the tape substrate 13 so that the module substrate 1 is separated into individual pieces and then shipped again in a tape form. Therefore, in the nonvolatile memory production line, it is conceivable that the module substrate 1 is not separated into individual pieces, but is shipped after the process is performed integrally with the rigid substrate 2.
  • the following inconvenience arises if the module substrate 1 is not separated. That is, the electrical characteristic inspection of the nonvolatile memory basically has many test items and a long test time. For this reason, the module substrate 1 is separated into pieces, and a plurality of nonvolatile memories are simultaneously inspected in parallel. According to this method, when a defective product is found, the defective product is removed at that time, and a new module substrate 1 can be set in the vacant test socket by removing the defective product. For this reason, the electrical characteristic inspection can be performed efficiently.
  • the electrical characteristics can be inspected only in series for the nonvolatile memories arranged in a tape shape. Inefficient with memory.
  • the electrical property inspection is performed in the state of the individual module substrate 1! /, So the electrical property inspection is performed in the state of the integrated rigid substrate 2. To implement it, it is necessary to change the configuration to be different from the existing production line. For this reason, it is necessary to divide the module substrate 1 into pieces in the nonvolatile memory production line.
  • the present invention is not limited to this.
  • the structure of a heat-resistant resin sheet or heat-resistant paper paper is used. You may do it.
  • Heat resistance is required for the material of the tape substrate 13 because the tape substrate 13 must withstand the heating when sealing the IC card chip mounted on the module substrate 1 in the IC card manufacturing line described later. There is also some power. Therefore, the material of the tape substrate 13 is required to have heat resistance enough to withstand the heating when sealing the IC card chip.
  • a resin sheet, heat-resistant paper or non-woven cloth is used as the tape substrate 13, the connection between the tape substrate 13 and the separated module substrate 1 is not a mechanical connection.
  • an adhesive is used. It can be a connection. Further, instead of an adhesive, a tape-like substrate can be fused and connected.
  • IC force chip 15 is mounted on each module substrate 1 connected to tape substrate 13.
  • the IC card chip 15 is mounted in the IC card chip mounting area of the module substrate 1.
  • the IC card chip 15 and the electrode 8 are electrically connected using a bonding wire 16.
  • the bonding wire 16 is made of, for example, a gold wire.
  • the IC card chip 15 and the bonding wire 16 are sealed with a resin 17.
  • Sealing with the resin 17 can use, for example, a transfer molding method.
  • the runner Z gate portion into which the resin 17 flows can be formed in the holding portion 7 of the module substrate 1.
  • the conductor pattern 12 made of a gold film is formed on the holding portion 7, the releasability of the resin 17 formed on the runner Z gate portion of the holding portion 7 is improved.
  • the resin 17 is, for example, injected into the runner Z gate portion formed in the holding portion 7 from the upper direction of the module substrate 1. It is formed so as to cover the IC card chip 15 mounted on the module substrate 1 from the cover part cover.
  • the individual module substrates 1 are separated from the tape substrate 13 to which the module substrate 1 is connected. At this time, the module substrate 1 is cut at the connection portion between the holding unit 7 and the module substrate 1.
  • a cutting method for cutting both the module substrate 1 and the resin 17 for example, a method using a mold, a water jet method, or a cutting method using a diamond saw can be used.
  • FIGS. 14 and 15 an IC card as shown in FIGS. 14 and 15 can be manufactured by embedding the module substrate 1 singulated into a plastic card substrate 18.
  • FIG. 14 is a view showing one side of the completed IC card
  • FIG. 15 is a view showing the side opposite to FIG.
  • the sealing portion in the region where the nonvolatile memory chip and its controller are mounted is separated from the sealing portion in the region where the IC card chip is mounted.
  • a nonvolatile memory chip is mounted on a module substrate on a nonvolatile memory production line, and the module substrate is separated into pieces.
  • the module substrate is provided with a holding portion, and after the electrical characteristic inspection is performed, the module substrate is connected to the tape substrate using the holding portion.
  • the module board integrated in a tape shape is shipped to the IC card production line.
  • the IC card is manufactured using a module substrate integrated in a tape shape. Therefore, since existing facilities can be used in both the nonvolatile memory production line and the IC card production line, an IC card equipped with the nonvolatile memory can be efficiently produced. Ie
  • the existing nonvolatile memory production line individual module boards are shipped, and in the existing IC card production line, a module board integrated in a tape shape is used. IC card is manufactured. At this time, when transferring the module substrate from the nonvolatile memory production line to the IC card production line, it is desirable to deliver the module substrate with a tape substrate in which the module substrate is integrated, but the module substrate is separated into pieces. Because It becomes a problem. However, in the present embodiment, the separated module substrate is integrated with the tape substrate by the holding portion. Therefore, after performing the process by the non-volatile memory production line, a plurality of module substrates are provided. The module board can be delivered to the IC card production line in a tape-like state.
  • IC card chip 20 (corresponding to IC card chip 15 in FIG. 10), nonvolatile memory chip 21 (corresponding to nonvolatile memory chip 3 in FIG. 7), and controller chip 22 (controller chip in FIG. 7) 4) will be described.
  • a nonvolatile memory circuit such as a flash memory capable of electrically erasing and writing data is formed on the main surface of the nonvolatile memory chip 21, for example.
  • the storage capacity of the nonvolatile memory chip 21 is larger than that of the memory parts of the other IC card chip 20 and controller chip 22.
  • the bonding node on the main surface of the nonvolatile memory chip 21 is electrically connected to the module substrate through bonding wires.
  • the bonding wire also has, for example, gold (Au) fine wire equal force.
  • a plurality of memory cells constituting the memory circuit of the non-volatile memory chip 21 increase the threshold voltage when electrons are injected into, for example, the floating gate of the memory cell, and also pull out the electrons at the floating gate.
  • the memory cell stores information corresponding to the level of the threshold voltage with respect to the word line voltage for reading data.
  • the threshold voltage of the memory cell transistor is low, the state is the erase state, and the state is the high state.
  • an IC card microcomputer circuit On the main surface of the IC card chip 20, for example, an IC card microcomputer circuit is formed.
  • This IC card microcomputer circuit has a function as a security controller. For example, it is an ISOZIEC 15408 evaluation / certification body that can be used for electronic payment services. Authenticated function by is realized.
  • This IC card microcomputer circuit is, for example, CPU (Central Processing Unit), Mask ROM (Read Only Memory), RAM (Random Access Memory), EEPROM (Electrically Erasable Programmable ROM) and other arithmetic circuits It has the integrated circuit like.
  • the mask ROM stores, for example, execution programs and encryption algorithms.
  • the RAM has a function as a memory for data processing, for example.
  • the EEPROM also functions as a data storage memory.
  • the IC card on which this IC card chip 20 is mounted sends a predetermined authentication certificate stored in the EEPROM and is subject to subsequent authentication on the condition that authentication is obtained. Communication processing is now possible.
  • Such a security processing operation program is owned by Mask ROM!
  • FIG. 16 shows an example of an IC card microcomputer circuit in the IC card chip 20.
  • IC card microcomputer circuit is CPU20a, RAM20b as work RAM, timer 20c, EEPRO M20d, coprocessor unit 20e, mask ROM20f, system control logic 20g, I / O port (IZO port) 20h, data bus 20i and address bus 20j have.
  • the mask ROM 20f is used to store an operation program (encryption program, decryption program, interface control program, etc.) and data of the CPU 20a.
  • the RAM 20b is a work area of the CPU 20a or a temporary storage area for data, and is composed of, for example, SRAM or DRAM.
  • the system control logic 20g decodes this and causes the CPU 20a to execute a processing program necessary for executing the command. That is, the CPU 20a fetches an instruction by accessing the mask ROM 20f at an address instructed by the system control logic 20g, decodes the fetched instruction, and performs operand fetch and data operation based on the decoding result.
  • the coprocessor unit 20e performs a remainder calculation process in RSA or elliptic curve cryptography according to the control of the CPU 20a.
  • the IZO port 20h has a 1-bit input / output terminal IZO, and is also used for data input / output and external interrupt signal input.
  • the I / O port 20h is coupled to the data bus 20i and is connected to the data bus 20i.
  • CPU 20a, RAM 20b, timer 20c, EEPROM 20d and coprocessor The subunit 20e etc. are electrically connected.
  • the system control logic 20g controls the operation mode and interrupt of the IC card microcomputer circuit, and further includes a random number generation logic used to generate an encryption key.
  • the IC card microcomputer circuit is initialized, and the CPU 20a starts executing the instruction from the start address of the program in the EEPROM 20d.
  • the IC card microcomputer circuit operates in synchronization with the clock signal CLK.
  • the EEPROM 20d is electrically erasable and writable, and is used as an area for storing data such as ID (Identification) information and an authentication certificate used for identifying an individual.
  • a flash memory or a ferroelectric memory may be used instead of the EEPRPM20d.
  • the IC card microcomputer circuit supports a contact interface that uses an external terminal to interface with the outside.
  • an interface controller circuit is formed on the main surface of the controller chip 22.
  • the interface controller circuit has a function of controlling an external interface operation and a memory interface operation in accordance with a control mode according to an instruction from the outside or a setting determined in advance inside.
  • the function of the interface controller circuit recognizes the memory card interface control mode according to the state of commands and buses exchanged with external devices via the external connection terminals. It also switches the bus width according to the recognized memory card interface control mode and converts the data format according to the recognized memory card interface control mode. Furthermore, it performs a power-on reset function, interface control with the IC card microcomputer circuit in the IC card chip 20, interface control with the memory circuit in the nonvolatile memory chip 21, power supply voltage conversion, and the like. These operations may be performed in whole or in part depending on the purpose of use.
  • FIG. 17 shows an example of the interface controller circuit 22.
  • a memory circuit 21a in FIG. 17 indicates a memory circuit formed in the nonvolatile memory chip 21.
  • the interface controller circuit 22 has a host interface circuit 22a, a micro computer 22b, a flash controller 22c, a buffer controller 22d, a buffer memory 22e, and an IC card interface circuit 22f.
  • the buffer memory 22e is composed of DRAM or SRAM.
  • IC card interface circuit 22f has IC card microcomputer Circuit 20 is electrically connected.
  • the microcomputer 22b has a CPU (central processing unit) 2 2b 1, a program memory (PGM) 22b2 that holds an operation program for the CPU 22bl, a work memory (WRAM) 22b3 used for a work area of the CPU 22bl, and the like.
  • the host interface circuit 22a detects the issuance of a memory card initialize command or the like, the host interface circuit 22a makes it possible to execute an interface control mode control program corresponding to the microcomputer 22b by an interrupt.
  • the microcomputer 22b controls the external interface operation by the host interface circuit 22a by executing its control program. It also controls access (write, erase and read operations) and data management to the memory circuit 21a by the flash controller 22c, and the data format specific to the memory card by the buffer controller 22d and the common data format for the memory. Controls format conversion between.
  • the data read from the memory circuit 21a or the data written to the memory circuit 21a is temporarily stored in the nother memory 22e.
  • the flash controller 22c can operate the memory circuit 21a as a hard disk compatible file memory and manage data in units of sectors.
  • the flash controller 22c includes an ECC circuit (not shown), adds an ECC code when storing data in the memory circuit 21a, and performs error detection and correction processing using the ECC code on the read data. It is also possible to omit the IC card interface 22f according to the purpose of use.
  • FIG. 18 is a diagram for explaining an example in which the method of connecting the separated module substrate 1 and the tape substrate 13 is changed.
  • FIG. 9 shows an example in which the holding portion 7 provided on the module substrate 1 is connected to the upper portion of the holding portion 14 provided on the tape substrate 13.
  • the holding part 7 provided on the module substrate 1 is connected so as to be covered with the holding part 14 provided on the tape substrate 13.
  • the tape substrate 13 is made of a metal material such as stainless steel, for example, it is possible to prevent grease leakage even if a runner Z-gate is formed on the tape substrate 13 with high processing accuracy. It is. Note that, since the holding portion 7 formed on the module substrate 1 is made of, for example, a resin, the variation in the thickness becomes large. For this reason, when sealing with grease, it is necessary to prevent leakage of grease by suppressing it with a movable plate that absorbs variations in thickness from the back side of the holding portion 7.
  • FIG. 19 is a diagram for explaining an example in which the shape of the holding portion 7 provided on the separated module substrate 1 is a letter shape.
  • through-holes 26 are provided in a T-shaped holding portion 7, and individual module substrates 1 are connected by passing connection members 27 through the through-holes 26. Even with this configuration, it is possible to force the module substrate 1 together.
  • the configuration shown in FIG. 19 has an advantage that it is not necessary to prepare a new tape substrate because the holding unit 7 itself has a role as a tape substrate in which the holding unit 7 is integrated.
  • the connecting member 27 can also constitute a metal material force, for example.
  • the holding portion 7 is provided with a transport hole 26a.
  • FIG. 20 is a cross-sectional view showing a cross section taken along line AA in FIG. As shown in FIG. 20, it can be seen that the connecting member 27 is inserted into the through hole 26 provided in the holding portion 7 and is pressed. A method of connecting the holding portion 7 provided with the through hole 26 with the connecting member 27 will be described with reference to FIG. As shown in FIG. 21 (a), a U-shaped connecting member 27 is inserted into through holes 26 formed in different holding portions 7. Then, as shown in FIG. 21 (b), the upper part of the inserted connecting member 27 is bent to caulk the connecting member 27. In this way, a plurality of module substrates can be connected using the T-shaped holding portion 7.
  • FIG. 22 is a view showing an example in which a step (offset) 28 is provided in the holding portion 14 of the tape substrate 13.
  • a step (offset) 28 is provided in the holding portion 14 of the tape substrate 13.
  • the step 28 increases the thickness of the holding portion of the module substrate when the holding portion of the module substrate and the holding portion 14 of the tape substrate 13 are connected. Since absorption is possible, the surface of the module substrate and the height of the tape substrate 13 can be aligned.
  • FIG. 23 is a diagram showing another method of connecting the holding unit 7 of the module substrate 1 and the holding unit 14 of the tape substrate 13. As shown in FIG. 23, a through hole 29 is provided in the holding portion 7 provided in the module substrate 1. Then, the protruding holding portion 14 is inserted into the through hole 29. Then, the holding part 7 and the holding part 14 are connected by bending. With this configuration, a plurality of module substrates 1 can be connected to the tape substrate 13.
  • the present invention can be widely used in the manufacturing industry for manufacturing IC cards equipped with nonvolatile memory chips.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Credit Cards Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Technique permettant de fabriquer efficacement une carte de circuit imprimé sur laquelle est monté une puce mémoire non volatile. Une puce mémoire non volatile est montée sur un substrat de module (1) sur une ligne de fabrication de mémoire non volatile, et la puce de mémoire est scellée avec une résine (6). Ensuite, le substrat de module (1) est séparé entre chaque élément. À ce moment, une section de maintien (7) est ajoutée au substrat de module (1), et après une inspection des caractéristiques électriques, le substrat de module (1) est connecté à une carte de circuit imprimé (13) au moyen de la section de maintien (7). Ensuite, les substrats de modules (1) intégrés sous forme de bande sont envoyés sur la ligne de fabrication de la carte de circuit imprimé. Sur la ligne de fabrication de la carte de circuit imprimé, les cartes de circuit imprimé sont fabriquées au moyen des substrats de modules (1) intégrés sous forme de bande.
PCT/JP2005/013238 2005-07-19 2005-07-19 Dispositif semi-conducteur et son procédé de fabrication WO2007010595A1 (fr)

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JP2007525462A JPWO2007010595A1 (ja) 2005-07-19 2005-07-19 半導体装置およびその製造方法

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Publication number Priority date Publication date Assignee Title
WO2010095612A1 (fr) * 2009-02-23 2010-08-26 ソニー株式会社 Dispositif de mémoire
US20150085461A1 (en) * 2013-09-20 2015-03-26 Ibiden Co., Ltd. Combined wiring board and method for manufacturing combined wiring board
EP2407014B1 (fr) * 2009-03-09 2017-05-17 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé et système de connexion d'une pluralité de cartes de circuit imprimé à au moins un élément support ou cadre

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JPH11307679A (ja) * 1998-04-20 1999-11-05 Nec Saitama Ltd ボール・グリッド・アレイ型パッケージ
JP2000138307A (ja) * 1998-10-29 2000-05-16 Hitachi Cable Ltd 半導体装置用中間製品
JP2001033748A (ja) * 1999-07-26 2001-02-09 Dainippon Ink & Chem Inc 液晶表示素子
JP2001210750A (ja) * 2000-01-27 2001-08-03 Nec Corp 半導体装置
JP2005122657A (ja) * 2003-10-20 2005-05-12 Renesas Technology Corp Ｉｃカード

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Publication number Priority date Publication date Assignee Title
JPH1098060A (ja) * 1996-09-21 1998-04-14 Rohm Co Ltd 電子部品の製造方法及びその電子部品の検査方法
JPH11307679A (ja) * 1998-04-20 1999-11-05 Nec Saitama Ltd ボール・グリッド・アレイ型パッケージ
JP2000138307A (ja) * 1998-10-29 2000-05-16 Hitachi Cable Ltd 半導体装置用中間製品
JP2001033748A (ja) * 1999-07-26 2001-02-09 Dainippon Ink & Chem Inc 液晶表示素子
JP2001210750A (ja) * 2000-01-27 2001-08-03 Nec Corp 半導体装置
JP2005122657A (ja) * 2003-10-20 2005-05-12 Renesas Technology Corp Ｉｃカード

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Publication number Priority date Publication date Assignee Title
WO2010095612A1 (fr) * 2009-02-23 2010-08-26 ソニー株式会社 Dispositif de mémoire
US8856426B2 (en) 2009-02-23 2014-10-07 Sony Corporation Memory device
EP2407014B1 (fr) * 2009-03-09 2017-05-17 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Procédé et système de connexion d'une pluralité de cartes de circuit imprimé à au moins un élément support ou cadre
US20150085461A1 (en) * 2013-09-20 2015-03-26 Ibiden Co., Ltd. Combined wiring board and method for manufacturing combined wiring board
US9844151B2 (en) * 2013-09-20 2017-12-12 Ibiden Co., Ltd. Method for manufacturing combined wiring board

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