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WO2007019339A2 - Systeme de recuperation d'horloge et de donnees - Google Patents

Systeme de recuperation d'horloge et de donnees Download PDF

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Publication number
WO2007019339A2
WO2007019339A2 PCT/US2006/030501 US2006030501W WO2007019339A2 WO 2007019339 A2 WO2007019339 A2 WO 2007019339A2 US 2006030501 W US2006030501 W US 2006030501W WO 2007019339 A2 WO2007019339 A2 WO 2007019339A2
Authority
WO
WIPO (PCT)
Prior art keywords
clock
phase
data
signal
clock signal
Prior art date
Application number
PCT/US2006/030501
Other languages
English (en)
Other versions
WO2007019339A3 (fr
Inventor
Phillip Johnson
Zheng Chen
Barry Britton
Original Assignee
Lattice Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lattice Semiconductor Corporation filed Critical Lattice Semiconductor Corporation
Publication of WO2007019339A2 publication Critical patent/WO2007019339A2/fr
Publication of WO2007019339A3 publication Critical patent/WO2007019339A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Definitions

  • the present invention relates to electronics, and, in particular, to clock-and-data- recovery circuits.
  • a receiver can perform clock-and-data-recovery (CDR) processing to recover a clock signal from each data stream, where the clock signal is derived based on the timing of the data represented in the data stream.
  • CDR clock-and-data-recovery
  • a typical CDR circuit comprises a sampling clock generator, such as a phase-locked loop (PLL) or a delay-locked loop (DLL), that generates one or more sampling clocks used to sample the received data stream.
  • PLL phase-locked loop
  • DLL delay-locked loop
  • a single receiver may receive multiple, different data streams, potentially having different data rates. Such a receiver will typically have a different CDR circuit for each different data stream. Implementing multiple CDR circuits, each with its own sampling clock generator can require too much layout area and/or operating power for some integrated circuit applications.
  • the present invention is a clock-and-data recovery system, comprising a clock generator and one or more channel circuits.
  • the clock generator generates a plurality of phase-offset clock signals
  • each channel circuit generates an output data stream and a recovered clock signal based on an input data signal.
  • Each channel circuit comprises a data for each phase-offset clock signal, a logic circuit, and a data sampler.
  • Each data register generates an output signal based on the level of the corresponding phase-offset clock signal at a transition in the input data signal.
  • the logic circuit processes the output signals from the data registers to select one of the phase-offset clock signals as a sampling clock signal, and the data sampler samples the input data signal based on the sampling clock signal to generate the output data stream and generates the recovered clock signal based on the sampling clock signal.
  • the present invention is a clock-and-data recovery system, comprising a clock generator and two or more channel circuits coupled to the clock generator.
  • the clock generator generates a plurality of phase-offset clock signals.
  • Each channel circuit generates an output data stream and a recovered clock signal based on an input data signal and the plurality of phase-offset clock signals.
  • Fig. 1 is a block diagram of a clock-and-data-recovery system, according to one embodiment of the present invention
  • Fig. 2 is a more-detailed block diagram of one possible implementation of the CDR system of Fig. 1;
  • Fig. 3 shows an exemplary timing diagram illustrating the relationship between the input data signal and the sixteen clock signals of Fig. 2.
  • Fig. 1 is a block diagram of a clock-and-data-recovery system 100, according to one embodiment of the present invention.
  • CDR system 100 has a multi-phase clock generator 102 and N CDR channel circuits 104, where N31.
  • Clock generator 102 generates a multi-phase set of clock signals 106 (i.e., multiple versions of a clock signal sequentially separated from each other in phase over one clock period by a specified phase-offset increment). For example, in one implementation, clock generator 102 generates 16 clock signals, each having the same frequency, but separated in phase from the previous clock signal by about 22.5 degrees. Clock signals 106 are all applied to each CDR channel circuit 104, which uses the set of clock signals to generate a (different) recovered clock signal 110 and a (different) output data stream 112 from a corresponding (different) input data signal 108, potentially having different data rates.
  • Fig. 2 is a more-detailed block diagram of one possible implementation of CDR system 100 of Fig. 1. Although Fig. 2 shows only one CDR channel circuit 104, the implementation may include other, similar CDR channel circuits.
  • multi-phase clock generator 102 is a delay-locked loop (DLL) that is capable of selectively generating either 16 clock signals (separated by phase-offset increments of about 22.5 degree) or 8 clock signals (separated by phase-offset increments of about 45 degrees).
  • a received reference clock (REFCLK) is applied to the first delay element in delay chain 204, where each delay element in the chain delays the reference clock by an incremental amount of time, which corresponds to a reasonably predictable amount of phase for a given clock rate.
  • Each clock signal 106 corresponds to the output of (a different) one of the delay elements in delay chain 204, as selected using a corresponding multiplexer (not shown) in delay chain 204.
  • the number of delay elements in delay chain 204 and the number of clock signals output from delay chain 204 are metal mask programmable.
  • delay chain 204 receives, from PD/ALU 202, 16 DelNumber values, each of which dictates the number of delay elements in delay chain 204 between a different pair of successive clock signals 106.
  • reference clock REFCLK has a period of 100 nsec
  • each delay element in delay chain 204 delays the reference clock by 1 nsec (i.e., corresponding to a phase shift of about 3.6 degrees)
  • clock generator 102 is configured to generate 16 clock signals.
  • the sixteen clock signal 106 would be selected to be the output from the 100 fll (i.e., 6+6+7+6+6+6+7+6+6+6+7+6+6+6+7+6+6+7+6) delay element in delay chain 204, where that sixteenth clock signal corresponds to reference clock REFCLK delayed by 100 nsec (i.e., one complete 360-degree clock cycle of REFCLK).
  • the 8 clock signals 106 could be generated using (12, 13, 12, 13, 12, 13, 12, 13) as the 8 DelNumber values, where the eighth clock signal would correspond to reference clock REFCLK delayed by one complete clock cycle.
  • the values used in these examples are for purposes of explanation only; actual values may be larger or smaller.
  • the last selected clock i.e., either the sixteenth clock signal or the eighth clock signal, depending on whether clock generator 102 is configured to generate 16 or 8 clock signals
  • PD/ALU 202 generates the phase difference between REFCLK and DelClk and uses that phase difference to adjust the DelNumber values as necessary to ensure that those two clock signals are as close to being in phase (i.e., separated by one complete clock cycle of REFCLK) as possible.
  • PD/ALU 202 sets the 1-bit status signal MASTER LOCK to a value (e.g., 1) that indicates that clock signals 106 are valid.
  • CDR channel circuit 104 receives input data signal 108 and (up to) 16 clock signals 106, referred to as CLKO-CLKl 5.
  • CDR channel circuit 104 has 16 data registers 206 (e.g., flip-flops, although other types of data registers are possible) arranged in two banks 208 and 210, where input data signal 108 is applied to the clock input of each flip-flop. In bank 208, each of the first eight clock signals CLK0-CLK7 is applied to the data input of a different flip-flop.
  • bank 210 also has a (2Hl) multiplexer (mux) 212 for each flip-flop, where one of the second eight clock signals CLK8-CLK15 is applied to the "0" input of each mux 212 and a corresponding one of the first eight clock signals CLK0-CLK7 is applied to the mux's "1" input.
  • the output of each mux 212 is applied to the data input of the corresponding flip-flop 206, where the selection of which received clock signal to apply is dictated by control signal CLK_WTDTH.
  • a different one of the 16 clock signals CLKO-CLKl 5 is applied to the data input of a different one of the 16 flip-flops 206, while input data signal 108 is applied to the clock input of each flip-flop.
  • flip-flops 206 are triggered by rising edges (in alternative implementations, falling-edge-triggered flip-flops could be used)
  • input data signal 108 e.g., corresponding to a data transition from a "0" to a "1”
  • each flip-flop will (substantially) simultaneously present the current value of its received clock signal CLKz as its output value Qi.
  • reference clock REFCLK and each clock signal 106 has a 50% duty cycle
  • the values of half of clock signals 106 will be high, and the values of the rest will be low.
  • clock signals CLKO-CLKl 5 represent a sequence of increasingly phase-offset clock signals, eight consecutive clock signals 106 will be either high or low and the rest will be the opposite.
  • Fig. 3 shows an exemplary timing diagram illustrating the relationship between input data signal 108 and the sixteen clock signals CLK0-CLK15.
  • the portion of input data signal 108 shown in Fig. 3 corresponds to a bit sequence of (0 1 0 0 1) and has rising transitions at times tl and t3 and a falling transition at time t2.
  • clocks CLK0-CLK2 and CLKl 1 -CLKl 5 are high and eight consecutive clocks CLK3-CLK10 are low.
  • clock selector logic 214 analyzes the 16 Q/ values to select one of clock signals CLK/ as selected clock 216 for input to processing block 218.
  • clock selector logic 214 selects a clock 180 degrees away (e.g., CLKl 1) for use as selected clock 216. If the transition were a 0-to-l transition, then clock selector logic 214 would select one of the clocks corresponding to the transition, rather than looking 180 degrees away.
  • processing block 218 receives input data signal 108 and control signal BIT WIDTH.
  • processing block 218 samples input data signal 108 at every rising edge of selected clock 216 to generate sampled data.
  • processing block 218 is capable of outputting the sampled data as a serial or parallel data stream, where the parallelism of output data stream 112 is controlled by the value of control signal BITJWIDTH, such that output data stream 112 can be up to 4 bits wide.
  • processing block 218 has a clock divider that divides selected clock 216 by the same value dictated by the BIT-WIDTH control signal to generate recovered clock signal 110 as a divided version of selected clock 216.
  • downstream digital logic e.g., used to decode the output data
  • downstream digital logic is able to run at a lower frequency.
  • a f ⁇ rst-in, first-out (FIFO) buffer can be used to re-time the data to make chip routing less of an issue.
  • CDR channel circuit 104 can operate at a higher frequency than during the 16-phase mode.
  • the maximum frequency of the clock generator is a function of the number of phases and the intrinsic delay of each delay element. For example, if each delay element has a minimum delay of 1 ns, then the maximum frequency of clock generator 102 for the 16-phase mode would be 1/(16 ns) or about 62.5 MHz. For the 8- phase mode, however, the maximum frequency of the clock generator would be 1/(8 ns) or about 125 MHz.
  • the frequency of input data signal 108 is the same as the frequencies of clock signals CLKO-CLKl 5. In general, that need not be true. As a result, clock selector logic 214 may need to constantly change which clock signal is used for selected clock 216.
  • clock selector logic 214 there are limits placed on which clock signals can be selected by clock selector logic 214. For example, in one possible implementation, at each cycle of the control loop, clock selector logic 214 can change the selected clock by at most one clock signal in either direction from the previously selected clock signal. If the desired change is greater than the specified limit, then the control loop is not correctly locked to the data, and lock signal LOCK is set low by clock selector logic 214.
  • VCOs multi-phase voltage-controlled oscillators
  • the present invention has been described in the context of a CDR system capable of generating either 8 or 16 different clock signals, other embodiments may generate other numbers of phase-offset clock signals, including only one number of clock signals or more than two different numbers of clock signals.
  • circuits including possible implementation as a single integrated circuit, a multi chip module, a single card, or a multi card circuit pack
  • present invention is not so limited.
  • various functions of circuit elements may also be implemented as processing blocks in a software program.
  • Such software may be employed in, for example, a digital signal processor, micro controller, or general purpose computer.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Cette invention concerne un système de récupération d'horloge et de données (CDR) comportant un générateur d'horloge multiphase qui génère des signaux d'horloge à déphasage ainsi qu'un ou plusieurs circuits de canaux recevant chacun un signal de données d'entrée (différent) et tous les signaux d'horloge à déphasage et générant un flux de données de sortie et un signal d'horloge récupérée. Chaque circuit de canal comprend des registres de données (tels que des registres à bascules) qui reçoivent chacun le signal de données d'entrée au niveau de son port d'entrée d'horloge et un signal d'horloge à déphasage différent au niveau de son port d'entrées de données de façon que le registre à bascules soit déclenché à chaque front (montant) dans le signal de données d'entrée. Le circuit de canal traite les sorties des différents registres à bascules pour sélectionner un signal d'horloge à déphasage à utiliser pour échantillonner le signal de données d'entrée pour générer le flux de données de sortie, le signal d'horloge récupérée étant généré à partir du signal d'horloge à déphasage sélectionné.
PCT/US2006/030501 2005-08-08 2006-08-07 Systeme de recuperation d'horloge et de donnees WO2007019339A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/199,287 2005-08-08
US11/199,287 US7599457B2 (en) 2005-08-08 2005-08-08 Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits

Publications (2)

Publication Number Publication Date
WO2007019339A2 true WO2007019339A2 (fr) 2007-02-15
WO2007019339A3 WO2007019339A3 (fr) 2008-01-03

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PCT/US2006/030501 WO2007019339A2 (fr) 2005-08-08 2006-08-07 Systeme de recuperation d'horloge et de donnees

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US (1) US7599457B2 (fr)
WO (1) WO2007019339A2 (fr)

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US8014481B1 (en) * 2006-11-13 2011-09-06 Marvell International Ltd. Upstream data recovery and data rate detection
US9178713B1 (en) 2006-11-28 2015-11-03 Marvell International Ltd. Optical line termination in a passive optical network
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TWI637186B (zh) * 2017-03-28 2018-10-01 奇景光電股份有限公司 異常時脈偵測方法及其電路
CN108037332B (zh) * 2017-12-29 2023-11-07 陕西海泰电子有限责任公司 多通道参考时钟发生模块
JP2022132859A (ja) * 2021-03-01 2022-09-13 富士通株式会社 光伝送装置および光伝送システム
TWI775389B (zh) * 2021-04-15 2022-08-21 智原科技股份有限公司 時脈資料校正電路
CN114244362B (zh) * 2021-11-18 2025-08-29 重庆吉芯科技有限公司 一种基于时间交织adc的通道随机化电路及方法
CN114650052A (zh) * 2022-03-31 2022-06-21 北京神经元网络技术有限公司 一种时钟恢复电路及芯片

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Also Published As

Publication number Publication date
US7599457B2 (en) 2009-10-06
WO2007019339A3 (fr) 2008-01-03
US20070030936A1 (en) 2007-02-08

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