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WO2007030368A3 - Lattice-mismatched semiconductor structures on insulators and their fabrication methods - Google Patents

Lattice-mismatched semiconductor structures on insulators and their fabrication methods Download PDF

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Publication number
WO2007030368A3
WO2007030368A3 PCT/US2006/033859 US2006033859W WO2007030368A3 WO 2007030368 A3 WO2007030368 A3 WO 2007030368A3 US 2006033859 W US2006033859 W US 2006033859W WO 2007030368 A3 WO2007030368 A3 WO 2007030368A3
Authority
WO
WIPO (PCT)
Prior art keywords
lattice
insulators
mismatched semiconductor
semiconductor structures
fabrication methods
Prior art date
Application number
PCT/US2006/033859
Other languages
French (fr)
Other versions
WO2007030368A2 (en
Inventor
Matthew T Currie
Anthony J Lochtefeld
Zhiyuan Cheng
Thomas A Langdo
Original Assignee
Amberwave Systems Corp
Matthew T Currie
Anthony J Lochtefeld
Zhiyuan Cheng
Thomas A Langdo
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/220,482 external-priority patent/US7638842B2/en
Priority claimed from US11/221,064 external-priority patent/US20070054467A1/en
Application filed by Amberwave Systems Corp, Matthew T Currie, Anthony J Lochtefeld, Zhiyuan Cheng, Thomas A Langdo filed Critical Amberwave Systems Corp
Publication of WO2007030368A2 publication Critical patent/WO2007030368A2/en
Publication of WO2007030368A3 publication Critical patent/WO2007030368A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

Monolithic lattice-mismatched semiconductor heterostructures and methods for forming the same, such as by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly- defective interface areas along with the underlying substrates to produce alternative active- area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.
PCT/US2006/033859 2005-09-07 2006-08-30 Lattice-mismatched semiconductor structures on insulators and their fabrication methods WO2007030368A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/221,064 2005-09-07
US11/220,482 2005-09-07
US11/220,482 US7638842B2 (en) 2005-09-07 2005-09-07 Lattice-mismatched semiconductor structures on insulators
US11/221,064 US20070054467A1 (en) 2005-09-07 2005-09-07 Methods for integrating lattice-mismatched semiconductor structure on insulators

Publications (2)

Publication Number Publication Date
WO2007030368A2 WO2007030368A2 (en) 2007-03-15
WO2007030368A3 true WO2007030368A3 (en) 2007-11-15

Family

ID=37836348

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/033859 WO2007030368A2 (en) 2005-09-07 2006-08-30 Lattice-mismatched semiconductor structures on insulators and their fabrication methods

Country Status (1)

Country Link
WO (1) WO2007030368A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2929444B1 (en) 2008-03-31 2010-08-20 Commissariat Energie Atomique METHOD FOR MANUFACTURING A MICROELECTRONIC STRUCTURE OF THE SEMICONDUCTOR TYPE ON INSULATION AND WITH DIFFERENTIATED PATTERNS, AND STRUCTURE THUS OBTAINED
US7767546B1 (en) 2009-01-12 2010-08-03 International Business Machines Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer
US20100176482A1 (en) 2009-01-12 2010-07-15 International Business Machine Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation
EP2221853B1 (en) * 2009-02-19 2012-04-25 S.O.I. TEC Silicon Relaxation and transfer of strained material layers
US8587063B2 (en) * 2009-11-06 2013-11-19 International Business Machines Corporation Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels
US9177967B2 (en) * 2013-12-24 2015-11-03 Intel Corporation Heterogeneous semiconductor material integration techniques

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050181549A1 (en) * 2004-02-17 2005-08-18 Barr Alexander L. Semiconductor structure having strained semiconductor and method therefor
US20060160291A1 (en) * 2005-01-19 2006-07-20 Sharp Laboratories Of America, Inc. Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050181549A1 (en) * 2004-02-17 2005-08-18 Barr Alexander L. Semiconductor structure having strained semiconductor and method therefor
US20060160291A1 (en) * 2005-01-19 2006-07-20 Sharp Laboratories Of America, Inc. Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
LIJUAN HUANG ET AL: "Electron and Hole Mobility Enhancement in Strained SOI by Wafer Bonding", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE SERVICE CENTER, PISACATAWAY, NJ, US, vol. 49, no. 9, September 2002 (2002-09-01), pages 1566 - 1571, XP011072347, ISSN: 0018-9383 *
RIM K ET AL: "Fabrication and mobility characteristics of ultra-thin strained si directly on insulator (SSDOI) MOSFETs", INTERNATIONAL ELECTRON DEVICES MEETING 2003. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC 8 - 10, 2003, NEW YORK, NY : IEEE, US, 8 December 2003 (2003-12-08), pages 49 - 52, XP010683956, ISBN: 0-7803-7872-5 *
YANG M ET AL: "High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations", INTERNATIONAL ELECTRON DEVICES MEETING 2003. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC 8 - 10, 2003, NEW YORK, NY : IEEE, US, 8 December 2003 (2003-12-08), pages 453 - 456, XP010684050, ISBN: 0-7803-7872-5 *

Also Published As

Publication number Publication date
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