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WO2008038260A1 - Compteur en mémoire - Google Patents

Compteur en mémoire Download PDF

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Publication number
WO2008038260A1
WO2008038260A1 PCT/IL2006/001132 IL2006001132W WO2008038260A1 WO 2008038260 A1 WO2008038260 A1 WO 2008038260A1 IL 2006001132 W IL2006001132 W IL 2006001132W WO 2008038260 A1 WO2008038260 A1 WO 2008038260A1
Authority
WO
WIPO (PCT)
Prior art keywords
counter
counter value
module
decision
operative
Prior art date
Application number
PCT/IL2006/001132
Other languages
English (en)
Inventor
Zeev Geyzel
Leonid Dorrendorf
Original Assignee
Nds Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nds Limited filed Critical Nds Limited
Priority to PCT/IL2006/001132 priority Critical patent/WO2008038260A1/fr
Publication of WO2008038260A1 publication Critical patent/WO2008038260A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
    • H03K21/403—Arrangements for storing the counting state in case of power supply interruption
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Definitions

  • the present invention relates to a counter in memory, and in particular, but not exclusively to, a counter in non-volatile memory with limited write endurance.
  • memory with limited write endurance is typically quickly worn out when the values stored in the memory are updated frequently, often leading to system failure.
  • a common scenario where memory values are changed extensively is with counters, where the counters are incremented or decremented on the occurrence of selected events.
  • the exact value of the counter is not essential, only the order of magnitude of the counter value is important.
  • a standard solution for implementing a counter in a memory with limited write endurance is to update the counter in random access memory (RAM) and every N counts to update the counter in the NVM based on the value in the RAM.
  • RAM random access memory
  • NVM non-volatile memory
  • the present invention seeks to provide an improved counter system.
  • the system of the present invention in preferred embodiments thereof, includes a counter system having a counter value stored in a memory, wherein a decision to update the counter value (increment or decrement) in response to receipt of a countable input is based on a randomly generated value.
  • the counter value is updated in a probabilistic manner in that sometimes the counter value is updated in response to receipt of the countable input and sometimes the counter value is not updated in response to the receipt of the countable input.
  • the decision to update the counter value is based on a probability which is inversely proportional to the counter value.
  • the internal state of the counter is generally not equal to the number of countable inputs received by the counter system as the counter value is updated in a probabilistic manner. Therefore, the exact number of the counter inputs received by the counter system cannot generally be determined from the counter value. Instead, an expected value of the number of counter inputs received by the counter system is preferably determined from the counter value based on probability.
  • the counter system generally reduces memory wear.
  • a counter system for limited write endurance memory including a receive module to receive a plurality of countable inputs, a non- volatile memory including a counter having a counter value, a decision module operationally connected to the receive module, the decision module being operative to render a decision, at least partially based on a randomly generated value, whether to update the counter value after receipt of one of the countable inputs, and an update module operationally connected to the decision module and the memory, the update module being operative to update the counter value of the counter in accordance with the decision rendered by the decision module.
  • the system includes a retrieval module operationally connected to the memory, the retrieval module being operative to determine an expected value of the countable inputs received by the receive module from the counter value.
  • the system includes a random number generator operationally connected to the decision module, the random number generator being operative to generate the randomly generated value, the decision module being operative to render the decision by comparing the randomly generated value with the output of a non-increasing function, the retrieval module being operative to determine the expected value based on a retrieval function such that performing integration on a reciprocal of the non-increasing function determines the retrieval function.
  • the non-increasing function is positive.
  • the non-increasing function equals a constant.
  • the non-increasing function is inversely proportional to the counter value.
  • the non-increasing function is a reciprocal of the counter value.
  • the retrieval function is equal to the counter value squared divided by two.
  • the update module is operative to increment the counter value in accordance with the decision. Further, in accordance with a preferred embodiment of the present invention the update module is operative to increment the counter value by one unit in accordance with the decision.
  • the update module is operative to decrement the counter value in accordance with the decision.
  • the update module is operative to decrement the counter value by one unit in accordance with the decision.
  • the decision module is operative such that a probability of deciding to update the counter value after receipt of one of the countable inputs is inversely proportional to the counter value.
  • the decision module is operative such that the probability of deciding to update the counter value after receipt of one of the countable inputs is a reciprocal of the counter value.
  • the decision module is operative such that the probability of deciding to update the counter value after receipt of one of the countable inputs is fixed.
  • the system includes a random number generator operationally connected to the decision module, the random number generator being operative to generate the randomly generated value, the decision module being operative to render the decision by comparing the randomly generated value with the output of a non-increasing function.
  • the non-increasing function converges to zero. Further, in accordance with a preferred embodiment of the present invention the non-increasing function equals a constant.
  • the non-increasing function is inversely proportional to the counter value.
  • the non-increasing function is a reciprocal of the counter value.
  • the receive module is operationally connected to a television system for displaying a plurality of channels, the receive module being operative to receive the countable inputs from the television system while the television system displays one of the channels, so that the counter value is representative of the amount of time that the one channel is displayed by the television system.
  • the receive module is operationally connected to a network router which routes a plurality of packets, the receive module being operative to receive one of the countable inputs for each of the packets routed by the network router so that the counter value is representative of the number of packets routed by the router.
  • the countable inputs correspond to a plurality of violations
  • the counter being a violation counter for counting a value representative of the violations
  • the system further including a violation monitor to at least one of report violation and prevent an action when the counter value exceeds a predetermined value.
  • the violation monitor is operative to prevent access to a server when the counter value exceeds a predetermined value.
  • the memory is divided into a plurality of writable sections including a first section and a second section, the counter being in the first section, the countable inputs corresponding to write operations in the second section such that the counter value is representative of the write operations in the second section.
  • a method for counting a plurality of countable inputs in a non-volatile memory with limited write endurance including receiving the countable inputs, rendering a decision, at least partially based on a randomly generated value, whether to update a counter value after receipt of one of the countable inputs, and updating the counter value in accordance with the decision.
  • Fig. 1 is a partly pictorial, partly block diagram view of a counter system constructed and operative in accordance with a preferred embodiment of the present invention
  • Fig. 2 is a partly pictorial, partly block diagram view of a preferred embodiment of a viewer rating system using the counter system of Fig. 1;
  • Fig. 3 is a block diagram view of a preferred embodiment of a network diagnostic system using the counter system of Fig. 1;
  • Fig. 4 is a block diagram view of a preferred embodiment of a violation monitoring system using the counter system of Fig. 1 ;
  • Fig. 5 is a partly pictorial, partly block diagram view of a preferred embodiment of an Internet server violation monitoring system using the counter system of Fig. 1 ;
  • Fig. 6 is a partly pictorial, partly block diagram view of a preferred embodiment of a smart card having a memory arrangement using the counter system of Fig. 1.
  • Fig. 1 is a partly pictorial, partly block diagram view of a counter system 10 constructed and operative in accordance with a preferred embodiment of the present invention.
  • the counter system 10 preferably includes a receive module 12, a non- volatile memory 14 with limited write endurance, a random number generator 16, a decision module 18, an update module 20 and a retrieval module 22.
  • the receive module 12 is preferably operative to receive a plurality of countable inputs 24.
  • the memory 14 typically includes a counter 26 having a counter value 28.
  • the initial value of the counter value 28 is typically set to one, when the counter 26 is used in incrementing mode.
  • the random number generator 16 is preferably operative to generate a randomly generated value, r (block 30).
  • the value of r is preferably between zero and one, based on a uniform distribution.
  • the random number generator 16 is preferably a true random number generator. It will be appreciated by those ordinarily skilled in the art that any other suitable random number generator may be used, for example, but not limited to, a pseudorandom number generator such as selecting a value from a statistically well distributed string of numbers.
  • the decision module 18 is typically operationally connected to the receive module 12.
  • the decision module 18 is preferably operative to render a decision whether to update the counter value 28 after receipt of one of the countable inputs 24.
  • the decision is typically based on the randomly generated value, r (block 30), by comparing the randomly generated value, r (block 30) with the output of a non-increasing function, F(n) (block 32) where n is the counter value 28.
  • the non-increasing function F(n) (block 32) is typically a positive non-increasing function.
  • the non-increasing function F(n) (block 32) is inversely proportional to the counter value 28 so that the decision module 18 is operative such that a probability of deciding to update the counter value 28 after receipt of one of the countable inputs 24 is inversely proportional to the counter value 28.
  • the non-increasing function F(n) (block 32) is a reciprocal of the counter value 28 so that the decision module 18 is operative such that a probability of deciding to update the counter value 28 after receipt of one of the countable inputs 24 is a reciprocal of the counter value 28.
  • n the randomly generated value, r (block 30) is compared to the value 1/n. If r is less than 1/n, then a decision is rendered to update the counter value 28. If r is not less than 1/n, then a decision is rendered not to update the counter value 28.
  • the non-increasing function F(n) (block 32) equals a constant so that the decision module 18 is operative such that a probability of deciding to update the counter value 28 after receipt of one of the countable inputs 24 is fixed.
  • the randomly generated value, r (block 30) is compared to the value c. If r is less than c, then a decision is rendered to update the counter value 28. If r is not less than c, then a decision is rendered not to update the counter value 28. Therefore, the counter value 28 is updated in a probabilistic manner.
  • the update module 20 is typically operationally connected to the decision module 18 and the memory 14.
  • the update module 20 is preferably operative to update the counter value 28 of the counter 26 in accordance with the decision rendered by the decision module 18.
  • the counter value 28 is typically updated by incrementing the counter value 28 by one unit. It will be appreciated by those ordinarily skilled in the art that if the counter system 10 is operating in decrementing mode then the counter value 28 is typically updated by decrementing the counter value 28, for example, but not limited to, by one unit.
  • the random number generator 16 and the decision module 18 operate in substantially the same manner as in incrementing mode, for example, but not limited to, using the same F(n) and limits of r.
  • the initial value of the counter is typically set at a suitably large enough value.
  • the counter value 28 is generally not equal to the number of countable inputs 24 received by the receive module 12 as the counter value 28 is updated in a probabilistic manner. Therefore, the exact number of the counter inputs 24 received by the counter system cannot generally be determined from the counter value 28. Instead, an expected value 34 of the number of counter inputs 24 received by the receive module 12 is preferably determined by the retrieval module 22 from the counter value 28 based on probability, generally using a retrieval function, described in more detail below.
  • F(n) — . Therefore, if the initial value of the counter value 28 is 1 and n the present value of the counter value 28 is n and the counter value 28 is incremented by 1 unit for each increment, then in general, to increase the counter value 28 from n to n+1, on average n countable inputs 24 need to be received by the receive module 12. Therefore, when the counter value 28 has a value of n, the number of the countable inputs 24 received by the receive module 12 is probably between (n-1 + n-2 + .... l) and (n + n-l + n-2 + .... 1).
  • the expected value 34 on average is equal to the average of equations 3 and 4, giving the retrieval function as follows:
  • the nonvolatile memory 26 requires, at most, n write operations to the memory 14. Therefore, if the nonvolatile memory 26 has a lifespan of m write operations, then a one-for-one counting system (where one countable input leads to writing of one count) provides a counter with a lifetime of m counts. However, using the method of the counter system 10, the non- volatile memory 26 is generally usable to count to m 2 approximately ⁇ countable inputs 24. The extended lifespan of the counter
  • the decision module 18 renders X decision operations corresponding to the receipt of X countable inputs 24 and the counter value 28 is equal to n
  • the expected value 34 determined by the retrieval n rv module 22 is n with a variance of approximately ⁇ , and a standard deviation
  • the distribution is close to normal, and therefore, the 3 ⁇ criterion may be used to determine with a probability of 99.7% that the retrieved value has a deviation of no more than 3 ⁇ which equals
  • the receive module 12 receives 5000 countable inputs 24, the counter value 28 will have a value approximately equal to 100, the expected value 34 will have a value approximately equal to 5000 with a relative error of no more than 34% with 99.7% accuracy.
  • the receive module 12 receives 500,000 countable inputs 24, the counter value 28 will have a value approximately equal to 1000, the expected value 34 will have a value approximately equal to 500,000 with a relative error of no more than 11% with 99.7% accuracy.
  • the retrieval function is preferably determined by performing integration on a reciprocal of the non-increasing function, as follows:
  • Fig. 2 is a partly pictorial, partly block diagram view of a preferred embodiment of a viewer rating system 36 using the counter system 10 of Fig. 1.
  • the viewer rating system 36 is typically operationally connected to, or implemented with, a television system including a set-top box 38 and a television 42.
  • the set-top box 38 is generally operative to receive and decode a plurality of TV channels 46 for display on the television 42 to a viewer 40.
  • the viewer rating system 36 preferably includes a plurality of counters 44. Each counter 44 is typically associated with a different one of the TV channels 46. Each counter 44 is preferably incremented periodically while the channel 46, associated with the counter 44, is being decoded by the set-top box 38. Therefore, the count on each counter 44 represents the amount of time a particular TV channel 46 is being decoded by the set-top box 38.
  • Each of the counters 44 is typically implemented using the elements of the counter system 10 of Fig. 1.
  • Each counter 44 typically includes the receive module 12, the random number generator 16, the decision module 18, the update module 20 and the storage arrangement 14 (Fig. 1). It will be appreciated by those ordinarily skilled in the art that some of the elements of the counter system 10 may be shared among the counters 44, for example, but not limited to, the random number generator 16 and the storage arrangement 14.
  • the set-top box 38 preferably determines the TV channel 46 being decoded by the set-top box 38 using techniques known to those ordinarily skilled in the art.
  • the set-top box 38 preferably prepares the countable inputs 24 (Fig. 1) for counting by the counters 44 according to the channel 46 being decoded by the set-top box 38.
  • the countable inputs 24 are prepared on a periodic basis such that the number of countable inputs 24 represents the time that the set-top box 38 spends decoding particular channels 46.
  • each counter 44 is: operationally connected to the set-top box 38; and is operative to receive the channel appropriate countable inputs 24 from the set-top box 38 while the set-top box 38 is decoding the appropriate channel 46 for display by the television 42. Therefore, the counter value of each counter 44 is representative of the amount of time that an appropriate channel 46 is being decoded by the set-top box 38 for display by the television 42. Therefore, each counter 44 is incremented periodically while the channel 46 associated with the counter 44 is being decoded by the set-top box 38, based on the channel appropriate countable inputs 24.
  • Fig. 3 is a block diagram view of a preferred embodiment of a network diagnostic system 48 using the counter system 10 of Fig. 1.
  • the network diagnostic system 48 is preferably operative to diagnose network traffic, for example, but not limited to, identify bottlenecks in the network and see which kind of traffic uses different parts of the system.
  • the network diagnostic system 48 typically includes a network diagnostic module 58 and a plurality of packet counters 50 (only one shown in Fig. 3 for the sake of clarity). At least one of the packet counters 50 is typically disposed in each of a plurality of network routers 52 (only one shown for the sake of clarity).
  • the network routers 52 generally route a plurality of packets 56.
  • Each packet counter 50 is typically implemented in a non- volatile RAM 54 of each network router 52.
  • Each packet counter 50 is substantially the same as the counter system 10 (Fig. 1).
  • the receive module 12 (Fig. 1) of the packet counter 50 is typically operationally connected to the network router 52.
  • the receive module 12 is preferably operative to receive one countable input 24 (Fig. 1) for each packet 56 routed by the network router 52 so that the counter value 28 of the packet counter 50 is representative of the number of packets 56 routed by the network router 52.
  • the network router(s) 52 optionally include more than one packet counter 50, so that each packet counter 50 count a different type of packet 56.
  • the network diagnostic module 58 is typically operative to analyze network traffic based on the counter values 28 (Fig. 1) of the packet counters 50.
  • Fig. 4 is a block diagram view of a preferred embodiment of a violation monitoring system 60 using the counter system 10 of Fig. 1.
  • the violation monitoring system 60 typically includes a violation counter 62 and a violation monitor 64.
  • the violation counter 62 is preferably operative to count a value representative of a number of violations.
  • the violation counter 62 is substantially the same as the counter system 10 (Fig. 1), wherein the countable inputs 24 (Fig. 1) correspond to a plurality of violations (not shown).
  • the violation monitor 64 is preferably operative to monitor the counter value 28 of the violation counter 62 in order to prevent an action based on the violations and/or to report the violations.
  • violations are software failure, unexpected or malicious program flow, suspicious user behavior, deviation from accepted protocol, badly signed communication packets, password errors (for example, but not limited to, PIN codes at an ATM), and antivirus findings.
  • Fig. 5 is a partly pictorial, partly block diagram view of a preferred embodiment of an Internet server violation monitoring system 66 using the counter system 10 of Fig. 1.
  • the Internet server violation monitoring system 66 typically includes a violation monitor 68 and a violation counter 70.
  • the violation counter 70 is preferably operative to count violations by the public 72 accessing an Internet server 74 via the Internet 76.
  • the violations typically include hacking or illegal intrusion attempts on the Internet server 74.
  • the violation counter 70 is substantially the same as the counter system 10 of Fig. 1.
  • the violation monitor 68 is preferably operative to prevent access to the Internet server 74 when the counter value 28 (Fig. 1) of the violation counter 70 exceeds a predetermined value.
  • Fig. 6 is a partly pictorial, partly block diagram view of a preferred embodiment of a smart card 78 having a memory arrangement 80 using the counter system 10 of Fig. 1.
  • the memory arrangement 80 is typically limited write endurance non-volatile memory.
  • the memory arrangement 80 is divided into six writable sections or pages 82, 84, 86, 88, 90, 92, by way of example only.
  • the page 92 includes five counters 94, 96, 98, 100, 102, by way of example only.
  • 96, 98, 100, 102 is preferably operative to count write operations to the different pages 82, 84, 86, 88, 90, respectively.
  • Each counter 94, 96, 98, 100, 102 is substantially the same as the counter system 10 of Fig. 1, wherein the countable inputs 24 (Fig. 1) preferably correspond to the write operations in the pages 82, 84, 86, 88, 90 so that the counter values of counters 94, 96, 98, 100, 102 are representative of the number of write operations in the pages 82, 84, 86, 88, 90, respectively.
  • the counters 94, 96, 98, 100, 102 are typically used to monitor write endurance of the pages 82, 84, 86, 88, 90.
  • a one-to-one counter system wherein one countable input leads to incrementing the counter by one unit, may fail before the failure of the pages 82, 84, 86, 88, 90. Therefore, the counters 94, 96, 98, 100, 102 based on the counter system 10 (Fig. 1) are particularly suitable for the counting application described with reference to Fig. 6.
  • software components of the present invention may, if desired, be implemented in ROM (read only memory) form.
  • the software components may, generally, be implemented in hardware, if desired, using conventional techniques.

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Abstract

La présente invention concerne un système de compteur pour mémoire à résistance limitée à l'écriture incluant un module de réception (12) servant à recevoir une pluralité d'entrées dénombrables (24), une mémoire non volatile incluant un compteur comportant une valeur de compteur (28), un module de décision (18) fonctionnellement raccordé au module de réception, le module de décision servant à rendre une décision reposant au moins en partie sur une valeur produite au hasard (30) et portant sur l'éventualité de la mise à jour de la valeur de compteur après réception de l'une des entrées dénombrables, et un module de mise à jour (20) fonctionnellement raccordé au module de décision et à la mémoire, le module de mise à jour servant à mettre à jour la valeur de compteur du compteur en tenant compte de la décision rendue par le module de décision. L'invention concerne également l'appareil et les procédés correspondants.
PCT/IL2006/001132 2006-09-27 2006-09-27 Compteur en mémoire WO2008038260A1 (fr)

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PCT/IL2006/001132 WO2008038260A1 (fr) 2006-09-27 2006-09-27 Compteur en mémoire

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Application Number Priority Date Filing Date Title
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WO2008038260A1 true WO2008038260A1 (fr) 2008-04-03

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Cited By (1)

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US20070245068A1 (en) * 2006-04-13 2007-10-18 Emilio Yero Cycle count storage methods

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US6345001B1 (en) * 2000-09-14 2002-02-05 Sandisk Corporation Compressed event counting technique and application to a flash memory system
US6643187B2 (en) * 2000-09-14 2003-11-04 Sandisk Corporation Compressed event counting technique and application to a flash memory system
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