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WO2008146760A1 - 記憶素子及びその読み出し方法 - Google Patents

記憶素子及びその読み出し方法 Download PDF

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Publication number
WO2008146760A1
WO2008146760A1 PCT/JP2008/059592 JP2008059592W WO2008146760A1 WO 2008146760 A1 WO2008146760 A1 WO 2008146760A1 JP 2008059592 W JP2008059592 W JP 2008059592W WO 2008146760 A1 WO2008146760 A1 WO 2008146760A1
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WO
WIPO (PCT)
Prior art keywords
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section
memory means
memory device
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Application number
PCT/JP2008/059592
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English (en)
French (fr)
Inventor
Yutaka Hayashi
Kazuhiko Matsumoto
Takashi Uemura
Original Assignee
National Institute Of Advanced Industrial Science And Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute Of Advanced Industrial Science And Technology filed Critical National Institute Of Advanced Industrial Science And Technology
Priority to EP08764638.6A priority Critical patent/EP2166571B1/en
Priority to US12/601,788 priority patent/US8223548B2/en
Priority to JP2009516309A priority patent/JP5196500B2/ja
Priority to CN2008800217764A priority patent/CN101689547B/zh
Publication of WO2008146760A1 publication Critical patent/WO2008146760A1/ja

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/699—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having the gate at least partly formed in a trench
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0415—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having ferroelectric gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
    • H10D62/882—Graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/033—Manufacture or treatment of data-storage electrodes comprising ferroelectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

　記憶素子（１）は、長さと第１表面と第１表面に囲まれた断面とを有する第１の半導体領域（１００）と、第１表面上に設けられた記憶手段（３００）と、記憶手段（３００）上に設けられたゲート（４００）と、から少なくとも構成され、第１の半導体領域（１００）の断面の等価断面半径を、記憶手段（３００）の等価酸化シリコン膜厚以下とすることにより低プログラム電圧を実現する。断面の等価断面半径ｒを１０ｎｍ以下、ゲート長を２０ｎｍ以下とすることにより、ゲート電圧換算の多値レベル間隔を室温で認識できる固有値とする。
PCT/JP2008/059592 2007-05-24 2008-05-23 記憶素子及びその読み出し方法 WO2008146760A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP08764638.6A EP2166571B1 (en) 2007-05-24 2008-05-23 Memory device and its reading method
US12/601,788 US8223548B2 (en) 2007-05-24 2008-05-23 Memory device with reduced programming voltage method of reduction of programming voltage and method of reading such memory device
JP2009516309A JP5196500B2 (ja) 2007-05-24 2008-05-23 記憶素子及びその読み出し方法
CN2008800217764A CN101689547B (zh) 2007-05-24 2008-05-23 存储元件及其读取方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007138470 2007-05-24
JP2007-138470 2007-05-24

Publications (1)

Publication Number Publication Date
WO2008146760A1 true WO2008146760A1 (ja) 2008-12-04

Family

ID=40075006

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/059592 WO2008146760A1 (ja) 2007-05-24 2008-05-23 記憶素子及びその読み出し方法

Country Status (6)

Country Link
US (1) US8223548B2 (ja)
EP (1) EP2166571B1 (ja)
JP (1) JP5196500B2 (ja)
KR (1) KR101342476B1 (ja)
CN (1) CN101689547B (ja)
WO (1) WO2008146760A1 (ja)

Families Citing this family (8)

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Publication number Priority date Publication date Assignee Title
JP6547702B2 (ja) * 2016-07-26 2019-07-24 信越半導体株式会社 半導体装置の製造方法及び半導体装置の評価方法
US10276697B1 (en) * 2017-10-27 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance FET with improved reliability performance
US11678486B2 (en) 2019-06-03 2023-06-13 Macronix Iniernational Co., Ltd. 3D flash memory with annular channel structure and array layout thereof
US11088246B2 (en) 2019-07-18 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a field effect transistor using carbon nanotubes and a field effect transistor
US11165032B2 (en) * 2019-09-05 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistor using carbon nanotubes
US11133329B2 (en) * 2019-09-09 2021-09-28 Macronix International Co., Ltd. 3D and flash memory architecture with FeFET
WO2021184310A1 (zh) * 2020-03-19 2021-09-23 厦门三安光电有限公司 发光二极管
KR20210030306A (ko) 2021-02-25 2021-03-17 삼성전자주식회사 반도체 메모리 장치

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JPH1093083A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体装置の製造方法
JP2000156423A (ja) * 1998-11-18 2000-06-06 Internatl Business Mach Corp <Ibm> 電界効果トランジスタを含む超小型電子素子
JP2000207881A (ja) * 1999-01-07 2000-07-28 Nec Corp 単一電子メモリ素子の駆動回路及びその駆動方法
JP2004172616A (ja) * 2002-11-15 2004-06-17 Samsung Electronics Co Ltd 垂直ナノチューブを利用した不揮発性メモリ素子
JP2006229233A (ja) * 2005-02-16 2006-08-31 Samsung Electronics Co Ltd 複数のトラップ膜を備える不揮発性メモリ素子
WO2006132158A1 (ja) * 2005-06-10 2006-12-14 Sharp Kabushiki Kaisha 不揮発性半導体記憶装置およびその製造方法

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* Cited by examiner, † Cited by third party
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JPH1093083A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 半導体装置の製造方法
JP2000156423A (ja) * 1998-11-18 2000-06-06 Internatl Business Mach Corp <Ibm> 電界効果トランジスタを含む超小型電子素子
JP2000207881A (ja) * 1999-01-07 2000-07-28 Nec Corp 単一電子メモリ素子の駆動回路及びその駆動方法
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See also references of EP2166571A4 *

Also Published As

Publication number Publication date
EP2166571A1 (en) 2010-03-24
EP2166571B1 (en) 2017-08-30
US20100208522A1 (en) 2010-08-19
CN101689547A (zh) 2010-03-31
KR101342476B1 (ko) 2013-12-17
JPWO2008146760A1 (ja) 2010-08-19
EP2166571A4 (en) 2010-09-29
KR20100018557A (ko) 2010-02-17
US8223548B2 (en) 2012-07-17
CN101689547B (zh) 2012-06-27
JP5196500B2 (ja) 2013-05-15

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