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WO2008105535A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2008105535A1
WO2008105535A1 PCT/JP2008/053651 JP2008053651W WO2008105535A1 WO 2008105535 A1 WO2008105535 A1 WO 2008105535A1 JP 2008053651 W JP2008053651 W JP 2008053651W WO 2008105535 A1 WO2008105535 A1 WO 2008105535A1
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WO
WIPO (PCT)
Prior art keywords
substrate
semiconductor chip
manufacturing
same
semiconductor device
Prior art date
Application number
PCT/JP2008/053651
Other languages
English (en)
French (fr)
Inventor
Akinobu Shibuya
Koichi Takemura
Akira Ouchi
Tomoo Murakami
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009501322A priority Critical patent/JPWO2008105535A1/ja
Priority to US12/526,236 priority patent/US8237292B2/en
Publication of WO2008105535A1 publication Critical patent/WO2008105535A1/ja
Priority to US13/549,001 priority patent/US8669138B2/en

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Abstract

　基板（１）と半導体チップ（５）はフリップチップ接続される。基板（１）の接続パッド（３）と半導体チップ（５）の入出力端子（１０）の周囲に、最大粒径が５μｍ以下で含有量が４０乃至６０質量％のフィラーと樹脂との複合体であるアンダーフィル材（７）が充填される。また、アンダーフィル材（７）で覆われていない基板（１）の一主面及び半導体チップ（５）の側面は、含有量が７５質量％以上のフィラーとガラス転移温度が１８０°C以上の樹脂との複合体であるモールド材（８）により封止される。モールド材（８）で覆われた基板（１）と半導体チップ（５）は、一体として上下から薄化される。
PCT/JP2008/053651 2007-03-01 2008-02-29 半導体装置及びその製造方法 WO2008105535A1 (ja)

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US8237292B2 (en) 2012-08-07
US20130005085A1 (en) 2013-01-03

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