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WO2008117361A1 - 論理シミュレーション方法及び論理シミュレータ - Google Patents

論理シミュレーション方法及び論理シミュレータ Download PDF

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Publication number
WO2008117361A1
WO2008117361A1 PCT/JP2007/055961 JP2007055961W WO2008117361A1 WO 2008117361 A1 WO2008117361 A1 WO 2008117361A1 JP 2007055961 W JP2007055961 W JP 2007055961W WO 2008117361 A1 WO2008117361 A1 WO 2008117361A1
Authority
WO
WIPO (PCT)
Prior art keywords
logic
logic simulation
physical
simulation method
physical specification
Prior art date
Application number
PCT/JP2007/055961
Other languages
English (en)
French (fr)
Inventor
Kenichi Nomura
Hideaki Anbutsu
Cheng Giam Tan
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to JP2009506074A priority Critical patent/JP4573909B2/ja
Priority to PCT/JP2007/055961 priority patent/WO2008117361A1/ja
Publication of WO2008117361A1 publication Critical patent/WO2008117361A1/ja
Priority to US12/585,081 priority patent/US8825463B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

　アナログ回路の物理動作と論理シミュレーション時の論理動作の差異による検証ミスを防止可能な論理シミュレーション方法を提供する。 　物理仕様検出部（２）によって、論理ライブラリ（６）に記述された検証対象のアナログ回路（ＰＬＬ回路やＤＬＬ回路）の物理仕様を検出し、監視部（３）によって、論理シミュレーション時の信号または設定が物理仕様を満たすか否かを監視し、物理仕様を満たさない場合は警告出力部（４）により警告を発するようにする。
PCT/JP2007/055961 2007-03-23 2007-03-23 論理シミュレーション方法及び論理シミュレータ WO2008117361A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009506074A JP4573909B2 (ja) 2007-03-23 2007-03-23 論理シミュレーション方法及び論理シミュレーション装置
PCT/JP2007/055961 WO2008117361A1 (ja) 2007-03-23 2007-03-23 論理シミュレーション方法及び論理シミュレータ
US12/585,081 US8825463B2 (en) 2007-03-23 2009-09-02 Logic simulation method and logic simulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/055961 WO2008117361A1 (ja) 2007-03-23 2007-03-23 論理シミュレーション方法及び論理シミュレータ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/585,081 Continuation US8825463B2 (en) 2007-03-23 2009-09-02 Logic simulation method and logic simulator

Publications (1)

Publication Number Publication Date
WO2008117361A1 true WO2008117361A1 (ja) 2008-10-02

Family

ID=39788106

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/055961 WO2008117361A1 (ja) 2007-03-23 2007-03-23 論理シミュレーション方法及び論理シミュレータ

Country Status (3)

Country Link
US (1) US8825463B2 (ja)
JP (1) JP4573909B2 (ja)
WO (1) WO2008117361A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016139186A (ja) * 2015-01-26 2016-08-04 株式会社ソシオネクスト 論理シミュレーション方法、論理シミュレーション装置及びプログラム

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8369165B2 (en) * 2011-02-17 2013-02-05 Nanya Technology Corporation Synchronous signal generating circuit
US11321225B2 (en) 2020-05-22 2022-05-03 International Business Machines Corporation Reducing the memory load time for logic simulator by leveraging architecture simulator

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0926985A (ja) * 1995-07-11 1997-01-28 Fujitsu Ltd シミュレーション装置及びシミュレーション方法
JP2000357179A (ja) * 1999-06-14 2000-12-26 Nec Ic Microcomput Syst Ltd Ｐｌｌブロックのジッタを考慮したタイミング検証を行う論理シミュレーション方法及びその論理シミュレータ
JP2006262489A (ja) * 2005-03-18 2006-09-28 Avago Technologies General Ip (Singapore) Private Ltd 二重同調要素を有する線形位相ロックループ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0926985A (ja) * 1995-07-11 1997-01-28 Fujitsu Ltd シミュレーション装置及びシミュレーション方法
JP2000357179A (ja) * 1999-06-14 2000-12-26 Nec Ic Microcomput Syst Ltd Ｐｌｌブロックのジッタを考慮したタイミング検証を行う論理シミュレーション方法及びその論理シミュレータ
JP2006262489A (ja) * 2005-03-18 2006-09-28 Avago Technologies General Ip (Singapore) Private Ltd 二重同調要素を有する線形位相ロックループ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016139186A (ja) * 2015-01-26 2016-08-04 株式会社ソシオネクスト 論理シミュレーション方法、論理シミュレーション装置及びプログラム
US10262089B2 (en) 2015-01-26 2019-04-16 Socionext Inc. Logic simulation method, logic simulation apparatus and computer-readable storage medium storing logic simulation program

Also Published As

Publication number Publication date
US20090326902A1 (en) 2009-12-31
JP4573909B2 (ja) 2010-11-04
US8825463B2 (en) 2014-09-02
JPWO2008117361A1 (ja) 2010-07-08

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