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WO2008137573A1 - Structure de couche de dispositif de diode électroluminescente utilisant une couche de contact de nitrure d'indium gallium - Google Patents

Structure de couche de dispositif de diode électroluminescente utilisant une couche de contact de nitrure d'indium gallium Download PDF

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Publication number
WO2008137573A1
WO2008137573A1 PCT/US2008/062261 US2008062261W WO2008137573A1 WO 2008137573 A1 WO2008137573 A1 WO 2008137573A1 US 2008062261 W US2008062261 W US 2008062261W WO 2008137573 A1 WO2008137573 A1 WO 2008137573A1
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WO
WIPO (PCT)
Prior art keywords
layer
contact
nitride
strained
nitride layer
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Application number
PCT/US2008/062261
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English (en)
Inventor
Michael Iza
Hirokuni Asamizu
Christian G. Van De Walle
Steven P. Denbaars
Shuji Nakamura
Original Assignee
The Regents Of The University Of California
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by The Regents Of The University Of California filed Critical The Regents Of The University Of California
Priority to JP2010506644A priority Critical patent/JP2010526444A/ja
Publication of WO2008137573A1 publication Critical patent/WO2008137573A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/8215—Bodies characterised by crystalline imperfections, e.g. dislocations; characterised by the distribution of dopants, e.g. delta-doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material

Definitions

  • the present invention relates to an improved light emitting diode (LED) device layer structure including a p-type contact layer that contains at least some indium (In), wherein the p-type contact layer is a not-intentionally doped strained nitride contact layer.
  • LED light emitting diode
  • GaN gallium nitride
  • AlGaN, InGaN, AlInGaN aluminum and indium
  • MBE molecular beam epitaxy
  • MOCVD metalorganic chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • GaN and its alloys are most stable in the hexagonal wurtzite crystal structure, in which the structure is described by two (or three) equivalent basal plane axes that are rotated 120° with respect to each other (the a-axes), all of which are perpendicular to a unique c-axis.
  • Group III and nitrogen atoms occupy alternating c-planes along the crystal's c-axis.
  • the symmetry elements included in the wurtzite structure dictate that III -nitrides possess a bulk spontaneous polarization along this c-axis, and the wurtzite structure exhibits piezoelectric polarization.
  • the wurtzite lattice can be characterized by three parameters: the edge length of the basal hexagon (a), the height of the hexagon lattice cell (c), and the cation- anion bond length ratio (u) along the [0001] axis in units of c.
  • the c/a ratio for the wurtzite crystal is 1.633 with a u value of 0.375.
  • the c/a ratio for AlN, GaN, and InN will differ.
  • GaN is the closest to the ideal crystal, followed by InN and AlN.
  • the degree of non-ideality of the crystal lattice also affects the magnitude and direction of the polarization.
  • the main contribution to the strength of polarization is attributed to the covalent bond parallel to the [0001] direction, the other three bonds are also equally ionic. These three bonds serve to counteract the polarization contributed by the other bond because they are pointed at angles opposite to the bond parallel to the c-axis.
  • the effect of the three angled bonds will decrease and the total polarization will increase, and vice versa.
  • This total macroscopic polarization is thus referred to as spontaneous polarization (P sp ) since it occurs in the equilibrium lattice at zero strain [Refs. 1-3].
  • Figures Ia- Id illustrate these effects for Ill-nitrides 100a, 100b, 100c, lOOd grown pseudomorphically on both Ga- face and N-face GaN 102a, 102b, 102c, 102d, and show P sp and P pe directions in Ga- face Al x Gai_ x N 100a grown on Ga- face GaN 102a ( Figure Ia), N-face Al x Gai_ x N 100b grown on N-face GaN 102b ( Figure Ib), Ga- face In x Gai_ x N 100c grown on Ga- face GaN 102c ( Figure Ic), and N-face In x Gai_ X N lOOd grown on N-face GaN 102d.
  • the AlGaN 100a is under tensile strain 104
  • the AlGaN 100b is under tensile strain 106
  • the InGaN 100c is under compressive strain 108
  • the InGaN lOOd is under compressive strain 110.
  • the AlGaN 100a is grown in the ⁇ 0001> direction 112 on GaN 102a so that the last grown surface of the AlGaN 100a is Ga- face 114 ( Figure Ia), and the InGaN 100c is grown in the ⁇ 0001> direction 116 on GaN 102c so that the last grown surface of the InGaN 100c is a Ga-face 118.
  • the AlGaN 100b is grown in the ⁇ 000-l> direction 120 on GaN 102b so that the last grown surface of the AlGaN 100b is N- face 122, and the InGaN lOOd is grown in the ⁇ 000-l> direction 124 on GaN 102d, so that the last grown surface of the InGaN lOOd is an N-face 126.
  • the external quantum efficiency or total efficiency ( ⁇ ) of LEDs can be defined by the following equation:
  • the extraction efficiency, ⁇ ext is defined as the amount of photons extracted
  • the injection efficiency, ⁇ mj is defined as the amount of carriers injected into the active region of the device
  • the internal quantum efficiency, ⁇ mt is defined as the amount of photons generated in the active region of the device.
  • the internal quantum efficiency of a device can be maximized by reducing the number of non-radiative centers, such as defects and impurities.
  • the internal quantum and injection efficiencies of blue nitride based LEDs have already been improved to a high level by optimizing the deposition conditions of the device layers. Therefore, further improvement in external efficiency of a device would require improvement in the extraction efficiency and injection efficiency.
  • nitride based devices The injection efficiency of nitride based devices is hampered by the difficulty in obtaining an ohmic p-type contact with a low voltage drop across the metal- semiconductor interface.
  • I/ Au Nickel/Gold
  • TCO transparent conducting oxide
  • ITO Indium Tin Oxide
  • Another approach to improve the voltage drop across the metal/semiconductor interface is the use of a strained nitride contact layer grown on top of the nitride semiconductor device [Refs. 5-8].
  • a strained nitride contact layer pseudomorphically grown atop the nitride device results in the tilting of the electric field in such a way that the tunneling of charge carriers through the barrier can be drastically enhanced [Ref. 8].
  • P-type doped strained contact layers have previously been demonstrated and have been shown to improve the performance of nitride devices [Refs. 8, 9].
  • p-type doping of nitride layers has been shown to drastically decrease the material quality by inducing crystal defects and gross morphological degradation of the nitride films [Ref. 10]. These effects were shown to have deleterious consequences on the electrical performance of the nitride films.
  • the present invention distinguishes itself from above mentioned methods by the use of a not-intentionally doped strained nitride contact layer in order to improve the total resistance of nitride based devices.
  • This improved technique can be used as a means to reduce the resistance across the contact-to-semiconductor interface, thereby drastically reducing the operating voltage at a given current without the detrimental effects associated with doping of the nitride films.
  • the present invention satisfies this need.
  • Figures Ia- Id are schematics illustrating spontaneous and piezoelectric polarization in pseudomorphically grown AlGaN/GaN and InGaN/GaN heterostructures for Ga- face and N-face films [Ref. 4].
  • Figure 2 is a flow chart of the preferred embodiment of the present invention.
  • Figure 3 is a graph showing measured "on wafer” output power as a function of not-intentionally doped InGaN contact layer thickness.
  • Figure 4 is a schematic showing a device layer structure for electrically contacting a nitride semiconductor device, according to the present invention.
  • the present invention describes improved quality nitride devices using one or more not-intentionally doped strained contact layers.
  • Not-intentionally doped strained nitride contact layers offer a means of improving the injection efficiency of Ill-nitride devices.
  • nitrides refers to any alloy composition of the (Ga,Al,In,B)N semiconductors having the formula Ga « Al x In ⁇ B 2 N where:
  • the not-intentionally doped strained contact layers may comprise multiple layers having varying or graded compositions, a heterostructure comprising one or more layers of dissimilar (Al,Ga,In,B)N composition, or one or more layers of dissimilar (Al,Ga,In,B)N composition.
  • the not-intentionally doped strained contact layer or layers may be deposited using deposition techniques such as HVPE, MOCVD or MBE.
  • the not-intentionally doped strained contact layers may be deposited (for example, grown) in any crystallographic nitride direction, such as on a conventional c-plane oriented nitride semiconductor crystal, on a non-polar plane such as a-plane or m-plane, or on any semi-polar plane.
  • the present invention discloses a device layer structure for electrically contacting a nitride semiconductor device, comprising a p-type nitride layer of the nitride semiconductor device, an unintentionally doped (UID) strained nitride layer on the p-type nitride layer for forming a contact-to-semiconductor interface with a contact for the p-type nitride layer, wherein a resistance across the contact-to- semiconductor interface between the contact and the UID strained nitride layer is reduced as compared to a resistance across a contact-to-semiconductor interface formed directly between the contact and the p-type nitride layer.
  • the UID strained nitride layer may interface both the p-type nitride layer and the contact.
  • the UID strained nitride layer may be lattice mismatched to the p-type nitride layer.
  • the present invention further discloses a device layer structure comprising a p-type contact layer that is a semiconductor nitride layer containing at least some indium (In).
  • the p-type contact layer may be a not-intentionally doped strained nitride contact layer.
  • the nitride contact layer's thickness may be less than 10 nm.
  • the nitride contact layer may be an indium gallium nitride (InGaN) contact layer.
  • the nitride contact layer may be used in a device, such as a light emitting diode.
  • the present invention further discloses a method for fabricating a nitride semiconductor device with increased injection efficiency, comprising using an unintentionally doped (UID) strained nitride layer on a p-type nitride layer of the semiconductor nitride device for forming a contact-to-semiconductor interface with a contact for the p-type nitride layer, so that a resistance across the contact-to- semiconductor interface between the contact and the UID strained nitride layer is reduced as compared to a resistance across a contact-to-semiconductor interface formed directly between the contact and the p-type nitride layer.
  • UID unintentionally doped
  • the present invention provides a means of enhancing (Ga,Al,In,B)N devices.
  • FIG. 2 is a flowchart that illustrates the steps of the MOCVD process for the growth not-intentionally doped strained InGaN contact layer, according to the preferred embodiment of the present invention that is described in the following paragraphs.
  • a sapphire (0001) substrate is loaded into an MOCVD reactor, as shown in Block 200.
  • the reactor's heater is turned on and ramped to a set point temperature of 115O 0 C under hydrogen and/or nitrogen, as shown in Block 202.
  • nitrogen and/or hydrogen flow over the substrate at atmospheric pressure in Block 202 (which is an optional step).
  • the reactor's set point temperature is then decreased to 57O 0 C and 3 seem of trimethylgallium (TMGa) is introduced into the reactor to initiate the GaN nucleation or buffer layer growth, as shown in Block 204.
  • TMGa trimethylgallium
  • the GaN nucleation or buffer layer reaches the desired thickness.
  • the TMGa flow is shut off and the reactor's temperature is increased to 1185 0 C.
  • 15 seem of TMGa is introduced into the reactor to initiate the GaN growth for 15 minutes, as shown in Block 206.
  • 4 seem of Si 2 H 6 is introduced into the reactor to initiate the growth of n-type GaN doped with silicon for 45 minutes, as shown in block 208.
  • the reactor's temperature set point is decreased to 880 0 C, and 30 seem of Triethylgallium (TEGa) is introduced into the reactor for 200 seconds to initiate the deposition of the GaN barrier, as shown in block 210.
  • TSGa Triethylgallium
  • 70 seem of Trimethylindium (TMIn) is introduced into the reactor for 24 seconds and then shut to initiate the deposition of the InGaN quantum wells, as shown in block 210.
  • TEGa is introduced into the reactor for 160 seconds for growth of GaN and then shut; these preceding steps are referred to the LED's multiple quantum well (MQW), shown in block 210.
  • MQW LED's multiple quantum well
  • 1 seem of TMGa and 1 seem of Trimethylaluminum (TMAl) are introduced into the reactor for 100 seconds and then shut for the deposition of the AlGaN electron blocking layer, shown in block 212.
  • the reactor's set point temperature is maintained at 88O 0 C and 3.5 seem of TMGa and 50 seem of
  • Bis(cyclopentadienyl)magnesium (Cp 2 Mg) is introduced into the reactor for 12 minutes and then shut for the deposition of p-type GaN doped with magnesium, as shown in block 214.
  • the reactor set point temperature is increased to 93O 0 C and 40 sscm of TMIn along with 30 seem of TEGa are introduced for 40 seconds for growth of the not-intentionally doped strained nitride contact layer, as shown in block 216.
  • the reactor is cooled down while flowing ammonia to preserve the GaN film, as shown in Block 218.
  • the nitride diode is removed and annealed in a hydrogen deficient atmosphere for 15 minutes at a temperature of 700 0 C in order to activate the p-type GaN, as shown in Block 222.
  • Table 1 shows the voltage characteristics of an LED device structure using a not-intentionally doped strained nitride contact layer (in this case, an InGaN contact layer), known as sample B, compared to that of an LED device structure without an InGaN contact layer, known as sample A, for a drive current of 20 mA and 100 niA.
  • sample B a not-intentionally doped strained nitride contact layer
  • sample A an InGaN contact layer
  • sample B has a drastically improved contact layer due to the lower operating voltage at both 20 mA and 100 mA.
  • this improvement in operating voltage is achieved without a decrease in the measured output power of the device.
  • the use of a not-intentionally doped, strained nitride contact layer, as described in the preferred embodiment of this invention shows a dramatic enhancement in device operation by drastically reducing the operating voltage at both 20 mA and 100 mA drive currents in nitride based devices.
  • the InGaN contact layer thickness can be varied in order to study the effects of thickness on the contact layer properties.
  • the thickness of the contact layer may be varied by using 2 nm, 4 nm, and 6 nm thick contact layers.
  • Figure 3 shows the measured "on wafer” output power for the samples with various not-intentionally doped InGaN contact layer thicknesses. It is clear from the data that no degradation in output power is observed for samples with not- intentionally doped InGaN contact layer thicknesses of 2 nm and 4 nm. However, the output power dramatically decreases for the sample with 6 nm. This indicates that in order to achieve a reduction in forward voltage by using a not-intentionally doped InGaN contact layer, without compromising the device output power performance, the not-intentionally doped InGaN contact layer thickness should be less 10 nm. Possible Modifications and Variations
  • Figure 4 is a schematic showing a device layer structure for electrically contacting a nitride semiconductor device 400, comprising a p-type nitride layer 402 of the nitride semiconductor device 400, an unintentionally doped (UID) strained nitride layer 404 on the p-type nitride layer 402 for forming a contact-to- semiconductor interface 406 with a contact 408 for the p-type nitride layer 402, wherein a resistance across the contact-to-semiconductor interface 406 between the contact 408 and the UID strained nitride layer 404 is reduced as compared to a resistance across a contact-to-semiconductor interface formed directly between the contact 408 and the p-type nitride layer 402.
  • UID unintentionally doped
  • the UID strained nitride 404 layer may interface both the p-type nitride layer 402 and the contact 408 (i.e. there are no other layers between the UID layer 404 and the contact 408 or between the UID layer 404 and the p-type layer 402).
  • the UID layer 404 is typically lattice mismatched to the p-type nitride layer 402.
  • the device layer structure may comprise a p-type contact layer 404 that is a semiconductor nitride layer containing at least some indium.
  • the device layer structure is typically formed by growth, for example, by MOCVD, MBE, or HVPE (growth parameters may vary), but any method of fabrication that achieves the device layer structure having increased injection efficiency may be used (including, but not limited to non-growth methods such as wafer bonding).
  • Figure 2 shows a growth process for the growth of a not- intentionally doped strained nitride contact layer.
  • the steps may comprise loading a substrate in a growth reactor (block 200), heating the substrate under hydrogen and/or nitrogen and/or ammonia (block 202), depositing a nitride buffer layer on the substrate (block 204), depositing a nitride semiconductor on the buffer layer (block 206), depositing an n-type nitride semiconductor film on the nitride semiconductor (block 208), depositing an active layer, such as a nitride MQW, on the n-type semiconductor film (block 210), depositing an AlGaN blocking layer on the active layer (block 212), depositing a nitride p-type semiconductor film on the blocking layer (block 214), depositing a not intentionally doped strained nitride contact layer on the p-type layer (block 216), cooling the structure (block 218), thereby achieving an (Al,Ga
  • the UID layer 404 may be used to make contacts such as, but not limited to, ohmic contact and Schottky contact to the semiconductor device 400.
  • the contact 408 is typically (but not exclusively) a metal alloy.
  • Figure 4 also shows additional layers, such as an active region 410 between an n-type nitride layer 412 and the p-type nitride layer 402, wherein the device 400 is a light emitting diode.
  • additional layers such as an active region 410 between an n-type nitride layer 412 and the p-type nitride layer 402, wherein the device 400 is a light emitting diode.
  • III -nitride device layers may be grown in the ⁇ 0001> or ⁇ 000-l> direction, to achieve Ga-face, Ill-face, or N-face oriented devices.
  • UID layers may be placed in between the p-type layer 402 and the UID layer 404, or between the UID layer 404 and the contact 408.
  • UID layers may be placed in between the p-type layer 402 and the UID layer 404, or between the UID layer 404 and the contact 408.
  • "not intentionally doped" is equivalent to a UID layer.

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Abstract

La présente invention concerne une structure de couche de dispositif de diode électroluminescente comprenant une couche de contact de type p composée au moins d'indium (In). Ladite couche de contact de type p est une couche de contact de nitrure contrainte dopée de façon non intentionnelle.
PCT/US2008/062261 2007-05-01 2008-05-01 Structure de couche de dispositif de diode électroluminescente utilisant une couche de contact de nitrure d'indium gallium WO2008137573A1 (fr)

Priority Applications (1)

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JP2010506644A JP2010526444A (ja) 2007-05-01 2008-05-01 窒化インジウムガリウム接触層を使用する発光ダイオード素子層構造

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US91518907P 2007-05-01 2007-05-01
US60/915,189 2007-05-01

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US7791101B2 (en) * 2008-03-28 2010-09-07 Cree, Inc. Indium gallium nitride-based ohmic contact layers for gallium nitride-based devices
WO2010085754A1 (fr) * 2009-01-23 2010-07-29 Lumenz Inc. Dispositifs semi-conducteurs comportant des barrières de diffusion de dopant
US9437785B2 (en) * 2009-08-10 2016-09-06 Cree, Inc. Light emitting diodes including integrated backside reflector and die attach
US8445890B2 (en) 2010-03-09 2013-05-21 Micron Technology, Inc. Solid state lighting devices grown on semi-polar facets and associated methods of manufacturing
WO2016109616A1 (fr) * 2014-12-30 2016-07-07 Sensor Electronic Technology, Inc. Croissance d'hétéro-structure à limitation de déformation
WO2016197077A1 (fr) 2015-06-05 2016-12-08 Sensor Electronic Technology, Inc. Hétérostructure à couche de limitation de contraintes

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JP3592553B2 (ja) * 1998-10-15 2004-11-24 株式会社東芝 窒化ガリウム系半導体装置
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