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WO2009033965A1 - Système et procédé adaptatif d'allocation de pause d'accès direct à la mémoire - Google Patents

Système et procédé adaptatif d'allocation de pause d'accès direct à la mémoire Download PDF

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Publication number
WO2009033965A1
WO2009033965A1 PCT/EP2008/061453 EP2008061453W WO2009033965A1 WO 2009033965 A1 WO2009033965 A1 WO 2009033965A1 EP 2008061453 W EP2008061453 W EP 2008061453W WO 2009033965 A1 WO2009033965 A1 WO 2009033965A1
Authority
WO
WIPO (PCT)
Prior art keywords
dma
transactions
digital data
recording digital
series
Prior art date
Application number
PCT/EP2008/061453
Other languages
English (en)
Inventor
Wolfgang Klausberger
Stefan Abeling
Johann Maas
Herbert Schuetze
Original Assignee
Thomson Licensing
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing filed Critical Thomson Licensing
Publication of WO2009033965A1 publication Critical patent/WO2009033965A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the present invention relates to the field of mass storage solutions with multiple storage units.
  • exemplary embodiments of the present invention relate to improving data storage performance with respect to direct memory access data transfers, also known as DMA transfers, in such storage systems.
  • DMA burst transfers Before initiating a DMA transaction, the DMA engine has to check the status of the attached devices, including whether they are ready to send or receive data.
  • a DMA transfer is initiated when a device asserts a DMA request signal, also known as a DMARQ signal. The device signals the end of the DMA transaction by generating an interrupt.
  • U.S. Patent Application Publication No. 20020046367 to Yang discloses a method for preventing data corruption in a Floppy Diskette Controller.
  • the disclosed method determines the potential for data loss and/or data corruption on a data transfer by determining if, before each data transfer byte is read out or written in the floppy diskette in DMA mode, the maximum delay time for DMA request from the issue to the removal is greater than a specific value, and initializing a specific process by the computer system according to the comparison result.
  • U.S. Patent No. 5,774,681 discloses a PCI-ISA bridge device that includes a PCI interface for driving a target ready signal line when the PCI-ISA bridge device is address-specified as a current target by a read cycle on a PCI bus, and a status register for setting status information indicating respective states of a plurality of DMA request signals inputted to DMA controller. Further the PCI interface circuit includes a wait control circuit for inserting a predetermined wait time period in the timing for driving the target ready signal line, when the transaction is a read cycle for reading the content of the status register.
  • a method in accordance with the present invention is recited in claim 1 .
  • the method comprises measuring a necessary recovery time between successive ones of the DMA burst transfers, storing the necessary recovery time, and pausing for the stored necessary recovery time before each DMA burst transfer which is not a first in the sequence of DMA burst transfers.
  • the apparatus comprises a controller that includes measuring means for determining a minimum required pause duration, a memory means to store the minimum required pause duration, and at least one storage unit that is accessed by sequences of DMA burst transfers, each of the burst transfers being separated by pauses of the minimum required pause duration.
  • measuring the necessary recovery time may comprise incrementing a test pause duration over a series of DMA transactions until the necessary recovery time is determined.
  • the series of DMA transactions may comprise read transactions.
  • the series of DMA transactions may comprise write transactions.
  • the series of DMA transactions may comprise both read transactions and write transactions.
  • Fig. 1 is a block diagram of a data storage system in accordance with an exemplary embodiment of the present invention.
  • Fig. 2 is a state diagram that is useful in explaining the operation of an exemplary embodiment of the present invention.
  • Fig. 3 is a process flow diagram that shows a method in accordance with an exemplary embodiment of the present invention.
  • the data storage system shown in Fig. 1 is generally referred to by the reference number 100.
  • the data storage system 100 comprises a plurality of BusDriver modules, including a first BusDriver module 102, a second BusDriver module 104, a third BusDriver module 106 and a fourth BusDriver module 108.
  • Each of the four BusDriver modules 102, 104, 106, 108 performs the function of managing the operation of a plurality of storage devices such as ATA/ATAPI controlled devices, which are shown as Device#0,...,Device#15 in Fig. 1 .
  • the first BusDriver module 102 manages the operation of a first group of controlled storage devices 1 10.
  • the second BusDriver module 104 manages the operation of a second group of controlled storage devices 1 12.
  • the third BusDriver module 106 manages the operation of a third group of controlled storage devices 1 14.
  • the fourth BusDriver 108 manages the operation of a fourth group of controlled storage devices 1 16.
  • Each of the BusDriver modules 102, 104, 106, 108 comprises a general BusDriver controller, a Parallel Input Output unit, and a Direct Memory Access unit for each of the four storage devices it controls.
  • each Parallel Input Output unit is identified with a label in the form of PIO#n.
  • Each Direct Memory Access unit is identified with a label in the form of DMA#n.
  • the BusDriver controller associated with a first one of the first group of controlled devices 1 10 is -A- identified by the reference number 1 18 in Fig. 1 .
  • the PIO unit associated with the first one of the first group of controlled devices 1 10 is identified by the reference number 120 in Fig. 1 .
  • the DMA unit associated with the first one of the first group of controlled devices 1 10 is identified by the reference number 122 in Fig. 1 .
  • the remaining BusDriver controllers, PIO units and DMA units are not assigned separate reference numbers in Fig. 1 for clarity.
  • an exemplary one of the BusDriver modules 102, 104, 106, 108 is controlled by a system controller FPGA with an embedded software processor system not shown in Fig. 1 .
  • each of the four groups of controlled devices 1 10, 1 12, 1 14, 1 16 comprises four controlled devices. Accordingly, the exemplary data storage system 100 controls a total of 16 devices.
  • the skilled person will appreciate that other exemplary embodiments of the present invention may comprise configurations involving greater or smaller numbers of storage devices depending on design considerations for each individual system.
  • Each of the exemplary BusDriver modules 102, 104, 106 and 108 comprises a separate control path and data path. Each control path initiates upcoming transactions like commands or the like.
  • the control paths may be implemented, for example, as a serial communication interface, such as an I2C bus.
  • Each data path may comprise a real-time data path having a data bus and strobe signals for data transfer.
  • the first BusDriver module 102 comprises a control path 124 and a data path 132.
  • the second BusDriver module 104 comprises a control path 126 and a data path 134.
  • the third BusDriver module 106 comprises a control path 128 and a data path 136.
  • the fourth BusDriver module 108 comprises a control path 130 and a data path 138.
  • a system controller of the data storage system 100 initiates transfers of data in so-called clusters by sending register values for the cluster size, the cluster start address and the related command, namely "read” or "write", via one of the control paths 124, 126, 128, 130 to a respective one of the BusDriver controllers. Other registers that hold the status of finished transfers are ready to be read out by the system controller.
  • each of the respective BusDriver controllers 102, 104, 106, 108 supports its four associated DMA units in order to handle DMA transfers between the system controller and the attached groups of controlled devices 1 10, 1 12, 114, 1 16.
  • transfers are done according to the UDMA concept of the ATA interface.
  • the respective BusDriver controller 102, 104, 106, 108 will initiate read/write transfers as bursts, e.g. in sizes of multiples of 64 KB.
  • the adaptation of the pause length between DMA transfers is chosen to ensure error-free DMA read/write operations and to optimize the performance in a high-speed data recording workflow.
  • a state machine controlled by an embedded software processor may be initialized for determining or triggered to determine the minimum value of the pause that is necessary between DMA transactions. Typically, this is done as a part of a boot process of the system.
  • application contexts may exist and are encompassed by an exemplary embodiment of the invention, where determining the minimum pause duration is recommendable in more situations than just at boot time.
  • One such example is when the system involves hot-pluggable exchangeable storage devices.
  • Fig. 2 is a state diagram that is useful in explaining the operation of an exemplary embodiment of the present invention.
  • the state diagram is generally referred to by the reference number 200.
  • the state diagram 200 shows, in state-diagram style, exemplary steps for determining the minimal pause between DMA bursts to ensure error-free DMA read/write operations.
  • a system controller of the data storage system 100 which is denoted as Power PC or PPC in Fig. 2, is in an idle state 202.
  • the system controller initiates the state machine by sending the register values defining the conditions for the following process:
  • the cluster size which may be up to 16 MB, to be used for the determination transfer.
  • the Device sector start address for the determination procedure with other words the address where on the devices the DMA access shall begin.
  • the register values are read, as shown at state 204, and an interrupt is delivered to the system controller to signal the initialisation of the devices, shown at state 206.
  • the devices are denoted as "SSDs" in Fig. 2.
  • the skilled person will appreciate that the SSDs referred to in Fig. 2 correspond to the individual controlled devices 1 10, 112, 114, 116 shown in Fig. 1 .
  • the burst size for successive transfers is constant. Specifying a cluster size for the determination procedure automatically translates into a certain number of successive DMA bursts being used in the determination.
  • the cluster size and address is determined.
  • cluster size is zero, as shown at state 210, process flow is complete, as shown at state 212.
  • the system controller returns to the idle state 202. If the cluster size for a transfer is greater than zero, as shown at state 214, an initial DMA test operation runs with a pause of 0 ⁇ s between the successive transfers, as shown at state 216. This is equivalent to a local variable "i" being initialized as zero. Whenever a changed pause duration is being employed, the storage devices 1 10, 1 12, 1 14, 116 are initialised, i.e. reset and booted.
  • a loop structure is shown in which more than one DMA transaction may be performed in each iteration depending on the cluster size.
  • the cluster size is being used locally in the sense of "remaining cluster size" for the transfer.
  • the step of "calculate cluster size and address" shown at state 208 involves, for example, incrementing the previously used address or start address by the burst length and decrementing the cluster size by the burst length. After the calculation, it is tested whether or not the cluster size is zero, using the remaining cluster size as an indication whether or not any data are left over to be transferred.
  • the state machine is in a DMA_control state, as shown at state 222. If a timeout occurs during the transaction, as indicated at state 228, the pause is increased by an iteration value, for example, by 1 , 2, 3, 4 or 5 ⁇ s to name just a few exemplary values, as shown at states 216 and 218. In an exemplary embodiment of the present invention, a timeout may be considered to have occurred if no interrupt is detected during a timeout time of, for example, 100 ms. After that, the disks or other storage devices are initialized again, as shown at state 206, before the next test loop of DMA transactions can be started.
  • the adaptively determined pause duration may be referred to as a necessary recovery time or a minimum required pause duration herein.
  • the adaptively determined pause inserted between DMA bursts is only used in a streaming mode used for high-speed data storage.
  • the pause is not inserted for other data transfer tasks like reading or writing the volume info structure or the file allocation tables of the disks.
  • Such data is typically transferred either within one burst or in a separate non-streaming or PIO mode of the apparatus.
  • the minimum required pause duration is determined using read DMA accesses only. In an alternative embodiment, only write DMA accesses are used. In still another exemplary embodiment, separate minimum required pause duration values are determined for read DMA accesses and write DMA accesses.
  • the determination process may be divided into a coarse iteration part using a first increment value, and a subsequent fine iteration part where a second increment value smaller than the first increment value is being used. In between the two iterations, the momentary pause value is decreased once to the value it had before the last increase. In this manner, an exemplary embodiment of the present invention may determine the minimum pause duration value with reasonably few iterations and with good accuracy.
  • Fig. 3 is a process flow diagram that shows a method in accordance with an exemplary embodiment of the present invention.
  • the method is generally referred to by the reference number 300.
  • the skilled person will appreciate that the method 300 may be desirably performed by the data storage system 100.
  • An exemplary method in accordance with the present invention may, in addition, be implemented according to the state diagram 200.
  • the method begins.
  • a necessary recovery time between successive ones of DMA burst transfers is measured.
  • the necessary recovery time is stored, as shown at step 306.
  • a pause having a length equal to the necessary recovery time is inserted before each DMA burst transfer that is not a first transfer in a sequence of transfers. The method ends at step 310.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

La présente invention concerne un procédé (300) et un appareil (100) permettant l'enregistrement de données numériques sur une unité de stockage en utilisant des séquences de transfert de rafales DMA pour accéder à l'unité de stockage. Un procédé selon l'invention comprend la mesure (304) d'un temps de récupération nécessaire entre des transferts successifs desdits transferts de rafales DMA, le stockage (306) du temps de récupération nécessaire, et la pause (308) pour le temps de récupération nécessaire stocké avant chaque transfert de rafales DMA qui n'est pas le premier dans la séquence de transferts de rafales DMA.
PCT/EP2008/061453 2007-09-13 2008-09-01 Système et procédé adaptatif d'allocation de pause d'accès direct à la mémoire WO2009033965A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07116317 2007-09-13
EP07116317.4 2007-09-13

Publications (1)

Publication Number Publication Date
WO2009033965A1 true WO2009033965A1 (fr) 2009-03-19

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02141855A (ja) * 1988-11-24 1990-05-31 Nec Corp Ｄｍａコントローラの制御方式
JPH03156553A (ja) * 1989-11-14 1991-07-04 Hitachi Ltd Ｄｍａ制御装置および情報処理システム
EP0534529A1 (fr) * 1991-09-16 1993-03-31 International Business Machines Corporation Dispositif et méthode pour transfèrer des données en rafale
US5778198A (en) * 1995-06-14 1998-07-07 Brother Kogyo Kabushiki Kaisha Data transferring method and system utilizing a transfer-related waiting time
US20060174169A1 (en) * 2005-01-28 2006-08-03 Sony Computer Entertainment Inc. IO direct memory access system and method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02141855A (ja) * 1988-11-24 1990-05-31 Nec Corp Ｄｍａコントローラの制御方式
JPH03156553A (ja) * 1989-11-14 1991-07-04 Hitachi Ltd Ｄｍａ制御装置および情報処理システム
EP0534529A1 (fr) * 1991-09-16 1993-03-31 International Business Machines Corporation Dispositif et méthode pour transfèrer des données en rafale
US5778198A (en) * 1995-06-14 1998-07-07 Brother Kogyo Kabushiki Kaisha Data transferring method and system utilizing a transfer-related waiting time
US20060174169A1 (en) * 2005-01-28 2006-08-03 Sony Computer Entertainment Inc. IO direct memory access system and method

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