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WO2011066730A1 - Transistor à effet de champ à grille isolante cmos en mode inversion à orientation cristallographique hybride - Google Patents

Transistor à effet de champ à grille isolante cmos en mode inversion à orientation cristallographique hybride Download PDF

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Publication number
WO2011066730A1
WO2011066730A1 PCT/CN2010/070653 CN2010070653W WO2011066730A1 WO 2011066730 A1 WO2011066730 A1 WO 2011066730A1 CN 2010070653 W CN2010070653 W CN 2010070653W WO 2011066730 A1 WO2011066730 A1 WO 2011066730A1
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WIPO (PCT)
Prior art keywords
channel
region
gate
field effect
effect transistor
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Application number
PCT/CN2010/070653
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English (en)
Chinese (zh)
Inventor
肖德元
王曦
张苗
陈静
薛忠营
Original Assignee
中国科学院上海微系统与信息技术研究所
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Priority to US12/810,740 priority Critical patent/US8330229B2/en
Publication of WO2011066730A1 publication Critical patent/WO2011066730A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to the field of semiconductor manufacturing technologies, and in particular, to an inversion mode full-enclosed gate CMOS field effect transistor in which a mixed crystal orientation is used.
  • CMOS Complementary Meta l Oxide Semiconductor
  • I. ff device leakage current
  • I.J device leakage current
  • I.J threshold voltage
  • Silicon-on-insulator refers to a substrate technology that replaces traditional bulk silicon with an "engineered" substrate.
  • the substrate is usually composed of the following three layers: a thin monocrystalline silicon top layer, An etched circuit is formed thereon; a relatively thin buried oxide layer (BOX, bur ied oxide), that is, an insulating silicon dioxide intermediate layer; a very thick body type bottom silicon village bottom layer, whose main function is to provide mechanical equipment for the upper two layers support. Since the oxide layer in the SOI structure separates the silicon film layer from the bottom layer of the bulk silicon substrate, the large-area ⁇ - ⁇ junction will be replaced by a dielectric lectr ici solat ion.
  • BOX bur ied oxide
  • the source region and the drain region extend down to the buried oxide layer, effectively reducing leakage current and junction capacitance.
  • this can be improved by reducing the thickness of the silicon, whether it is a partially depleted or fully depleted design.
  • Channel-based inversion mode compared to conventional planar CMOS devices Double-gate or triple-gate fin FETs with good gate control and scaling down capability
  • the inversion mode field effect transistor has different impurity doping types of the source region and the drain region than the channel impurity doping type, the conductive carriers are minority carriers (small children), and the source region and the drain region are respectively in the trench. There is a PN junction between the tracks. This structural device is currently the most widely used.
  • the hole mobility at the (110) Si village current is more than doubled in the ⁇ 110> crystal orientation compared with the conventional (100) Si substrate.
  • the electron mobility is the highest at the (100) Si village.
  • IBM et al. developed a new technology for manufacturing CMOS circuits using mixed crystal orientation Si. Yang M, leong M, Shi L et al. introduced their technology in the article "High performance CMOS fabricated on hybrid substrate with different crystal orientations" published in the Digest of Technical Paper of International Electron Devices Meeting, 2003.
  • the CMOS device is fabricated on the (100) crystal Si surface with buried oxide layer, while the PMOS device is fabricated on the (110) crystal plane Si, and the performance of the PM0S device is greatly improved.
  • I. Ff 100 ⁇ / ⁇ m
  • (110) PMOS device drive current on the bottom of the village increased by 45%.
  • the disadvantage is that the PMOS device fabricated on the epitaxial layer does not have a buried oxide layer to isolate it from the substrate, so device performance is still affected.
  • the technical problem to be solved by the present invention is to provide a hybrid crystal inversion mode full-enclosed gate CMOS field effect transistor.
  • a mixed crystal inversion mode full-enclosed gate CMOS field effect transistor comprising: a semiconductor substrate, a MN region having a second channel above the semiconductor substrate, and a first channel above the MN region PMOS region and a gate region, the PMOS region and the MN region further include The source region and the drain region at both ends of the channel are characterized in that: the first channel and the second channel have a waist-shaped cross section, a semicircle from the left and right ends, and a semicircle at the center and the left and right ends.
  • the transition-connected rectangles are formed together, and the first channel is made of an n-type (110) S i material, the second channel is made of a p-type (100) S i material; the gate region is the first trench a surface of the channel and the second channel is completely surrounded; a first buried oxide layer is disposed between the PMOS region and the MOS region; and between the MN region and the semiconductor substrate Two buried oxide layers.
  • the present invention also provides a mixed crystal inversion mode full-enclosed gate CMOS field effect transistor, comprising: a semiconductor substrate, a PMOS region having a first channel above a semiconductor substrate, and a second region above the PMOS region a NMOS region and a gate region of the channel, the PMOS region and the NMOS region further comprising source and drain regions respectively located at opposite ends of the channel, wherein: the first channel and the second channel
  • the cross section is a waist shape, and is composed of a semicircle at the left and right ends, and a rectangle which is connected with the semicircle at the left and right ends in the middle, and the first channel adopts an n-type (110) S i material, and the second groove a p-type (100) S i material is used; the gate region completely surrounds the surfaces of the first channel and the second channel; and a first buried layer is disposed between the PMOS region and the NMOS region An oxide layer; a second buried oxide layer is disposed between the PMOS region
  • the device structure of the invention has the advantages of single, compact and high integration.
  • different crystal orientation channels, racetrack-shaped full-enclosed gate structures, high dielectric constant gate dielectrics and metal gates have high current carrying current.
  • Sub-mobility can avoid polysilicon gate depletion and short channel effects.
  • FIG. la-lc is a schematic structural diagram of a device according to Embodiment 1 of the present invention:
  • Figure la is a top view
  • Figure lb is a cross-sectional view of Figure la along XX ';
  • Figure lc is a cross-sectional view of the figure la along the ZZ ' direction.
  • FIG. 2 is a perspective view showing a channel portion of a device structure according to Embodiment 1 of the present invention.
  • 3 is a schematic cross-sectional view of a channel structure of the present invention.
  • 4a is a top plan view of a transistor in the first embodiment of the present invention.
  • Figure 4b is a cross-sectional view along line XX' of Figure 4a.
  • 5a-5c are schematic diagrams showing the structure of a device according to a second embodiment of the present invention:
  • Figure 5a is a plan view
  • Figure 5b is a cross-sectional view along line XX' of Figure 5a;
  • Figure 5c is a cross-sectional view of Figure 5a taken along the line ZZ'.
  • 6a is a top plan view of a transistor in a second embodiment of the present invention.
  • Figure 6b is a cross-sectional view of Figure 6a taken along XX '.
  • the mixed crystal inversion mode full-enclosed gate CMOS field effect transistor of this embodiment includes: a semiconductor substrate 100, a PMOS region 400 having a first channel 401, and a second channel 301.
  • the cross sections of the first channel 401 and the second channel 301 are both waist-shaped (racetrack shape), and the first channel 401 is preferably an n-type (110) S i material, the second channel 301 is preferably a p-type (100) S i material.
  • the gate region 500 completely surrounds the surfaces of the first channel 401 and the second channel 301.
  • the shape of the cross section of the first channel 401 and the second channel 301 is formed by a semicircle at the left and right ends and a rectangle that is connected to the semicircle at the left and right ends in the middle. As shown in Figure 3, it can be decomposed into a dual gate channel structure and a cylindrical full-enclosed gate channel structure that operate independently in parallel.
  • d is the diameter of the semicircle at the left and right ends of the cross section
  • w is the width of the middle rectangle
  • the total width of the raceway cross section is d+w
  • x is the thickness of the gate dielectric layer.
  • a first buried oxide layer 201 (BOX) is provided to isolate them to avoid between the regions. Interfere with each other.
  • a second buried oxide layer 202 is provided in addition to the portion covered by the gate region 500. The second buried oxide layer 202 can isolate the NMOS region 300 or the PMOS region 400 from the semiconductor substrate 100, effectively reducing leakage current, thereby improving device performance.
  • the PM0S region 400 and the MN region 300 further include source and drain regions respectively located at opposite ends of the channel.
  • the source region 403 of the PM0S region and the drain region 402 of the PMOS region are heavily doped p-type (110) S i materials or GeS i materials; the source region 303 of the ⁇ OS region and the drain region 302 of the MN region are heavily doped An n-type (100) S i material or a S iC material.
  • the length of the source/drain region located in the lower layer parallel to the channel direction is greater than the length of the source and drain regions located in the upper layer, so that the source and drain regions of the lower layer are exposed, thereby facilitating the extraction of the electrodes. Referring to Fig. la, the width of both ends of the source/drain region perpendicular to the channel direction is larger than the diameter of the channel, that is, the PM0S region 400 and the ⁇ OS region 300 have a fin shape with a narrow central end.
  • the gate region 500 includes: a gate dielectric layer 501 completely surrounding the surfaces of the first trench 401 and the second trench 301, and a gate completely surrounding the gate dielectric layer 501 Material layer 502.
  • the gate material layer 502 is a metal or an all-metal silicide; the metal or all-metal silicide is selected from the group consisting of titanium, nickel, tantalum, tungsten, tantalum nitride, tungsten nitride, titanium nitride, titanium silicide And one or a combination of tungsten silicide and nickel silicide; the material of the gate dielectric layer 502 may be one of a silicon dioxide, a silicon oxynitride compound, a silicon oxycarbide compound or a germanium-based high dielectric constant material.
  • the semiconductor substrate 100 is a S i village bottom, and may be other semiconductor materials such as Ge, Ga, and In.
  • the length L of the first channel 401 and the second channel 402 is 10-50 nm, and the diameter d of the semicircle at the left and right ends of the cross section is 10 -80 nm, the width of the middle rectangle is 10 - 200 nm.
  • the first buried oxide layer 201 and the second buried oxide layer 202 each have a thickness of 10 to 200 nm, and the materials thereof are all silicon dioxide.
  • a complete transistor can be obtained through a subsequent semiconductor fabrication process.
  • Fig. 4a is a plan view of the transistor of the embodiment, and Fig. 4b is a cross-sectional view thereof.
  • the subsequent semiconductor manufacturing process includes: forming a gate on the gate material layer 502, a source region 403 in the PMOS region, a source region 303 in the MN region, a drain region 402 in the PMOS region, and a MN Area A source and a drain are formed on the drain region 302 of the domain, respectively.
  • an insulator dielectric spacer structure 503 is further disposed on both sides of the gate, and the material thereof may be silicon dioxide, silicon nitride or the like.
  • the device structure of the hybrid crystal inversion mode full-enclosed gate CMOS field effect transistor of the present embodiment includes: a semiconductor substrate 100' having a first channel 401 'PM0S region 400', NM0S region 300' having a second channel 301' and a gate region 500'.
  • the cross section of the first channel 401' and the second channel 301' are both waist-shaped, and are formed by a semicircle at the left and right ends, and a rectangle which is connected with the semicircle at the left and right ends in the middle, and the first groove
  • the track 401' is preferably an n-type (110) S i material
  • the second channel 301 ' is preferably a p-type (100) S i material.
  • the gate region 500' completely surrounds the surfaces of the first channel 401' and the second channel 301'.
  • a first buried oxide layer 201' (BOX) is also provided to isolate them to avoid between the regions.
  • a second buried oxide layer 202' is provided in addition to the portion covered by the gate region 500'.
  • the PM0S region 400' and the MN region 300' further include source regions 403', 303' and drain regions 402', 302' located at opposite ends of the channel.
  • the gate region 500' includes: a gate dielectric layer 50 that completely surrounds the surfaces of the first trench 401' and the second trench 301', and a gate material layer 502' that completely surrounds the gate dielectric layer 50.
  • the MN OS area 300' of the second embodiment is above the PMOS area 400', and the PM0S area 400' is above the semiconductor ridge 100', except for the second embodiment and the implementation.
  • the other technical solutions of the first example are the same.
  • a complete transistor can be obtained through subsequent semiconductor fabrication processes.
  • Fig. 6a is a plan view of the transistor of the embodiment, and Fig. 6b is a cross-sectional view thereof.
  • the subsequent semiconductor manufacturing process includes: forming a gate on the gate material layer 502', a source region 403' in the PMOS region, a source region 303' in the NMOS region, and a drain region 402' in the PM0S region.
  • the source and drain electrodes are respectively formed on the drain region 302' of the NM0S region.
  • An insulator dielectric spacer structure 503' is also formed on both sides of the gate, and the material thereof may be silicon dioxide, silicon nitride or the like.
  • the PM0S region and the ⁇ OS region use different SiS materials, especially the first channel uses n-type (110) S i material, and the second channel uses p-type (100)
  • the conductive carriers are minority carriers (small sub-), that is, the conductive carriers of the first channel are holes in the n-type (110) S i material
  • the two-channel conductive carriers are electrons in the p-type (100) S i material.
  • the invention adopts two different SiS materials with different crystal orientations, which is beneficial to further increase the carrier migration rate; on the other hand, the PM0S region and the Li OS region simultaneously have a buried oxide layer and the bottom of the village. Isolation can effectively reduce leakage current, enabling the device to have better performance and further scaling down.
  • the present invention also employs a full-enclosed gate channel structure having a cross-sectional waist (racetrack shape) which can be decomposed into a double gate channel structure and a cylindrical full-enclosed gate channel structure which operate independently in parallel.
  • the advantages of this configuration are: cum increases the channel cross-sectional area (increased rectangular portion), increasing the drive current of the device while maintaining the electrical integrity of the device (circular channel).
  • the present invention adopts a relatively accurate fluid dynamics model and a quantum mechanical density grading model, and considers and applies a mobility degradation model related to doping and surface roughness for three-dimensional.
  • Technical simulation. The simulation results show that the CMOS transistor of the present invention has high carrier mobility, low-low frequency device noise, and avoids polysilicon gate depletion and short channel effect, and increases the threshold voltage of the device in the inversion mode.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un transistor à effet de champ à grille isolante CMOS en mode inversion à orientation cristallographique hybride. Le CMOS FET comprend une région PMOS avec un premier canal (401), une région NMOS avec un second canal (301) et une région grille (500), le premier canal et le second canal présentant une coupe transversale en forme d'anneau allongé. Le premier canal (401) utilise un matériau en Si de type n (110) et le second canal (301) utilise un matériau Si de type p (100). La région grille (500) entoure complètement la surface des premier (401) et second (301) canaux. Des oxydes enfouis (202) viennent entre les régions PMOS et NMOS, et entre la région PMOS ou la région NMOS et le substrat Si de manière à les isoler. Cette structure en cristal hybride présente une configuration simple, un bon niveau d'intégration et est compact. En mode opérationnel d'inversion, les canaux en matériau à orientation cristallographique, la structure à grille isolante en forme d'anneau allongé, le diélectrique à forte permittivité et la grille métallique présentent une circulation élevée de courant de manière à éviter la déplétion de la grille en polysilicium et l'effet canal court.
PCT/CN2010/070653 2009-12-01 2010-02-11 Transistor à effet de champ à grille isolante cmos en mode inversion à orientation cristallographique hybride WO2011066730A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/810,740 US8330229B2 (en) 2009-12-01 2010-02-11 Hybrid orientation inversion mode GAA CMOSFET

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200910199724.2 2009-12-01
CN2009101997242A CN101719501B (zh) 2009-12-01 2009-12-01 混合晶向反型模式全包围栅cmos场效应晶体管

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WO2011066730A1 true WO2011066730A1 (fr) 2011-06-09

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US (1) US8330229B2 (fr)
CN (1) CN101719501B (fr)
WO (1) WO2011066730A1 (fr)

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