WO2012006766A1

WO2012006766A1 - Semiconductor structure and manufacturing method thereof

Info

Publication number: WO2012006766A1
Application number: PCT/CN2010/001498
Authority: WO
Inventors: 朱慧珑; 尹海洲; 骆志炯
Original assignee: 中国科学院微电子研究所
Priority date: 2010-07-14
Filing date: 2010-09-27
Publication date: 2012-01-19
Also published as: CN102339813A

Abstract

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor device comprises a semiconductor substrate (100), a local interconnection structure (120) connected with the semiconductor substrate (100), a laminated structure of through hole (220) electrically connected with the local interconnection structure (120). The laminated structure of through hole (220) comprises a through hole (221), a through hole sidewall (224), an insulating layer (225) and a conductive plug (226), wherein, the through hole (221) includes an upper through hole (222) and a lower through hole (223), the width of the upper through hole (222) is larger than the width of the lower through hole (223); the through hole sidewall (224) is adjacent to the inner wall of the lower through hole (223); the surface of the through hole (221) and the through hole sidewall (224) is covered with the insulating layer (225); the conductive plug (226) is formed in a space enclosed by the insulating layer (225) and is electrically connected with the local interconnection structure (120).

Description

Semiconductor structure and method of manufacturing the same

The present invention relates to the field of semiconductors, and more particularly to semiconductor structures and methods of fabricating the same, and more particularly to a method for fabricating a self-aligned via stack having a variable via size and fabricated using the method A semiconductor structure having a variable via size self-aligned via stack. Background technique

As the spacing of the semiconductor devices decreases, the metal wiring over the vias causes an increase in via-via short-circuit problems, and thus the via-metal line in the lithography process. Wire alignment requirements are higher, which leads to higher costs for mass production. Another method is to make smaller vias, but this further increases the need for lithography.

There is currently a method of self-aligning the fabrication of via stacks that can simultaneously form vias and metal traces. Through-holes and metal wirings formed at the same time are referred to as via laminates. Hereinafter, this process and existing problems will be described in detail in conjunction with FIG. Figures 1 (a) - (d) show a schematic diagram of a self-aligned via stack. The self-aligned via stack mainly comprises: an etch stop layer 1001, an interlayer dielectric ILD layer 1002 on the etch stop layer, and a hard mask HM (Hard Mask) layer 1003 on the ILD layer 1002. As shown in Fig. 1(a), by coating the photoresist 1004, the photoresist is patterned so that via holes are formed between the remaining photoresists 1004. Next, as shown in Fig. 1(b), the HM layer is etched to further form via holes in the HM layer, and then the remaining photoresist and the etched polymer are removed by cleaning. As shown in Fig. 1(c), after the via patterning is completed, the photoresist pattern 1005 is overlaid onto the hard mask layer to define a pattern of metal wiring to be formed. Further etching into the ILD layer 1002 is performed using the HM 1003 on the ILD layer 1002 and the photoresist pattern 1005 as a mask. As shown in Figure 1 (d), the via is formed by etching, and the width of the upper portion of the via is larger than the width of the lower portion. Finally, a conductive plug is formed in the formed via hole, the upper portion of the conductive plug is wider, and is used as a metal wire; the lower portion of the conductive plug is narrow, and is used for a conductive plug in the through silicon via, usually electrically connected with the interconnect structure on the semiconductor structure connection. This forms a via stack structure by a self-aligned technique.

However, with the self-aligned via stack structure shown in FIG. 1, the short-circuit problem may still be caused due to the inability to freely change the via size. Summary of the invention In view of the above drawbacks of the conventional process, the present invention proposes a semiconductor structure with a self-aligned via stack structure of variable size.

According to a first aspect of the present invention, a semiconductor structure is provided, comprising: a semiconductor substrate; a local interconnect structure connected to the semiconductor substrate; a via stack structure electrically connected to the local interconnect structure; wherein the via hole The laminated structure comprises: a via hole, the via hole comprises an upper via hole and a lower via hole, wherein the width of the upper via hole is larger than the width of the lower via hole; the via sidewall wall is formed adjacent to the inner wall of the lower via hole; the insulating layer covers the via hole Forming a surface of the via sidewall; the conductive plug is formed in a space surrounded by the insulating layer and electrically connected to the local interconnect structure.

Preferably, the via sidewall spacer may have a thickness of 5-100 nm and the via has a bottom width of 30-500 nm. Alternatively, the via sidewall may be formed adjacent to the inner wall of the bottom of the via or may be formed in the middle of the lower via.

Down from the side wall of the via, the width of the conductive plug is aligned with the inner wall of the side wall of the via, so that the width of the conductive plug can be defined by the spacing of the inner walls of the side wall of the via.

Alternatively, the via sidewalls may be formed of any one of SiO 2 , Si 3 N 4 , SiON, SiOF, SiCOH, SiO, SiCO, SiCON.

The conductive plug further includes a barrier layer and a conductive material; the barrier layer covers a surface of the insulating layer, and the conductive material is formed in a space surrounded by the barrier layer. The barrier layer may be formed of a combination of one or more of TiN, TaN, Ta, Ti, TiSiN, TaSiN, TiW, WN or Ru. The conductive material may be formed of any one of \\, Al, Cu, TiAl.

The via holes in the embodiments of the present invention are formed by self-alignment. According to another aspect of the present invention, a method of fabricating a semiconductor structure is provided, comprising the steps of: providing a semiconductor substrate on which a local interconnect structure is formed; forming a via via and a via sidewall; forming a via hole covering the via hole and the via sidewall; forming a conductive plug in a space surrounded by the insulating layer; wherein the upper via hole and the lower via hole form a via hole, and the conductive plug is electrically connected to the local interconnect structure.

Optionally, the step of forming the lower via and the via sidewalls may include: forming a dielectric layer on the local interconnect structure; using a first mask pattern on the dielectric layer to define a width of the upper via to be formed; The second mask pattern defines a width of the lower via hole to be formed; using the second mask pattern as a mask, the dielectric layer is etched down to the local interconnect structure to form a self-aligned connection with the local interconnect structure Lower via hole; a via sidewall is formed along the inner wall of the bottom of the lower via.

Optionally, the step of forming the lower via and the via sidewalls may include: forming a dielectric layer on the local interconnect structure; using a first mask pattern on the dielectric layer to define a width of the upper via to be formed; Second mask pattern limit Determining the width of the lower via hole to be formed; using the second mask pattern as a mask, etching the dielectric layer downward to form a portion of the lower via hole by self-alignment; forming a via hole along the bottom inner wall of a portion of the lower via hole Side wall; using the via sidewall as a mask, further etching the dielectric layer to the local interconnect structure to complete the formation of the lower via.

Preferably, the step of forming the upper via hole comprises: removing the second mask pattern, and etching the dielectric layer downward with the first mask pattern as a mask to form an upper via hole by self-alignment, wherein the upper via hole and the lower hole Vias are connected.

Preferably, the forming of the conductive plug may include the steps of: covering the surface of the insulating layer to form a barrier layer; forming a conductive plug in a space surrounded by the barrier layer.

The semiconductor structure and the method of fabricating the same according to the embodiments of the present invention can realize self-alignment formation of via laminations, and can freely adjust the via size, avoid short circuits between the via holes, and improve the good yield of the device. DRAWINGS

The above and other objects, features and advantages of the present invention will become apparent from the <RTIgt

1 is a schematic view showing a semiconductor structure fabricated according to a conventional process;

2 to 12 are schematic views showing respective steps of a method of fabricating a semiconductor structure according to a first embodiment of the present invention, wherein FIGS. 11 and 12 illustrate a method of fabricating a semiconductor structure according to a first embodiment of the present invention. Manufacturing a completed semiconductor structure;

13 to 18 are schematic views showing respective steps of a method of fabricating a semiconductor structure according to a second embodiment of the present invention, wherein FIGS. 17 and 18 illustrate a method of fabricating a semiconductor structure according to a second embodiment of the present invention. Completed semiconductor structure.

It should be noted that the drawings are not to be construed as being limited to the scope of the invention. In the drawings, like components are identified by like reference numerals. detailed description

The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, and the details and functions that are not necessary for the present invention are omitted in the description to avoid confusion of the understanding of the present invention. First, a semiconductor structure fabricated in accordance with the process proposed by the first embodiment of the present invention will be described in detail with reference to FIGS. 11 to 12. FIG. 11 shows a method of fabricating a semiconductor structure according to a first embodiment of the present invention. A schematic representation of a semiconductor structure. As shown in FIG. 11, the semiconductor structure fabricated according to the proposed process of the present invention mainly comprises: a semiconductor substrate 100, a first dielectric layer 110 formed on the semiconductor substrate 100, and a second dielectric formed on the first dielectric layer 110. Layer 210, wherein a local interconnect structure 120 is also formed in the first dielectric layer 110. A via stack structure 220 is formed in the second dielectric layer 210 to be electrically connected to the local interconnect structure 120.

The via stack structure 220 includes: a via 221, the via 221 includes an upper via 222 and a lower via 223, and the width of the upper via 222 is greater than the width of the lower via 223 (the upper via 222 is shown in the figure) The lower via 223 is separated by a broken line; the via sidewall 224 is formed adjacent to the inner wall of the lower via 223; the insulating layer 225 is formed to cover the surface of the via 221 and the via sidewall 224; and the conductive plug 226 is formed on the insulating layer The space enclosed by 225 is electrically connected to the local interconnect structure 120.

Preferably, the via sidewall spacer 224 may have a thickness of 5-100 nm, and the via 221 may have a bottom width of 30-500 nm.

Optionally, the via sidewall spacer 224 is formed adjacent to the middle of the lower via hole 223, or may be formed on the inner wall of the bottom of the via hole 221 as shown in FIGS. 16-18.

Down from the via sidewall 224, the width of the conductive plug 226 is aligned with the inner wall of the via sidewall 224, and thus the width of the conductive plug 226 can be defined by the spacing of the inner walls of the via sidewall 224.

Alternatively, the via sidewall spacer 224 may be formed of any one of SiO ₂ , Si ₃ N ₄ , SiON, SiOF, SiC0H, Si0, SiC0, SiCON.

Referring to FIG. 12, the conductive plug 226 further includes a barrier layer 227 and a conductive material 228; the barrier layer covers the surface of the insulating layer 225, and the conductive material 228 is formed in a space surrounded by the barrier layer 227. The barrier layer 227 may be formed of a combination of one or more of TiN, TaN, Ta, Ti, TiSiN, TaSiN, TiW, WN or Ru. The conductive material 228 may be formed of any one of Al, Cu, and TiAl.

The via holes in the embodiments of the present invention are formed by self-alignment.

In Fig. 11 and Fig. 12, the through-hole laminate on the left side has a shape similar to that of the via-hole stack on the right side in a direction perpendicular to the plane of the paper, and the width of the upper via hole is larger than the width of the lower via hole. The role of metal wiring. Similarly, Figure 17 and Figure 18 are similar.

It can be seen from the semiconductor structure shown in FIG. 11 and FIG. 12 that in the semiconductor structure, the size of the through hole can be adjusted by the thickness of the side wall, and the object to be achieved by the embodiment of the present invention is achieved: The semiconductor structure of the hole stack. 17 and 18 are semiconductor structures obtained in accordance with another embodiment of the present invention.

Next, the respective steps of the semiconductor manufacturing method according to the first embodiment of the present invention will be described in detail with reference to Figs. 2 to 12. First, as shown in FIG. 2, a local interconnect structure 120 is formed on a semiconductor substrate 100 including an IC device (not shown). For example, the local interconnect structure 120 can be completed by a damascene method by first depositing an ILD layer 110 on the semiconductor substrate 100 on which the device is fabricated, which may have a thickness of 100-300 ηπι. Undoped silicon oxide (SiO ₂ ), various doped silicon oxides (such as borosilicate glass, borophosphosilicate glass, etc.) and silicon nitride (Si ₃ N ₄ ) may be used as the constituent material of the ILD layer 210. . This is followed by chemical mechanical polishing, engraving, etching, and tungsten metal deposition, followed by metal layer polishing step lithography, development, etching, cleaning, and electroplating. Wherein the local interconnect structure 120 may be composed of copper or other conductive material.

An ILD 210 is then formed over the semiconductor substrate on which the local interconnect structure 120 is formed, and may have a thickness of 100-500 nm.

Next, as shown in FIG. 3, a polysilicon layer 310 is deposited on the semiconductor structure shown in FIG. 2 as a hard mask (HM) for the next level of interconnection. Photoresist PR320 is then applied over polysilicon layer 310 and photoresist PR320 is patterned for the next level of interconnect. In addition to the polysilicon, other materials may be used as the hard mask, and those skilled in the art may select according to actual needs. As shown in FIG. 4, the polysilicon layer 310 is etched by a dry etching method using the patterned photoresist of FIG. 3 as a mask to form a hard mask as the next-level interconnection. The dry etching method may be reactive ion etching RIE. Here, the pattern of the polysilicon layer 310 formed after etching is referred to as a first mask pattern for defining the width of the upper via. Photoresist PR320 on patterned polysilicon layer 310 as a hard mask is then removed. As shown in FIG. 5, a new layer of photoresist is applied over the polysilicon layer 310 as a hard mask. The photoresist is exposed, developed, and removed to form a patterned photoresist PR330 that acts as a photoresist mask for the self-aligned via stack. The pattern formed by the photoresist PR330 patterning is referred to as a second mask pattern for defining the width of the lower via. The ILD layer 210 is then etched to half or other depth using an RIE etch that is selective to polysilicon. For example, the etch depth can depend on the requirements of the via metal plug process. Then, as shown in FIG. 6, the photoresist PR330 shown in FIG. 5 is removed. Then, spacer material 228 is deposited (5-50 nm is used to form the via side) Wall. The sidewall material 228 may be formed of any one of SiO ₂ , Si ₃ N ₄ , SiON, SiOF, SiC0H, Si0, SiC0, SiCON, or other materials may also be used.

It should be understood that the deposited via sidewall material need not fill the entire via as long as it satisfies the thickness required to form the via sidewall. As shown in Fig. 7, the sidewall material 228 in the process of Fig. 6 is subjected to RIE etching (masking step of RIE etching). A via sidewall spacer 224 as shown in Fig. 7 is formed on the sidewall of the ILD layer 210. As shown in Fig. 8, a photoresist PR340 is further formed on the structure obtained by the process of Fig. 7 for via etching. The ILD layer 210 is further etched by using RIE under the common mask of the photoresist PR340 and the via spacers 224 until the position of the interconnect 120 is reached, thereby exposing the upper surface of the interconnect 120, The structure shown in Fig. 9 forms a lower via 223. As shown in FIG. 10, the photoresist PR340 is removed, and the polysilicon 310 (first mask pattern) is used as a mask, and the ILD layer 210 is further etched using RIE to obtain the upper via 222 shown in FIG. . The upper via 222 and the lower via 223 together form a via 221 .

It can be seen that through the via side wall technology, different through hole sizes are realized under the premise of ensuring the self-alignment of the through holes. Finally, a via stack as shown in Fig. 11 is formed using a conventional method. For example, the insulating layer 225 is formed, and a conductive plug 226 is formed in a space surrounded by the insulating layer. As shown in FIG. 12, the conductive plug may further include a barrier layer 227 and a conductive material 228 formed in a space surrounded by the barrier layer. CMP polishing is performed and stopped at the ILD layer 210. The polysilicon hard mask 310 is also removed together while the CMP is being performed. Thus, the semiconductor structure according to the first embodiment of the present invention can be obtained. Next, the respective steps of the semiconductor structure manufacturing method according to the second embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4 and FIGS. 13 to 18. For the sake of brevity, the same process steps as in the first embodiment in the fabrication steps according to the second embodiment of the present invention are omitted, and the drawings of the first embodiment are referred to when describing the specific steps. First, process steps similar to those shown in Figs. 2 to 4 of the first embodiment of the present invention are performed. That is, the local interconnect structure 120 is formed on the semiconductor substrate 100 including an IC device (not shown). Local interconnection An interlayer dielectric ILD 210 is deposited over structure 120. Polysilicon 310 is deposited as a hard mask for the next level of interconnection. Photoresist PR320 is then applied over polysilicon layer 310 and photoresist PR320 is patterned for the next level of interconnect. The polysilicon 310 is etched by a dry etching method using a patterned photoresist as a mask to form a hard mask as a next-level interconnection. Then, the photoresist PR 320 on the patterned polysilicon layer 310 as a hard mask is removed. The photoresist 310 formed after patterning is used as a first mask pattern for defining the width of the upper via. Next, as shown in FIG. 13, another photoresist layer PR 330 using a self-aligned via is patterned. Photoresist 330 is referred to as a second pattern mask for defining the width of the lower via. Then, using the second pattern mask, the ILD layer 210 is etched to the local interconnect structure 120 to be connected by reactive ion etching RIE, exposing the upper surface of the local interconnect connection 120 to be connected, thereby forming a lower Via 223. Then, as shown in FIG. 14, the photoresist layer PR330 is removed, and then sidewall material 208 (5-50 nm), such as a nitride or low-k material, is deposited. It should be noted that the deposited sidewall material 208 does not fill the entire via, but fills a portion of the via. Then, the sidewall material is subjected to RIE to form the via spacers 204 on the sidewalls of the interlayer dielectric layer 210 instead of the hard mask, resulting in a structure as shown in FIG. The upper surface of the local interconnect structure 120 to be joined is exposed by RIE etching of the sidewall material 208. Next, as shown in FIG. 15, the polysilicon layer 310 (first pattern mask) is used as a hard mask, and the interlayer dielectric layer 210 is etched by RIE to obtain an upper via hole 222, which forms a structure as shown in FIG. . The upper via 222 and the lower via 223 form a via 221 . On the basis of the structure shown in Fig. 16, the structure shown in Fig. 17 is formed using a conventional method. For example, the insulating layer 225 is formed, the conductive plug 226 is formed, CMP polishing is performed, and CMP polishing is stopped at the interlayer dielectric layer 210. The polysilicon layer 310 is also removed together while the CMP is being performed. Thus, a semiconductor structure according to the second embodiment of the present invention can be obtained.

As shown in FIG. 18, the conductive plug 226 may further include a barrier layer 227 and a conductive material 228.

The prior art problem of self-aligned vias is that the vias are too large to easily form a short circuit with the local interconnect structure, and the self-aligned via stack structure according to the embodiment of the present invention avoids the prior art. In the defect, a via stack having a variable via size can be realized. The invention has thus far been described in connection with the preferred embodiments. It will be appreciated that various other changes, substitutions and additions may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention is not limited to the specific embodiments described above, but is defined by the appended claims.

Claims

Rights request

1 . A semiconductor structure comprising: a semiconductor substrate;

a local interconnect structure connected to the semiconductor substrate;

a via laminate structure electrically connected to the local interconnect structure;

The through-hole lamination structure includes:

a via hole, the via hole including an upper via hole and a lower via hole, wherein the upper via hole has a width larger than a width of the lower via hole; the via sidewall spacer is formed adjacent to an inner wall of the lower via hole;

An insulating layer covering the surface of the via hole and the via sidewall;

A conductive plug is formed in a space surrounded by the insulating layer and electrically connected to the local interconnect structure.

2. The semiconductor structure according to claim 1, wherein the via sidewall spacer has a thickness of 5-100 nm.

3. The semiconductor structure of claim 1 wherein the via has a bottom width of 30-500 nm.

4. The semiconductor structure according to claim 1, wherein the via sidewall is formed adjacent to an inner wall of the via bottom.

5. The semiconductor structure according to claim 1, wherein a width of the conductive plug is aligned with an inner wall of the via sidewall according to the via sidewall.

6. The semiconductor structure of claim 1, wherein the via sidewalls are formed of any one of SiO ₂ , Si ₃ N ₄ , SiON, SiOF, SiCOH, SiO, SiCO, SiCON.

7. The semiconductor structure according to claim 1, wherein the conductive plug further comprises a barrier layer and a conductive material; the barrier layer covers a surface of the insulating layer, and the conductive material is formed in the barrier layer Within the space.

8. The semiconductor structure according to claim 7, wherein the barrier layer is formed of a combination of one or more of TiN, TaN, Ta, Ti, TiSiN, TaSiN, TiW, WN or Ru.

9. The semiconductor structure of claim 7, wherein the conductive material is formed of any one of W, Al, Cu, TiAl.

The semiconductor structure according to any one of claims 1 to 9, wherein the via holes are formed by self-alignment.

11. A method of fabricating a semiconductor structure, comprising the steps of:

Providing a semiconductor substrate on which a local interconnect structure is formed; Forming a lower via and a via sidewall;

Forming a via hole;

Covering the lower via, the upper via, and the via sidewall to form an insulating layer;

Forming a conductive plug in a space surrounded by the insulating layer;

The upper via and the lower via form a via, and the conductive plug is electrically connected to the local interconnect structure.

12. The method of claim 11, wherein forming the lower via and via sidewalls comprises: forming a dielectric layer on the local interconnect structure;

Using a first mask pattern on the dielectric layer to define a width of an upper via that needs to be formed;

Depicting a width of a lower via that needs to be formed using a second mask pattern;

Using the second mask pattern as a mask, etching the dielectric layer down to the local interconnect structure to form a lower via that communicates with the local interconnect structure by self-alignment;

A via sidewall is formed along the inner wall of the bottom of the lower via.

13. The method of claim 11, wherein forming the lower via and via sidewalls comprises: forming a dielectric layer on the local interconnect structure;

Using the second mask pattern as a mask, etching the dielectric layer downward to form a portion of the lower via hole;

Forming a via sidewall along a bottom inner wall of a portion of the lower via;

Forming the dielectric layer to the local interconnect structure by using the via sidewall as a mask to complete the formation of the via.

The method according to claim 12 or 13, wherein the forming the upper via comprises: removing the second mask pattern;

The dielectric layer is etched downward by using the first mask pattern as a mask to form an upper via by self-alignment; wherein the upper via is in communication with the lower via.

The method according to any one of claims 11 to 13, wherein the forming of the conductive plug comprises: forming a barrier layer covering a surface of the insulating layer;

A conductive material is formed in a space surrounded by the barrier layer.