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WO2012153835A1 - Carte de câblage imprimé - Google Patents

Carte de câblage imprimé Download PDF

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Publication number
WO2012153835A1
WO2012153835A1 PCT/JP2012/062122 JP2012062122W WO2012153835A1 WO 2012153835 A1 WO2012153835 A1 WO 2012153835A1 JP 2012062122 W JP2012062122 W JP 2012062122W WO 2012153835 A1 WO2012153835 A1 WO 2012153835A1
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
hole
wiring board
gnd
bypass capacitor
Prior art date
Application number
PCT/JP2012/062122
Other languages
English (en)
Japanese (ja)
Inventor
貴士 足立
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Publication of WO2012153835A1 publication Critical patent/WO2012153835A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections

Definitions

  • the present invention generally relates to a printed wiring board, and more particularly to a mounting structure of a bypass capacitor for reducing power feeding system electromagnetic noise.
  • Patent Document 1 Japanese Patent No. 3610127
  • Patent Document 2 Japanese Patent Laid-Open No. 2010-98162 disclose a wiring board using a bypass capacitor.
  • the printed circuit board disclosed in Patent Document 1 has a plurality of printed patterns wired in four directions on the front surface of a two-layer printed wiring board in which a printed circuit pattern is formed on the front surface and the back surface through an insulating base. It is a printed circuit board for mounting a circuit element.
  • FIG. 4A is a plan view showing the surface side of the printed wiring board disclosed in Patent Document 1.
  • FIG. 4B is a perspective plan view showing the back side of the printed wiring board disclosed in Patent Document 1.
  • FIG. 4A and 4B a plurality of lands 102 on which electronic circuit elements are mounted are disposed on the surface 101a.
  • a ground pattern 103 is disposed on the front surface 101a and the back surface 101b.
  • a main power supply pattern 104 is disposed on the back surface 101b.
  • On the back surface 101 b a power supply branch pattern 105 that branches from the main power supply pattern 104 and connects to a part of the plurality of lands 102 is provided.
  • a bypass capacitor is disposed between the power supply branch pattern 105 and the ground pattern 103.
  • the power supply branch pattern 105 is based on the connection portion 106 between the bypass capacitor and the power supply branch pattern 105, and the power supply from the connection portion 106 is higher than the inductance from the connection portion 106 to the land 102 connecting the electronic circuit and the power supply branch pattern 105.
  • the inductance to the branch pattern 105 and the main power supply pattern 104 is formed to be large.
  • an ideal T-type low-pass filter can be formed, the high frequency current loop of the power supply system can be reduced, and the radiation noise generated in the power supply line can be reduced.
  • FIG. 5 is a plan view showing the configuration of the printed wiring board disclosed in Patent Document 2.
  • FIG. 5 in the printed wiring board disclosed in Patent Document 2, power is supplied to semiconductor device 202 by power supply wiring 210 and ground lead wiring 211 connected to the power supply layer and ground layer of printed wiring board 201. ing.
  • the power supply terminal 203 of the semiconductor device 202 is connected to the bypass capacitor 207 via the power supply wiring 210.
  • One end of the bypass capacitor 207 is connected to the power supply layer via a via hole 205 connected to the power supply layer.
  • the other end of the bypass capacitor 207 is connected to the ground layer via the via hole 206b.
  • the ground terminal 204 of the semiconductor device 202 is connected to the ground layer via the via hole 206 a via the ground lead wiring 211.
  • the power supply wiring 210 connecting the bypass capacitor 207 and the power supply terminal 203 and the via hole 206a and the via hole 206b connected to the ground layer are arranged in the same straight line, so that the power supply current 208 and the ground current 209 are arranged. Therefore, the impedance of the power feeding system can be reduced and the electromagnetic noise can be reduced.
  • the printed circuit board disclosed in Patent Document 1 has a structure in which a bypass capacitor is mounted on the back side of an IC (Integrated Circuit) in order to reduce a high frequency current loop of a power supply system. For this reason, there are problems that the work of separately mounting the IC and the bypass capacitor on the front surface and the back surface of the substrate is complicated, and the thickness of the printed wiring board is increased.
  • IC Integrated Circuit
  • an object of the present invention is to solve the above-mentioned problem, and an IC and a bypass capacitor can be mounted on the same surface of the wiring board without using a multilayer wiring board having a complicated structure, and electromagnetic noise can be reduced. It is to provide a printed wiring board.
  • the printed wiring board according to the present invention includes a semiconductor element and a bypass capacitor mounted on the first surface, and a first power supply wiring and a GND pattern formed on the second surface.
  • the semiconductor element has a power supply pin and a GND pin.
  • the printed wiring board further includes a first GND wiring and a second GND wiring formed on the first surface, a first through hole, a second through hole, and a third through hole.
  • the first terminal of the bypass capacitor is connected to the power supply pin and the first power supply wiring through the first through hole.
  • the second terminal of the bypass capacitor is connected to the second through hole.
  • the GND pin of the semiconductor element is connected to the GND pattern from the first GND wiring on the first surface through the third through hole.
  • an IC and a bypass capacitor can be mounted on the same surface of a wiring board without using a multilayer wiring board having a complicated structure, and a printed wiring board that can reduce electromagnetic noise is provided. Can be provided.
  • FIG. 10 is a plan view showing a surface side of a printed wiring board disclosed in Patent Document 1.
  • FIG. FIG. 6 is a perspective plan view showing the back side of a printed wiring board disclosed in Patent Document 1.
  • 10 is a plan view showing a configuration of a printed wiring board disclosed in Patent Document 2.
  • FIG. 1A is a plan view showing the surface side of the printed wiring board according to Embodiment 1 of the present invention.
  • FIG. 1B is a perspective plan view showing the back side of the printed wiring board according to Embodiment 1 of the present invention.
  • FIG. 1C is a perspective plan view showing the front surface side and the back surface side of the printed wiring board according to Embodiment 1 of the present invention superimposed on each other.
  • FIGS. 1A, 1B, and 1C in the printed wiring board according to the present embodiment, patterns are formed on the front surface and the back surface of the insulating base, respectively, and the structure is simpler than that of the multilayer printed wiring board. A layer printed wiring board is used.
  • a mounting region 3 on which the semiconductor element 1 and the bypass capacitor 2 are mounted is provided on the surface side as the first surface of the printed wiring board.
  • a GND pattern 4 occupying a large area of the second surface, and a first power supply wiring 5 insulated and separated from the GND pattern 4 Is formed.
  • the periphery of the mounting region 3 is covered with a conductive GND pattern 6 in order to prevent external radiation noise from entering.
  • the semiconductor element 1 has a plurality of connection pins including a power supply pin 11 and a GND pin 12 for power supply around the semiconductor element 1.
  • the power supply pin 11 is connected to the second power supply wiring 13, and the GND pin 12 is connected to the first GND wiring 14.
  • the bypass capacitor 2 is disposed in the vicinity of the power supply pin 11 of the semiconductor element 1.
  • the first terminal 21 of the bypass capacitor 2 is connected to the power supply pin 11 by the second power supply wiring 13, and the second terminal 22 of the bypass capacitor 2 is connected to the second GND wiring 15.
  • the second power supply wiring 13 on the first surface and the first power supply wiring 5 on the second surface are connected to the second power supply wiring 13 of the bypass capacitor 2. They are connected to each other through a first through hole 31 disposed in the vicinity of one terminal 21.
  • the second GND wiring 15 on the first surface and the GND pattern 4 on the second surface are connected to each other through the second through hole 32 disposed between the first power supply wiring 5 and the semiconductor element 1 in the substrate surface.
  • the first GND wiring 14 on the first surface and the GND pattern 4 on the second surface are connected to each other via a third through hole 33 disposed between the second through hole 32 and the GND pin 12.
  • the second through hole 32 is disposed between the first power supply wiring 5 and the semiconductor element 1 in the substrate surface, so that the GND current 41 flowing between the GND pin 12 and the second through hole 32 is obtained. Is formed on a substantially straight line without intersecting the first power supply wiring 5. For this reason, the current loop between the semiconductor element 1 and the bypass capacitor 2 is reduced, and electromagnetic noise generated from the power feeding system of the semiconductor element 1 can be reduced.
  • the arrangement of the first through hole 31, the second through hole 32, and the third through hole 33 can be adjusted within the above range.
  • FIG. 2A is a current distribution diagram showing the surface side of the substrate, which is the result of the near magnetic field analysis of the printed wiring board.
  • FIG. 2B is a current distribution diagram showing the result of the near magnetic field analysis of the printed wiring board and showing the back side of the board.
  • the same reference numerals are given to the portions showing the same parts as in FIG.
  • the power supply current 42 flowing between the power supply pin 11 and the bypass capacitor 2 and the GND pattern 4 as shown in FIG. 2B are provided.
  • the GND current 41 flowing between the second through hole 32 and the third through hole 33 flows through the shortest path without bypassing the first power supply wiring 5.
  • Embodiment 2 are perspective plan views showing the front surface side and the back surface side of the printed wiring board according to Embodiment 2 of the present invention in an overlapping manner.
  • the printed wiring board in the present embodiment is obtained by changing the arrangement of the first through hole 31, the second through hole 32, the third through hole 33, and the bypass capacitor 2.
  • Other configurations are the same as those in the first embodiment. The same. Hereinafter, the description of the same structure as in the first embodiment will not be repeated.
  • the first through hole 31 is arranged outside the first power supply wiring 5.
  • the first power supply wiring 5 overlaps the current loop between the semiconductor element 1 and the bypass capacitor 2, the effect of noise suppression is reduced.
  • the first power supply wiring 5 can be accommodated between the first through hole 31 and the second through hole 32, the circuit area on the back surface side can be reduced.
  • the first through hole 31 and the second through hole 32 are disposed on both sides of the bypass capacitor 2 in the short direction.
  • the bypass capacitor 2 and the second through hole 32 can be arranged close to the semiconductor element 1, the current loop between the semiconductor element 1 and the bypass capacitor 2 can be reduced. Further, since the mounting region 3 on the front surface side can be reduced, the printed wiring board can be reduced in size.
  • the first through hole 31 and the second through hole 32 are arranged on both sides of the bypass capacitor 2 in the longitudinal direction.
  • the first power supply wiring 5 can be arranged close to the semiconductor element 1, the circuit area on the back surface side and the mounting region 3 on the front surface side can be reduced, and the printed wiring board can be further miniaturized. Can do.
  • the GND pin 12 of the semiconductor element 1 is provided on the same side as the power supply pin 11 or on another upper side and lower side. Is assumed. Even in such a case, the third through hole 33 is disposed in the in-plane position between the second through hole 32 and the GND pin 12, so that the GND pin 12 and the bypass capacitor 2 of the semiconductor element 1 are arranged.
  • the path of the GND current 41 flowing between the second terminal 22 is the shortest path without bypassing the first power supply wiring 5. For this reason, the current loop between the semiconductor element 1 and the bypass capacitor 2 can be minimized, and radiation noise can be suppressed.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

Une première borne (21) d'un condensateur de dérivation (2) est connectée à une broche d'alimentation électrique (11) d'un élément à semi-conducteur (1) et, via un premier trou traversant (31), à un premier câble d'alimentation électrique (5). Une seconde borne (22) du condensateur de dérivation (2) est connectée à un second trou traversant (32). Une broche de mise à la terre (12) de l'élément à semi-conducteur (1) est connectée d'un premier câble de mise à la terre (14) à un motif de mise à la terre (4) via un troisième trou traversant (33). Le courant circulant entre la broche de mise à la terre (12) et le second trou traversant (32) est formé de manière à ne pas croiser le premier câble d'alimentation électrique (5) en formant le second trou traversant (32) entre le premier câble d'alimentation électrique (5) et l'élément à semi-conducteur (1). Du fait de cette structure, un CI et un condensateur de dérivation peuvent être montés sur la même surface de la carte de câblage, et le bruit électromagnétique peut être réduit sans utiliser de carte de câblage multicouches ayant une structure complexe.
PCT/JP2012/062122 2011-05-12 2012-05-11 Carte de câblage imprimé WO2012153835A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011106852A JP2012238724A (ja) 2011-05-12 2011-05-12 プリント配線基板
JP2011-106852 2011-05-12

Publications (1)

Publication Number Publication Date
WO2012153835A1 true WO2012153835A1 (fr) 2012-11-15

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ID=47139309

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/062122 WO2012153835A1 (fr) 2011-05-12 2012-05-11 Carte de câblage imprimé

Country Status (2)

Country Link
JP (1) JP2012238724A (fr)
WO (1) WO2012153835A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531552A (zh) * 2013-10-25 2014-01-22 深圳市华星光电技术有限公司 芯片结构及电路结构

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108463048B (zh) * 2017-02-21 2022-04-15 拉碧斯半导体株式会社 基板电路装置
JP2024179161A (ja) * 2023-06-14 2024-12-26 キヤノン株式会社 露光ヘッド
JP2024179160A (ja) * 2023-06-14 2024-12-26 キヤノン株式会社 画像形成装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0954788A (ja) * 1995-08-11 1997-02-25 Canon Inc 印刷回路基板の設計方法、印刷回路基板及び印刷回路基板を備える電子機器
JP2000091785A (ja) * 1998-09-14 2000-03-31 Yaskawa Electric Corp 電子回路部品の電源パターン接続構造
WO2006112010A1 (fr) * 2005-04-13 2006-10-26 Renesas Technology Corp. Dispositif electronique
JP2009224735A (ja) * 2008-03-19 2009-10-01 Nec Infrontia Corp 多層プリント配線板及びそれを用いた電子機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0954788A (ja) * 1995-08-11 1997-02-25 Canon Inc 印刷回路基板の設計方法、印刷回路基板及び印刷回路基板を備える電子機器
JP2000091785A (ja) * 1998-09-14 2000-03-31 Yaskawa Electric Corp 電子回路部品の電源パターン接続構造
WO2006112010A1 (fr) * 2005-04-13 2006-10-26 Renesas Technology Corp. Dispositif electronique
JP2009224735A (ja) * 2008-03-19 2009-10-01 Nec Infrontia Corp 多層プリント配線板及びそれを用いた電子機器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531552A (zh) * 2013-10-25 2014-01-22 深圳市华星光电技术有限公司 芯片结构及电路结构
US9345124B2 (en) 2013-10-25 2016-05-17 Shenzhen China Star Optoelectronics Technology Co., Ltd. Chip and circuit structure

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