[go: up one dir, main page]

WO2013018126A1 - Transistor à couches minces et son procédé de fabrication - Google Patents

Transistor à couches minces et son procédé de fabrication Download PDF

Info

Publication number
WO2013018126A1
WO2013018126A1 PCT/JP2011/004353 JP2011004353W WO2013018126A1 WO 2013018126 A1 WO2013018126 A1 WO 2013018126A1 JP 2011004353 W JP2011004353 W JP 2011004353W WO 2013018126 A1 WO2013018126 A1 WO 2013018126A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
silicon layer
film transistor
thin film
amorphous silicon
Prior art date
Application number
PCT/JP2011/004353
Other languages
English (en)
Japanese (ja)
Inventor
宏 林
孝啓 川島
玄士朗 河内
Original Assignee
パナソニック株式会社
パナソニック液晶ディスプレイ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社, パナソニック液晶ディスプレイ株式会社 filed Critical パナソニック株式会社
Priority to PCT/JP2011/004353 priority Critical patent/WO2013018126A1/fr
Publication of WO2013018126A1 publication Critical patent/WO2013018126A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0229—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials characterised by control of the annealing or irradiation parameters

Definitions

  • the present invention relates to a thin film transistor, a method for manufacturing the same, and a display device.
  • organic EL displays using organic electroluminescence (EL) as one of the next generation flat panel displays that replace liquid crystal displays have attracted attention.
  • an organic EL display is a current-driven device, and development of a thin film transistor (thin film semiconductor device) having excellent on / off characteristics as a drive circuit for an active matrix display device is urgently required. Yes.
  • a thin film transistor in which a crystalline silicon layer is formed on a gate insulating layer and an amorphous silicon layer is formed on both sides of the crystalline silicon layer is disclosed as a thin film transistor that realizes excellent on and off characteristics (patent) Reference 1).
  • a thin film transistor that realizes excellent on and off characteristics (patent) Reference 1).
  • laser light is irradiated to amorphous silicon from an opening between a source electrode and a drain electrode. Thereby, only the amorphous silicon in the central region of the channel layer exposed at the opening can be formed as crystalline silicon.
  • amorphous silicon The mobility of amorphous silicon is about 1 cm 2 / Vs, whereas the mobility of crystalline silicon is as large as about 100 cm 2 / Vs, so that the on-state current can be increased by forming crystalline silicon.
  • an amorphous silicon layer is formed on both sides of the crystalline silicon layer.
  • amorphous silicon has a large band gap, and has a large energy barrier necessary for heat generation of electrons and holes and a potential barrier in which a tunnel effect occurs. Therefore, by forming an amorphous silicon layer on both sides of the crystalline silicon layer, generation of heat generation current and tunnel leakage current can be prevented, and off current can be reduced.
  • the crystalline silicon that increases the on-current and the amorphous silicon that decreases the off-current as the channel layer excellent on-characteristics and off-characteristics can be realized.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a thin film transistor capable of achieving both excellent on characteristics and excellent off characteristics, a method for manufacturing the same, and a display device. .
  • the thin film transistor of the present invention includes a substrate, a gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode, and the gate insulating layer.
  • a first silicon layer formed above the gate electrode; a second silicon layer formed on both sides of the first silicon layer on the gate insulating layer; and above one of the second silicon layers.
  • the first silicon layer is a crystalline silicon layer
  • the second silicon layer is a crystalline silicon layer having an average grain size smaller than the average grain size of crystals contained in the first silicon layer. And wherein the or a non-crystalline silicon layer.
  • the present invention it is possible to provide a thin film transistor, a method for manufacturing the same, and a display device capable of achieving both excellent on characteristics and excellent off characteristics.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view schematically showing the configuration of each step in the method for manufacturing a thin film transistor according to the first embodiment of the present invention.
  • FIG. 3 is a diagram illustrating a change in current-voltage characteristics of the thin film transistor when the crystallinity of the channel layer is changed.
  • FIG. 4A is a diagram showing a change in crystallinity of the crystalline silicon layer when the laser light absorptance of the amorphous silicon layer and the scan speed of the laser light are changed in laser annealing.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view schematically showing the configuration of each step in the method for manufacturing a thin film transistor according to the first embodiment of the present invention.
  • FIG. 3 is
  • FIG. 4B is a diagram for explaining a method of calculating the light absorption rate into the amorphous silicon layer.
  • FIG. 5A is a contour diagram showing the calculation result of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing.
  • FIG. 5B is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. .
  • FIG. 5A is a contour diagram showing the calculation result of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing.
  • FIG. 5C is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing.
  • FIG. 5D is a contour diagram showing calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing.
  • FIG. 5E is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. .
  • FIG. 5C is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing.
  • FIG. 5D is a contour diagram
  • FIG. 5F is a contour diagram showing calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing.
  • FIG. 6A shows a value obtained by dividing the optical film thickness of the gate insulating layer, which is a value obtained by adding the refractive index of the gate insulating layer to the film thickness of the gate insulating layer in laser annealing, by dividing the wavelength of the laser beam by 0.330 (wavelength It is a figure which shows the change of the absorptivity of an amorphous silicon layer when it is set as a silicon oxide layer film thickness corresponding to 120 nm at 532 nm.
  • FIG. 6A shows a value obtained by dividing the optical film thickness of the gate insulating layer, which is a value obtained by adding the refractive index of the gate insulating layer to the film thickness of the gate insulating layer in laser annealing, by
  • FIG. 6B is a diagram showing an example of a value obtained by converting the value on the horizontal axis of FIGS. 5A to 5F into the film thickness of the amorphous silicon layer.
  • FIG. 6C is a diagram illustrating an example of a value obtained by converting the value on the vertical axis in FIGS. 5A to 5F into the film thickness of the silicon oxide layer or the silicon nitride layer.
  • FIG. 7 shows the calculation of the absorptance of the amorphous silicon layer on which the crystallization control layer is formed when the thickness of the crystallization control layer and the thickness of the gate insulating layer are changed in laser annealing. It is a contour map which shows a result.
  • FIG. 8A is a diagram showing a change in the absorptance of the amorphous silicon layer on which the crystallization control layer is formed when the thickness of the crystallization control layer is changed.
  • FIG. 8B is a diagram showing a change in the absorptance of the amorphous silicon layer on which the crystallization control layer is formed when the film thickness of the crystallization control layer is changed.
  • FIG. 8C is a diagram showing a change in the absorptance of the amorphous silicon layer in which the crystallization control layer is formed when the film thickness of the crystallization control layer is changed.
  • FIG. 9 is a cross-sectional view schematically showing the configuration of the thin film transistor according to the second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view schematically showing the configuration of the thin film transistor according to the second embodiment of the present invention.
  • FIG. 10 is a cross-sectional view schematically showing the configuration of each step in the method for manufacturing a thin film transistor according to the second embodiment of the present invention.
  • FIG. 11 is a cross-sectional view schematically showing a configuration of a thin film transistor according to Modification 1 of the first and second embodiments of the present invention.
  • FIG. 12 is a diagram showing a change in crystallinity of the crystalline silicon layer when the laser light absorption rate of the amorphous silicon layer and the scan speed of the laser light are changed in laser annealing.
  • FIG. 13A is a contour diagram showing the calculation results of the absorptivity of the amorphous silicon layer when the thickness of the amorphous silicon layer and the thickness of the gate insulating layer are changed in laser annealing. .
  • FIG. 13B is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120.
  • FIG. 13C is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120.
  • FIG. 13D is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120.
  • FIG. 13C is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIG. 13A into the thicknesses of the silicon oxide layer and the silicon nitride layer included in the gate insulating layer 120.
  • FIG. 13D is
  • FIG. 14 is a cross-sectional view schematically showing a configuration of a thin film transistor according to Modification 2 of the first and second embodiments of the present invention.
  • FIG. 15 is a cross-sectional view schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to the second modification of the first and second embodiments of the present invention.
  • FIG. 16 is a cross-sectional view schematically showing a configuration of a thin film transistor according to Modification 2 of the first and second embodiments of the present invention.
  • FIG. 17 is a cross-sectional view schematically showing a configuration of a thin film transistor according to Modification 3 of the first and second embodiments of the present invention.
  • FIG. 18 is a cross-sectional view schematically showing the configuration of each step in the method for manufacturing a thin film transistor according to the third modification of the first and second embodiments of the present invention.
  • FIG. 19 is a cross-sectional view schematically showing a configuration of a thin film transistor according to a comparative example of the first and second embodiments of the present invention.
  • FIG. 20 is an external view of a display device according to the third embodiment of the present invention.
  • FIG. 21 is a partially cutaway perspective view of an organic EL panel according to the third embodiment of the present invention.
  • FIG. 22 is a diagram showing a circuit configuration of a pixel of an organic EL panel according to the third embodiment of the present invention.
  • FIG. 23A is a top view showing a state of laser light irradiation according to the embodiment of the present invention.
  • FIG. 23B is a cross-sectional view showing the rise of the amorphous silicon layer according to the embodiment of the present invention.
  • FIG. 23C is a diagram showing a change in the bulge amount of the amorphous silicon layer with respect to the input energy of the laser beam according to the embodiment of the present invention.
  • a thin film transistor includes a substrate, a gate electrode formed over the substrate, a gate insulating layer formed over the gate electrode, and the gate insulating layer.
  • a first silicon layer formed above the gate electrode; a second silicon layer formed on both sides of the first silicon layer on the gate insulating layer; and the second silicon layer.
  • the first silicon layer is a crystalline silicon layer
  • the second silicon layer is a crystal having an average grain size smaller than an average grain size of crystals contained in the first silicon layer. And wherein the silicon layer, or amorphous silicon layer.
  • the first silicon layer may be a crystalline silicon layer including a crystal having an average crystal grain size of 10 nm to 1 ⁇ m.
  • the first silicon layer is a crystalline silicon layer containing crystals having an average grain size of 40 nm or more and 1 ⁇ m or less
  • the second silicon layer is crystalline silicon containing crystals having an average grain size of 10 nm or more and less than 40 nm. It may be a layer.
  • end portions of the source electrode and the drain electrode facing each other may be formed above the first silicon layer, and the end portions of the source electrode and the drain electrode facing each other are formed on the second silicon layer. It may be formed above.
  • both the first silicon layer and the second silicon layer are formed by irradiating the amorphous silicon layer with laser light, the distance between the electrodes defined by the openings of the source electrode and the drain electrode is larger.
  • a crystalline silicon layer can be formed with a large width.
  • the horizontal resistance component of the channel layer can be reduced, and the on-characteristic can be remarkably improved.
  • the film thickness from the bottom surface of the channel layer to the top surface of both sides of the convex portion of the channel layer is smaller than the film thickness from the bottom surface of the channel layer to the top surface of the convex portion.
  • the resistance component in the vertical direction of the channel layer due to the amorphous silicon layer is reduced.
  • the crystalline silicon layer is formed with a width larger than the electrode interval defined by the openings of the source electrode and the drain electrode, and the horizontal resistance component of the channel layer and the vertical resistance due to the amorphous silicon layer are formed. Since the components are reduced, the on-characteristic can be remarkably improved.
  • both sides of the crystalline silicon layer of the channel layer are made of a crystalline silicon layer or an amorphous silicon layer having a small average particle diameter, the channel is less crystalline than when the channel is made entirely of a crystalline silicon layer, and the band The amount of amorphous silicon having a large gap increases. Therefore, the heat generation current and the tunnel current can be greatly suppressed, and the off characteristics can be greatly reduced.
  • the crystallinity of each of the first silicon layer at the center of the channel layer and the second silicon layers on both sides of the channel layer is set such that importance is placed on on-current or off-current. Can be made according to the design.
  • the thin film transistor manufacturing method includes a first step of preparing a substrate, a second step of forming a gate electrode over the substrate, and a gate insulating layer formed over the gate electrode. 3 steps, a fourth step of forming an amorphous silicon layer on the gate insulating layer, a fifth step of forming a light-transmissive crystallization control layer on the amorphous silicon layer, and the crystallization A sixth step of patterning the control layer so as to leave a region above the gate electrode; the crystallization control layer patterned with laser light; and the non-crystalline silicon layer on which the crystallization control layer is not formed The non-crystalline silicon layer on which the patterned crystallization control layer is formed as a first silicon layer, and the second silicon layer on which the crystallization control layer is not formed, A seventh step, an eighth step of removing the patterned crystallization control layer, a source electrode formed on one side of the second silicon layer, and a drain electrode on the other side of the second silicon layer.
  • the crystallization control layer may be an absorptance increasing layer that increases the absorptance with respect to the laser beam of a portion of the amorphous silicon layer where the crystallization control layer is formed.
  • the first silicon layer may be a crystalline silicon layer containing crystals having an average particle diameter of 10 nm to 1 ⁇ m.
  • the first silicon layer is a crystalline silicon layer including crystals having an average crystal grain size of 40 nm or more and 1 ⁇ m or less, and the second silicon layer has an average crystal grain size of 10 nm or more and less than 40 nm. It may be a crystalline silicon layer containing crystals.
  • the portion where the crystallization control layer is formed in the first silicon layer that is, the non-crystalline silicon layer that forms the channel layer with high crystallinity, but also the second silicon layer, that is, the channel layer with low crystallinity.
  • the portion of the non-crystalline silicon layer forming the crystallization control layer is also irradiated with a laser. Therefore, if the intensity of the laser beam and the film thickness are appropriately selected, there is a degree of freedom in forming a low crystalline channel layer up to a crystalline silicon layer having a small average crystal grain size.
  • the second silicon layer since the second silicon layer has a higher resistance than the first silicon layer, the off characteristics can be reduced as compared with the case where the entire region of the channel layer is the first silicon layer. Further, since the first silicon layer has a smaller resistance than the second silicon layer, the transverse resistance can be lowered and the on-current can be increased as compared with the case where the entire region of the channel layer is the second silicon layer. Therefore, the first silicon layer and the second silicon layer in the channel layer can be separately formed according to the desired thin film transistor design, such as emphasizing on-current or emphasizing off-current. As a result, both excellent on characteristics and off characteristics can be achieved.
  • the wavelength of the laser beam may be not less than 473 nm and not more than 561 nm.
  • the interference effect of laser light can be easily generated inside the crystallization control layer, the amorphous silicon layer, and the gate insulating layer, and the portion of the channel layer where the crystallization control layer is formed; It is possible to easily cause a difference in the absorption rate of the laser light between the portions on both sides.
  • the laser light absorption rate of the non-crystalline silicon layer in which the crystallization control layer is formed, and the non-crystalline silicon layer in which the crystallization control layer is not formed The difference from the absorption rate with respect to the laser beam may be 7% or more.
  • the portion of the channel layer where the crystallization control layer is formed can be a polycrystalline silicon layer, and the portion of the channel layer where the crystallization control layer is not formed can be a microcrystalline silicon layer.
  • the laser light absorption rate of the non-crystalline silicon layer in which the crystallization control layer is formed, and the non-crystalline silicon layer in which the crystallization control layer is not formed The difference from the absorption rate with respect to the laser light may be 1% or more.
  • the portion of the channel layer where the crystallization control layer is formed is a polycrystalline silicon layer, and the portion of the channel layer where the crystallization control layer is not formed is an amorphous silicon layer or a microcrystalline silicon layer. It can also be.
  • l and m are integers starting from 0, and the amorphous silicon in which the crystallization control layer is formed from the bottom surface of the amorphous silicon layer in which the crystallization control layer is formed
  • a value obtained by dividing the optical film thickness of the amorphous silicon layer which is a value obtained by integrating the refractive index of the amorphous silicon layer with the film thickness up to the upper surface of the layer, divided by the wavelength of the laser beam is X
  • the gate The value obtained by dividing the optical film thickness of the gate insulating layer by the refractive index of the gate insulating layer to the film thickness of the insulating layer divided by the wavelength of the laser beam is Y, and X and Y are as follows: (Equation 1) and (Equation 2) may be satisfied.
  • the absorption rate of the laser beam in the portion where the crystallization control layer of amorphous silicon is formed can include the maximum absorption rate, for example, 50% or more.
  • the gate insulating layer composed of a silicon nitride layer and a silicon oxide layer formed on the silicon nitride layer may be formed.
  • the gate insulating layer includes a capacitance of a series capacitor formed by the silicon nitride layer and the silicon oxide layer, and a capacitance of a single silicon oxide layer having a thickness of 100 nm to 140 nm. May be formed in such a film thickness that becomes equal to each other.
  • the gate insulating layer has a two-layer structure, and the absorptivity of the amorphous silicon laser light can be increased.
  • the average grain size of the crystal in the portion where the crystallization control layer of the channel layer is formed can be increased, and the on-current can be increased.
  • n is an integer starting from 0, and the non-crystalline silicon layer in which the crystallization control layer is formed from the bottom surface of the non-crystalline silicon layer in which the crystallization control layer is formed.
  • a value obtained by dividing the optical film thickness of the amorphous silicon layer which is a value obtained by integrating the refractive index of the amorphous silicon layer with the film thickness up to the upper surface, divided by the wavelength of the laser beam is X
  • a value obtained by dividing the optical film thickness obtained by converting the gate insulating layer composed of the silicon oxide layer by the refractive index of the silicon oxide layer by the value obtained by integrating the refractive index of the silicon oxide layer and the wavelength of the laser light is Y
  • X and Y may satisfy the following (formula 3) and (formula 4), or (formula 5) and (formula 6).
  • the absorption rate of the laser beam in the portion where the crystallization control layer of amorphous silicon is formed includes the maximum absorption rate, for example, 50 % Or more.
  • the optical thickness of the crystallization control layer which is a value obtained by integrating the refractive index of the crystallization control layer to the thickness of the crystallization control layer, is divided by the wavelength of the laser beam.
  • the value may be Z, k may be an integer starting from 0, and the Z may satisfy (Equation 7) below.
  • the crystallization control layer functions as an antireflection film for laser light, and can increase the laser light absorption rate of amorphous silicon.
  • the degree of increase in the absorptance periodically varies with the film thickness of the crystallization control layer, but the range in which the absorptance particularly increases is expressed by (Equation 7) using the optical film thickness of the crystallization control layer. . Therefore, by forming the crystallization control layer satisfying (Equation 7), it is possible to increase the absorption efficiency of the laser beam in the portion of the channel layer where the crystallization control layer is formed.
  • the amorphous silicon layer may be formed so that the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer is 100 nm or less.
  • the laser light passes through the amorphous silicon layer in the thickness direction and attenuates until reaching the position directly above the gate insulating layer serving as a current path.
  • the film thickness of the amorphous silicon layer is set to 100 nm or less, the laser light penetrates deeply into the amorphous silicon layer and crystallizes to the amorphous silicon layer directly above the gate insulating layer serving as a current path. be able to. Thereby, the subthreshold swing characteristic of the thin film transistor can be improved.
  • the amorphous silicon layer may be formed so that the film thickness from the bottom surface of the amorphous silicon layer to the top surface of the amorphous silicon layer is 10 nm or more.
  • the amorphous silicon layer When the amorphous silicon layer is extremely thin, the absorption rate of the laser beam by the amorphous silicon layer is low. Therefore, most of the energy of the laser beam transmitted through the amorphous silicon layer is input to the gate electrode, and the gate The electrode will be damaged. However, by setting the thickness of the amorphous silicon layer to 10 nm or more, damage to the gate electrode due to excessive laser light can be prevented.
  • the substrate having an undercoat layer formed on the surface may be prepared, and in the second step, the gate electrode may be formed on the undercoat layer.
  • the intrusion of impurities contained in the substrate into the channel layer can be suppressed.
  • a metal film made of a refractory metal containing Mo or MoW or an alloy of the refractory metal may be formed as the gate electrode.
  • a film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam may be formed as the gate insulating layer.
  • the light absorption of the laser light by the gate insulating layer can be suppressed, and the absorption rate of the amorphous silicon laser light can be increased.
  • a silicon oxide layer may be formed as the gate insulating layer.
  • a silicon nitride layer may be formed as the gate insulating layer.
  • a film having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam may be formed as the crystallization control layer.
  • a silicon oxide layer may be formed as a crystallization control layer.
  • a silicon nitride layer may be formed as a crystallization control layer.
  • the laser light may be light in a continuous oscillation mode or a pseudo continuous oscillation mode.
  • the laser light may be light emitted from a solid-state laser device.
  • the laser light may be light emitted from a laser device using a semiconductor laser element.
  • the fluctuation of the irradiation energy density of the laser light on the amorphous silicon layer may be less than 5%.
  • the non-crystalline silicon layer on which the crystallization control layer is formed and the non-crystalline silicon layer on which the crystallization control layer is not formed at a constant scan speed with laser light May be continuously irradiated.
  • a display device is a display device including a liquid crystal panel or an organic EL panel, and includes the thin film transistor.
  • the thin film transistor includes the liquid crystal panel when the display device includes the liquid crystal panel.
  • the organic EL panel is driven when the display device includes the organic EL panel.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a thin film transistor according to the present embodiment.
  • This thin film transistor is a channel etch type bottom gate thin film transistor for a display device, and includes a substrate 100, a gate electrode 110 formed on the substrate 100, a gate insulating layer 120 formed on the gate electrode 110, A crystalline silicon layer 131 as a first silicon layer formed on the gate insulating layer 120 and above the gate electrode 110; and on both sides of the crystalline silicon layer 131 on the gate insulating layer 120.
  • a non-crystalline silicon layer (amorphous silicon) 130 as a second silicon layer, a source electrode 171 formed above one of the non-crystalline silicon layers 130, and a non-crystalline silicon layer 130 are formed above the other.
  • the drain electrode 172 is formed, and the crystalline silicon layer 131 and the amorphous silicon layer 130 are non-bonded.
  • a contact layer 162 formed between the amorphous silicon layer 130 and the source electrode 171 and a contact layer 161 formed between the amorphous silicon layer 130 and the drain electrode 172 are provided.
  • the substrate 100 is a glass substrate made of a glass material such as quartz glass, non-alkali glass, and high heat resistance glass. Note that in order to prevent impurities such as sodium and phosphorus contained in the glass substrate from entering the crystalline silicon layer 131 and the amorphous silicon layer 130, silicon nitride (SiNx), silicon oxide (SiOy) is formed on the surface. Or a substrate on which an undercoat layer made of silicon oxynitride film (SiOyNx) or the like is formed. In addition, the undercoat layer may play a role of reducing the influence of heat on the substrate 100 in a high-temperature heat treatment process such as laser annealing. The thickness of the undercoat layer is, for example, about 100 nm to 2000 nm.
  • the gate electrode 110 has a single layer structure or a multilayer structure such as a conductive material that can withstand the melting point temperature of silicon or an alloy thereof.
  • a conductive material that can withstand the melting point temperature of silicon or an alloy thereof.
  • molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W) , Ta (tantalum), Nb (niobium), Ni (nickel), titanium (Ti), chromium (Cr), molybdenum tungsten (MoW), etc. are formed on the substrate 100 and patterned into a predetermined shape. It is formed.
  • the thickness of the gate electrode 110 is preferably 30 nm to 300 nm, more preferably 50 nm to 100 nm.
  • the thickness of the gate electrode 110 is small, the transmittance of the gate electrode 110 increases, and the reflection of the laser beam is likely to decrease.
  • the thickness of the gate electrode 110 is large, the coverage of the gate insulating layer 120 is lowered, and in particular, the characteristics of the thin film transistor are deteriorated such that the gate insulating layer 120 is disconnected at the end of the gate electrode 110. This is because it becomes easier.
  • the crystalline silicon layer 131 and the amorphous silicon layer 130 are semiconductor layers formed on the gate insulating layer 120 and constitute a channel layer whose carrier movement is controlled by the voltage of the gate electrode 110.
  • the crystalline silicon layer 131 is formed of a crystalline silicon layer such as a polycrystalline silicon layer, and is made polycrystalline by irradiating a part of amorphous silicon of the amorphous silicon layer 130 with a laser. Formed).
  • the crystalline silicon layer 131 can be a silicon layer having a mixed crystal structure of amorphous silicon and a crystalline silicon layer.
  • the average particle diameter of crystals contained in the crystalline silicon layer 131 is 10 nm or more and 1 ⁇ m or less.
  • the channel layer has a convex part and a flat part on the surface.
  • the film thickness (film thickness of the flat portion) from the bottom surface of the channel layer (the bottom surfaces of the crystalline silicon layer 131 and the amorphous silicon layer 130) to the surface of the flat portion (the upper surface of the amorphous silicon layer 130). Is thinner than the film thickness (film thickness of the convex portion) from the bottom surface of the channel layer to the upper surface of the convex portion (the upper surface of the crystalline silicon layer 131).
  • the convex portion of the channel layer is located above the gate electrode 110, and both ends thereof are located inside the both ends of the gate electrode 110. That is, the gate length (channel length) of the gate electrode 110 is longer than the length of the channel layer in the gate length direction.
  • both sides of the convex portion of the channel layer, that is, the flat portion of the channel layer serve as a charge transfer path.
  • the gate insulating layer 120 is made of, for example, silicon oxide, silicon nitride, silicon oxynitride film, aluminum oxide (AlOz), tantalum oxide (TaOw), or a laminated film thereof, and covers the gate electrode 110 on the substrate 100 so as to cover it. It is formed on the substrate 100 and the gate electrode 110.
  • the gate insulating layer 120 is preferably formed of silicon oxide. This is because it is preferable to make the interface state between the channel layer and the gate insulating layer 120 good in order to maintain good threshold voltage characteristics in the TFT.
  • the pair of contact layers 161 and 162 is made of an amorphous semiconductor layer containing impurities at a high concentration or a polycrystalline semiconductor layer containing impurities at a high concentration, and is formed in contact with the channel layer. Further, the pair of contact layers 161 and 162 are arranged to face each other with a predetermined interval on the channel layer.
  • Each of the pair of contact layers 161 and 162 is separately provided on both sides of the convex portion (crystalline silicon layer 131) of the channel layer, and the upper surface and the side surface of the end portion (end portion in the width direction) of the convex portion of the channel layer. , As well as on the upper surface of the flat portion of the channel layer extending from the side surface of the convex portion of the channel layer.
  • the pair of contact layers 161 and 162 is, for example, an n-type semiconductor layer in which amorphous silicon is doped with phosphorus (P) as an impurity, and a high-concentration impurity of 1 ⁇ 10 19 [atm / cm 3 ] or more is formed. Including n + layer.
  • Each of the contact layers 161 and 162 can have a film thickness of, for example, 5 nm to 100 nm.
  • the pair of source electrode 171 and drain electrode 172 are formed along the upper surface and side surface of the end portion of the convex portion of the channel layer and the upper surface of the flat portion of the channel layer formed on the side surface of the convex portion of the channel layer. In addition, the pair of source electrode 171 and drain electrode 172 are provided to be separated from each other.
  • the pair of source electrode 171 and drain electrode 172 is formed above the channel layer, and is formed on the corresponding contact layer 161 or 162, respectively. That is, the source electrode 171 is formed on the pair of contact layers 162, and the drain electrode 172 is formed on the contact layer 161.
  • the source electrode 171 and the drain electrode 172 can each have a single layer structure or a multilayer structure made of a conductive material or an alloy thereof, for example, aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), silver (Ag), copper (Cu), titanium (Ti), or chromium (Cr). Further, the source electrode 171 and the drain electrode 172 can have a three-layer structure of MoW / Al / MoW. The film thickness of the source electrode 171 and the drain electrode 172 is, for example, about 100 nm to 500 nm.
  • FIG. 2 is a cross-sectional view schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to the present embodiment.
  • the thin film transistor manufacturing method includes a first step of preparing the substrate 100, a second step of forming the gate electrode 110 on the substrate 100, a third step of forming the gate insulating layer 120 on the gate electrode 110, a gate
  • the fourth step of forming the amorphous silicon layer 130 on the insulating layer 120, the fifth step of forming the crystallization control layer 140 on the amorphous silicon layer 130, and the crystallization control layer 140 are combined with the gate electrode 110.
  • a sixth step of patterning so as to leave a region above the substrate, and laser light is continuously irradiated to the patterned crystallization control layer 140 and the amorphous silicon layer 130 on which the crystallization control layer 140 is not formed.
  • the amorphous silicon layer 130 on which the patterned crystallization control layer 140 is formed is used as the crystalline silicon layer 131, and the crystallization control layer 140 is formed.
  • the crystallization control layer 140 is an absorptance increasing layer that increases the absorptance of the portion of the amorphous silicon layer 130 where the crystallization control layer 140 is formed with respect to laser light.
  • the absorption rate of the amorphous silicon layer 130 with respect to the laser beam is the absorption of the convex portion of the amorphous silicon layer 130 and the portion below the convex portion corresponding to the lower portion of the crystallization control layer 140.
  • the rate is larger than the absorption rate of the portions on both sides of the convex portion of the amorphous silicon layer 130.
  • a glass substrate is prepared as a substrate 100 as shown in FIG.
  • an undercoat layer made of a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like may be formed on the surface of the substrate 100 by plasma CVD (Chemical Vapor Deposition) or the like.
  • the undercoat layer is preferably a silicon oxide film (SiOy) of 1.5 ⁇ y ⁇ 2.0, and has a thickness of 300 nm to 1500 nm.
  • a more preferable thickness range of the undercoat layer is 500 nm or more and 1000 nm or less. This is because if the thickness of the undercoat layer is increased, the thermal load on the substrate 100 can be reduced, but if it is too thick, film peeling or cracking occurs.
  • a gate electrode 110 having a predetermined shape is formed on the substrate 100.
  • a gate metal film made of a refractory metal containing Mo or MoW or an alloy of the refractory metal is formed on the substrate 100 by sputtering as the gate electrode 110, and the gate metal film is formed using a photolithography method and a wet etching method.
  • the gate electrode 110 having a predetermined shape can be formed by patterning. MoW wet etching can be performed using, for example, a chemical solution in which phosphoric acid (HPO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH) and water are mixed in a predetermined composition.
  • HPO 4 phosphoric acid
  • HNO 3 nitric acid
  • CH 3 COOH acetic acid
  • a gate insulating layer 120 is formed on the substrate 100 and the gate electrode 110 so as to cover the gate electrode 110.
  • a silicon oxide layer or a silicon nitride layer is formed as the gate insulating layer 120 over the gate electrode 110 by a plasma CVD method.
  • an amorphous silicon layer 130 made of amorphous silicon is continuously formed on the gate insulating layer 120 by plasma CVD or the like. To do.
  • a crystallization control layer 140 is formed on the amorphous silicon layer 130 by plasma CVD or the like.
  • the crystallization control layer 140 is an inorganic material layer having an insulating material such as silicon oxide or silicon nitride as a main component.
  • a part of the amorphous silicon layer 130 and the crystallization control layer 140 are continuously removed by etching. This removal is performed even after the crystallization control layer 140 is removed and the amorphous silicon layer 130 is exposed on the surface. Therefore, a convex part and a flat part are formed in the amorphous silicon layer 130, and the crystallization control layer 140 remains on the convex part.
  • etching of the amorphous silicon layer 130 and the crystallization control layer 140 is performed continuously, that is, a convex portion is formed by self-alignment, the side surface of the underlying amorphous silicon layer 130 (the convex portion of the channel layer) ) And the side surface of the upper crystallization control layer 140 are formed to be convex.
  • the amorphous silicon layer 130 is made into a crystalline silicon layer 131 by laser annealing. Specifically, a predetermined laser beam is moved relative to the substrate 100 in a certain direction, and the amorphous silicon layer 130 is crystallized using the laser beam to generate the crystalline silicon layer 131. More specifically, first, the formed amorphous silicon layer 130 is subjected to dehydrogenation treatment (dehydrogenation annealing treatment at a temperature of 400 ° C. or higher, which is a temperature at which hydrogen escapes from the amorphous silicon layer 130). carry out.
  • dehydrogenation treatment dehydrogenation annealing treatment at a temperature of 400 ° C. or higher, which is a temperature at which hydrogen escapes from the amorphous silicon layer 130.
  • the amorphous silicon layer 130 is made polycrystalline (including microcrystals) by laser annealing to form a crystalline silicon layer 131. Since the crystallization control layer 140 is transparent to the laser light used for this laser annealing, the laser light is irradiated to the amorphous silicon layer 130 on which the crystallization control layer 140 is formed in FIG.
  • the laser light is emitted in the order of one flat portion, the convex portion, and the other flat portion of the amorphous silicon layer 130, that is, the portion of the amorphous silicon layer 130 where the crystallization control layer 140 is not formed,
  • the non-crystalline silicon layer 130 is scanned in the order of the portion of the crystalline silicon layer 130 where the crystallization control layer 140 is formed and the portion of the non-crystalline silicon layer 130 where the crystallization control layer 140 is not formed.
  • the absorptivity of the laser beam in the portion where the control layer 140 is not formed is low.
  • the convex portion where the crystallization control layer 140 is formed and the portion below the crystallization are crystallized to form the crystalline silicon layer 131, but the crystallization control layer 140 is formed.
  • the flat portions on both sides of the non-convex portion remain uncrystallized without being crystallized.
  • the convex portion of the amorphous silicon layer 130 and the lower portion thereof are selectively crystallized, and the crystalline silicon layer 131 is selectively formed only on the convex portion of the amorphous silicon layer 130 and the lower portion thereof. Can be formed.
  • the laser light source of the laser light is a laser having a wavelength in the visible light region.
  • the laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and preferably a green laser having a wavelength of 473 nm to 561 nm.
  • the laser light having a wavelength in the visible light region is preferably light in a continuous oscillation mode or a pseudo continuous oscillation mode. This is because when the laser light having a wavelength in the visible light region is in a pulse oscillation mode other than the continuous oscillation mode or the pseudo continuous oscillation mode, the amorphous silicon layer 130 is irradiated with the laser light discontinuously.
  • the amorphous silicon layer 130 cannot always be kept in a molten state.
  • the reason why the quasi-continuous oscillation mode is also included is that the amorphous silicon layer 130 can be maintained in its molten state by applying a pulse and reheating it before it is cooled to below its melting point. Therefore, a preferred mode of the quasi-continuous oscillation mode is one in which the amorphous silicon layer 130 can be reheated by applying a pulse before it is cooled to below its melting point, and the molten state can be maintained.
  • the laser light having a wavelength in the visible light region may be light emitted from a solid-state laser device or light emitted from a laser device using a semiconductor laser element.
  • the laser light can be controlled with high accuracy. Further, the laser light having a wavelength in the visible light region is irradiated on the non-crystalline silicon layer 130 with the laser light when irradiated on the non-crystalline silicon layer 130 in order to form the crystalline silicon layer 131 without crystal unevenness. It is preferable if the fluctuation of the energy density is less than 5%. By forming the crystalline silicon layer 131 having no crystal unevenness, the initial design characteristics of the thin film transistor can be achieved, and the characteristics can be made uniform.
  • the laser light is transmitted through the non-crystalline silicon layer 130 in the thickness direction and attenuated until it reaches the top of the gate insulating layer 120 serving as a current path. End up.
  • the film thickness of the amorphous silicon layer 130 is 100 nm or less, the laser light penetrates deeply into the amorphous silicon layer 130 and the amorphous silicon layer 130 immediately above the gate insulating layer 120 serving as a current path. Can be crystallized.
  • the convex portion is formed so that the film thickness from the bottom surface of the amorphous silicon layer 130 to the top surface of the convex portion of the amorphous silicon layer 130 is 100 nm or less. preferable.
  • the amorphous silicon layer 130 on both sides of the convex portion of the amorphous silicon layer 130 is extremely thin, the absorption rate of the laser light by the amorphous silicon layer 130 is lowered. Therefore, most of the energy of the laser light transmitted through the amorphous silicon layer 130 is input to the gate electrode 110, and the gate electrode 110 is damaged.
  • the thickness of the amorphous silicon layer 130 is set to 10 nm or more, damage to the gate electrode due to excessive laser light can be prevented. Therefore, in the process of FIG. 2F, the protrusions are formed so that the film thickness from the bottom surface of the amorphous silicon layer 130 to the upper surfaces of both sides of the protrusions of the amorphous silicon layer 130 is 10 nm or more. It is preferred that
  • a film such as silicon oxide or silicon nitride having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser light is preferably formed as the gate insulating layer 120.
  • FIG. 2E in order to suppress the laser light from being absorbed by the crystallization control layer 140 and increase the absorption rate of the laser light of the amorphous silicon layer 130, in the step of FIG. 2E, FIG. A film such as silicon oxide or silicon nitride having an extinction coefficient of 0.01 or less with respect to the wavelength of the laser beam is preferably formed as the crystallization control layer 140.
  • the amorphous silicon layer 130 is irradiated with linearly focused laser light.
  • linearly focused laser light There are, for example, two irradiation methods, one of which is a fixed irradiation position of the linearly focused laser light.
  • the laser beam is irradiated while moving relative to the amorphous silicon layer 130.
  • the amorphous silicon layer 130 irradiated with the laser light absorbs the energy of the laser light and rises in temperature to be crystallized to become the crystalline silicon layer 131.
  • the crystallization control layer 140 is removed by wet etching.
  • the crystallization control layer 140 is made of silicon oxide, hydrofluoric acid is used, and when it is made of silicon nitride, phosphoric acid is used as an etching solution.
  • a contact layer 160 to be the contact layers 161 and 162 is formed so as to extend from the upper surface of the convex portion of the amorphous silicon layer 130 to the flat portion.
  • a pentavalent element impurity such as phosphorus is doped by plasma CVD, for example, so as to cover the upper surface and side surfaces of the convex portion of the crystalline silicon layer 131 and the upper surface of the flat portion of the amorphous silicon layer 130.
  • a contact layer 160 made of amorphous silicon is formed.
  • a resist material is applied on the contact layer 160, and exposure and development are performed to form a resist patterned into a predetermined shape. Thereafter, the contact layer 160 and the channel layer (amorphous silicon layer 130) are etched using this resist as a mask, thereby patterning the contact layer 160 and the channel layer into an island shape. Then, as shown in FIG. 2J, a source / drain metal film 170 to be the source electrode 171 and the drain electrode 172 is formed so as to cover the contact layer 160.
  • the source / drain metal film 170 having a three-layer structure of MoW / Al / MoW is formed by sputtering.
  • a resist material is applied onto the source / drain metal film 170, exposed and developed, and then patterned into a predetermined shape. Form. Thereafter, as shown in FIG. 2K, wet etching is performed using this resist as a mask to pattern the source / drain metal film 170, thereby forming a source electrode 171 and a drain electrode 172 having predetermined shapes. At this time, etching stops at the contact layer 160, and the contact layer 160 is exposed.
  • the resist on the source electrode 171 and the drain electrode 172 is removed, and the contact layer 160 is patterned by performing dry etching using the source electrode 171 and the drain electrode 172 as a mask. Thereby, a pair of contact layers 161 and 162 having a predetermined shape can be formed.
  • FIG. 3 is a diagram showing changes in the current-voltage characteristics of the thin film transistor when the crystallinity of the channel layer is changed.
  • FIG. 3 shows the characteristics when a voltage of 12 V is applied between the source and drain, the horizontal axis shows the gate-source voltage, and the vertical axis shows the source-drain current.
  • the channel layer is composed of the amorphous silicon layer 130 and the crystalline silicon layer 131.
  • the channel layer is composed of only the amorphous silicon layer 130 and only the crystalline silicon layer 131.
  • the channel layer exhibits different characteristics when the channel layer is configured. That is, as shown in FIG. 3, when the channel layer is formed of only the amorphous silicon layer 130, the off characteristics are good, but the on characteristics are bad. On the other hand, when the channel layer is composed of only the crystalline silicon layer 131, the off characteristics are poor, but the on characteristics are good.
  • the thin film transistor shown in FIG. 1 achieves both good off-characteristics and on-characteristics by utilizing the change in characteristics due to the difference in crystallinity shown in FIG. That is, while the on-current is increased by using the convex portion of the channel layer and the portion below it as the crystalline silicon layer 131, the off-current (leakage current) is formed by using the non-crystalline silicon layer 130 on both sides of the convex portion of the channel layer. Is reduced.
  • FIG. 4A shows the crystallinity of the crystalline silicon layer 131 when the laser light absorptivity of the amorphous silicon layer 130 and the scan speed of the laser light are changed in the laser annealing in the step of FIG. It is a figure which shows the change of.
  • changing the absorptance of the amorphous silicon layer 130 is realized by changing the thickness of the amorphous silicon layer 130, that is, the thickness of the channel layer.
  • a sample is used in which the laser output is 60 kW / cm 2 , the gate electrode 110 is 50 nm thick MoW, and the gate insulating layer 120 is 120 nm thick silicon oxide.
  • a-Si indicates that the crystalline silicon layer 131 does not crystallize as crystalline silicon but becomes amorphous silicon
  • SPC indicates the average grain size of the crystalline silicon layer 131.
  • Ex & .SPC indicates that the average particle diameter of the crystalline silicon layer 131 is approximately 40 nm or more and less than 60 nm
  • p-Si indicates the crystalline silicon layer.
  • the average particle size of 131 is about 60 nm or more and 1 ⁇ m or less
  • “abration” indicates that the crystalline silicon layer 131 does not function as a channel layer.
  • different crystalline silicon layers can be formed by changing the scanning speed of laser annealing and the absorption rate of the amorphous silicon layer 130. Even in the case where the scanning speed is constant, in the step of FIG. 2 (f), the absorptance to the laser light of the convex part of the amorphous silicon layer 130 on which the crystallization control layer 140 is formed and the part below the convex part. The difference between the absorptivity with respect to the laser light of the portions on both sides of the convex portion of the amorphous silicon layer 130 (the portion where the crystallization control layer 140 of the amorphous silicon layer 130 is not formed) is set to 1% or more.
  • the amorphous silicon layer and the crystalline silicon layer can be simultaneously formed by one laser scan, and the crystalline silicon layer 131 on the convex portion of the channel layer and the amorphous silicon layer 130 on both sides of the convex portion, Can be formed.
  • the absorptance of the amorphous silicon layer 130 is the structure, film thickness, and optical constant of the crystallization control layer 140, the film thickness and optical constant of the amorphous silicon layer 130, the structure, film thickness, and thickness of the gate insulating layer 120. It is derived by optical calculation in consideration of multiple interference of laser light, with the optical constant and the optical constant of the metal material forming the underlying gate electrode 110 as parameters. Hereinafter, examples of optical calculation will be described in detail.
  • FIG. 4B is a diagram for explaining a method for calculating the light absorption rate of the amorphous silicon layer 130.
  • FIG. 4B shows a model structure of a multilayer structure in which the structure of the thin film transistor shown in FIG. 1 is modeled.
  • a layer 401 of the complex refractive index N 1, and 402 of the complex refractive index N 2 a layer 403 of the complex refractive index N 3, a layer 404 of the complex refractive index N 4, the complex index of refraction N 5 substrate 405.
  • a layer 404, a layer 403, a layer 402, and a layer 401 are stacked on the substrate 405 in this order.
  • the region of the complex refractive index N 0 shown in the figure is outside the model structure and indicates the side on which the laser light is incident on the model structure. This region is, for example, air. In this case, the refractive index is 1 and the extinction coefficient is 0.
  • the substrate 405 is an insulating substrate made of, for example, transparent glass or quartz, and has a refractive index of 1.46, for example, and corresponds to the substrate 100 shown in FIG.
  • the layer 404 is made of, for example, 50 nm MoW having a refractive index of 3.47 and an extinction coefficient of 3.78, and corresponds to the gate electrode 110 shown in FIG.
  • the layer 403 is made of, for example, silicon oxide having a refractive index of 1.467 and an extinction coefficient of 0, and corresponds to the gate insulating layer 120 shown in FIG.
  • the layer 402 corresponds to the amorphous silicon layer 130 having a refractive index of 5.074 and an extinction coefficient of 0.621, for example.
  • the layer 401 is made of, for example, silicon oxide having a refractive index of 1.467 and an extinction coefficient of 0, and corresponds to the crystallization control layer 140 shown in FIG.
  • the amplitude reflection coefficient for light incident on the layer 401 from the outside is r 01
  • the amplitude reflection coefficient for light incident on the layer 402 from the layer 401 is r 12
  • R 23 is the amplitude reflection coefficient with respect to the incident light
  • r 34 is the amplitude reflection coefficient with respect to the light incident on the layer 404 from the layer 403.
  • the amplitude transmission coefficient of light incident on the layer 401 from the outside is t 01
  • the amplitude transmission coefficient of light incident on the layer 402 from the layer 401 is t 12
  • the amplitude transmission of light incident on the layer 402 from the layer 402 The coefficient is t 23
  • the amplitude transmission coefficient of light incident on the layer 404 from the layer 403 is t 34 .
  • the amplitude reflection coefficients of the entire layers above the region where the layer 404 corresponding to the gate electrode 110 is formed are r 01234 (R1), r 1234 (R2), and r 234 (R3), respectively.
  • the amplitude reflection coefficient when the layers 404 and 403 are regarded as one layer is r 234 (R3).
  • the amplitude reflection coefficient when the layer 404, the layer 403, and the layer 402 are regarded as one layer is r 1234 (R2)
  • the amplitude when the layer 404, the layer 403, the layer 402, and the layer 401 are regarded as one layer.
  • the reflection coefficient is r 01234 (R1).
  • the amplitude transmission coefficients of the entire layers in the first region are t 01234 (T1), t 1234 (T2), and t 234 (T3), respectively.
  • the amplitude transmission coefficient when the layers 404 and 403 are regarded as one layer is t 234 (T3).
  • t 1234 (T2) is an amplitude transmission coefficient when the layer 404, the layer 403, and the layer 402 are regarded as one layer, and the amplitude when the layer 404, the layer 403, the layer 402, and the layer 401 are regarded as one layer.
  • the transmission coefficient is t 01234 (T1).
  • the amplitude reflection coefficient and amplitude transmission coefficient of each layer in the first region can be expressed by the following (Expression 12) to (Expression 17).
  • the amplitude reflection coefficient and amplitude transmission coefficient of each layer in the second region can be expressed by the following (Equation 18) to (Equation 23).
  • d is the film thickness of each layer
  • ⁇ is the incident angle / transmission angle in each layer
  • ⁇ is the wavelength of the laser beam.
  • ⁇ can be calculated as shown below from Snell's law of the following equation.
  • the amplitude reflection coefficients r 01 , r 12 , r 23 , r 34 , r 35 and the amplitude transmission coefficients t 01 , t 12 , t 12 , t 34 , t 35 of each layer are expressed by the following (formula 24) to (formula). 33).
  • the light is monochromatic laser light, and the polarization is assumed to be P-polarized light.
  • the amplitude reflection coefficient and amplitude transmission coefficient of the entire layer in the first region are calculated as follows. That is, first, r 234 is calculated by substituting (Equation 26) and (Equation 27) into (Equation 14). Next, r 1234 is calculated by substituting (Equation 25) and r 234 into (Equation 13). Next, r 01234 is calculated by substituting (Equation 24) and r 1234 into (Equation 12). Next, t 234 is calculated by substituting (Equation 26), (Equation 27), (Equation 31), and (Equation 32) into (Equation 17).
  • t 1234 is calculated by substituting (Equation 25), (Equation 30), r 234 and t 234 into (Equation 16).
  • t 01234 is calculated by substituting (Equation 24), (Equation 29), r 1234 and t 1234 into (Equation 15).
  • a model structure including a gate electrode 110 made of MoW, a gate insulating layer 120 made of silicon oxide, an amorphous silicon 130, and a crystallization control layer 140 made of silicon oxide is shown.
  • Modification cases such as a case where the insulating film 120 has a laminated structure of silicon oxide and silicon nitride or a case where the crystallization control layer 140 does not exist can be similarly calculated by appropriately modifying the model structure of FIG. 4B.
  • the material of the gate electrode 110 is changed (for example, the material of the gate electrode 110 is Cu (refractive index 1.04, extinction coefficient 2.59), Al (refractive index 0.867, extinction coefficient 6.42), Mo.
  • the material of the gate insulating layer 120 and the crystallization control layer 140 is changed.
  • the material of the gate insulating layer 120 and the crystallization control layer 140 is, for example, silicon nitride (refractive index 1.947, extinction coefficient 0)
  • the same calculation can be performed by appropriately changing the physical property values.
  • FIGS. 5A to 5F show amorphous silicon when the thickness of the amorphous silicon layer 130 and the thickness of the gate insulating layer 120 are changed in the laser annealing in the step of FIG.
  • FIG. 6 is a contour diagram showing the calculation result of the absorptance of the layer 130.
  • 6A is a diagram showing a change in the absorptance of the amorphous silicon layer 130 when the thickness of the gate insulating layer 120 made of silicon oxide is 120 nm in FIGS. 5D and 5F.
  • the lower horizontal axis represents the optical film thickness of the amorphous silicon layer 130, that is, the value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness of the amorphous silicon layer 130. Is divided by the wavelength of the laser beam.
  • the left vertical axis indicates the optical film thickness of the gate insulating layer 120, that is, the value obtained by dividing the refractive index of the gate insulating layer 120 by the film thickness of the gate insulating layer 120 and dividing it by the wavelength of the laser beam.
  • the film thickness of the amorphous silicon layer 130 when the wavelength of the laser light is 532 nm without being normalized by the wavelength of the laser light is shown on the horizontal axis, and the film thickness of the gate insulating layer 120 is shown on the right side. It is shown on the vertical axis.
  • the value obtained by dividing the optical film thickness of the amorphous silicon layer 130 by the wavelength of the laser beam is shown on the horizontal axis, and the absorptance of the amorphous silicon layer 130 is shown on the vertical axis.
  • 5A uses a model in which the gate electrode 110 is made of Cu, the gate insulating layer 120 is made of silicon oxide, and the crystallization control layer 140 is 0 nm (the crystallization control layer 140 is not formed).
  • 5B uses a model in which the gate electrode 110 is made of Al, the gate insulating layer 120 is made of silicon oxide, and the crystallization control layer 140 is 0 nm.
  • the calculation in FIG. 5C uses a model in which the gate electrode 110 is made of Mo, the gate insulating layer 120 is made of silicon oxide, and the crystallization control layer 140 is 0 nm.
  • 5D uses a model in which the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the crystallization control layer 140 is 0 nm.
  • 5E uses a model in which the gate electrode 110 is made of W, the gate insulating layer 120 is made of silicon oxide, and the crystallization control layer 140 is 0 nm.
  • 5F uses a model in which the gate electrode 110 is made of MoW, the gate insulating layer 120 is made of silicon oxide, and the crystallization control layer 140 is made of 275 nm silicon oxide.
  • FIG. 6B is a diagram illustrating an example of a value obtained by converting the value on the horizontal axis of FIGS. 5A to 5F into the film thickness of the amorphous silicon layer 130.
  • FIG. 6B shows values obtained by converting the values on the horizontal axis of FIGS. 5A to 5F into the film thickness of the amorphous silicon layer 130 at the wavelength of 532 nm, the wavelength of 473 nm, and the wavelength of 569 nm. .
  • FIG. 6C is a diagram illustrating an example of values obtained by converting the values on the vertical axis in FIGS. 5A to 5F into the thickness of the gate insulating layer 120 made of silicon oxide or the gate insulating layer 120 made of silicon nitride.
  • FIG. 6C shows values obtained by converting the values on the vertical axis in FIGS.
  • 6C is an example of values obtained by converting the values on the horizontal axis and the vertical axis into the film thickness of the crystallization control layer 140 made of silicon oxide or silicon nitride or the film thickness of the gate insulating layer 120 in FIG. It can also be applied as a diagram showing.
  • l and m are integers starting from 0, and the crystallization control layer 140 is A value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness from the bottom surface of the formed amorphous silicon layer 130 to the top surface of the convex portion of the amorphous silicon layer 130 on which the crystallization control layer 140 is formed.
  • a value obtained by dividing the optical film thickness of the amorphous silicon layer 130 by the wavelength of the laser beam is X
  • the gate insulating layer is a value obtained by adding the refractive index of the gate insulating layer 120 to the film thickness of the gate insulating layer 120. If the value obtained by dividing the optical film thickness of 120 by the wavelength of the laser beam is Y, and X and Y satisfy the following (Equation 1) and (Equation 2), the convex portion of the amorphous silicon layer 130 and its lower part Part of the laser light
  • the absorptivity to include the maximum absorption rate for example, can be 50% or more.
  • 5A to 5F indicate ranges where X and Y satisfy the following (formula 1) and (formula 2), respectively.
  • FIG. 7 shows the projection of the amorphous silicon layer 130 when the thickness of the crystallization control layer 140 and the thickness of the gate insulating layer 120 are changed in the laser annealing in the step of FIG. It is a contour map which shows the calculation result of the absorption rate of a part.
  • 8A to 8C are diagrams showing changes in the absorptance of the convex portions of the amorphous silicon layer 130 when the film thickness of the crystallization control layer 140 is changed.
  • the lower horizontal axis represents the optical film thickness of the crystallization control layer 140, that is, the value obtained by integrating the refractive index of the crystallization control layer 140 with the film thickness of the crystallization control layer 140, and the wavelength of the laser light. Shows the value divided by.
  • the left vertical axis indicates the optical film thickness of the gate insulating layer 120, that is, the value obtained by dividing the refractive index of the gate insulating layer 120 by the film thickness of the gate insulating layer 120 and dividing it by the wavelength of the laser beam.
  • the film thickness of the crystallization control layer 140 when the wavelength of the laser beam is 532 nm without normalization with the wavelength of the laser beam is plotted on the horizontal axis
  • the thickness of the gate insulating layer 120 is plotted on the right vertical axis.
  • the horizontal axis indicates the value obtained by dividing the optical film thickness of the crystallization control layer 140 by the wavelength of the laser beam
  • the vertical axis indicates the absorptance of the convex portions of the amorphous silicon layer 130.
  • the gate electrode 110 is made of MoW
  • the gate insulating layer 120 is made of silicon oxide
  • the optical film thickness of the amorphous silicon layer 130 at the convex portion of the amorphous silicon layer 130 i.e., amorphous.
  • the value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness of the convex portion of the crystalline silicon layer 130 divided by the wavelength of the laser beam is 0.477 (the thickness of the amorphous silicon layer at the wavelength of 532 nm is And a model consisting of the case where the crystallization control layer 140 is silicon oxide is used.
  • the gate electrode 110 is made of MoW
  • the optical film thickness of the gate insulating layer 120 that is, the value obtained by adding the refractive index of the gate insulating layer 120 to the film thickness of the gate insulating layer 120, A value obtained by dividing by the wavelength is 0.331 (corresponding to a wavelength of 532 nm and a silicon oxide layer thickness of 120 nm), and a model is used in which the crystallization control layer 140 is made of silicon oxide.
  • the broken line, the two-dot chain line, and the solid line respectively indicate the refractive index of the amorphous silicon layer 130 to the optical film thickness of the amorphous silicon layer 130, that is, the film thickness of the convex portion of the amorphous silicon layer 130.
  • the value obtained by dividing the integrated value by the wavelength of the laser beam is 0.286 (corresponding to a non-crystalline silicon layer thickness of 30 nm at a wavelength of 532 nm), 0.763 (non-crystalline silicon layer thickness of 80 nm at a wavelength of 532 nm). ) And 0.954 (corresponding to a film thickness of the amorphous silicon layer of 100 nm at a wavelength of 532 nm).
  • the gate electrode 110 is made of MoW
  • the gate insulating layer 120 is made of silicon oxide
  • the optical film thickness of the amorphous silicon layer 130 at the convex portion of the amorphous silicon layer 130 that is, amorphous.
  • the value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness of the convex portion of the crystalline silicon layer 130 divided by the wavelength of the laser beam is 0.477 (the thickness of the amorphous silicon layer at the wavelength of 532 nm is And a model consisting of the case where the crystallization control layer 140 is silicon oxide is used.
  • the optical film thickness of the gate insulating layer 120 that is, the value obtained by adding the refractive index of the gate insulating layer 120 to the film thickness of the gate insulating layer 120, respectively.
  • the value divided by 0.276 (corresponding to a silicon oxide layer thickness of 100 nm at a wavelength of 532 nm), 0.552 (corresponding to a silicon oxide layer thickness of 200 nm at a wavelength of 532 nm) and 1.103 (silicon oxide at a wavelength of 532 nm). The calculation results when the layer thickness corresponds to 400 nm are shown.
  • the gate insulating layer 120 is made of silicon oxide, and the optical film thickness of the amorphous silicon layer 130 on the projection of the amorphous silicon layer 130, that is, the projection of the projection on the amorphous silicon layer 130.
  • the value obtained by adding the refractive index of the amorphous silicon layer 130 to the film thickness divided by the wavelength of the laser beam is 0.477 (corresponding to a film thickness of the amorphous silicon layer of 50 nm at a wavelength of 532 nm).
  • a model formed when the control layer 140 is made of silicon oxide is used.
  • the broken line of FIG. 8C, the dashed-two dotted line, and the continuous line have shown the calculation result in case the gate electrode 110 is Cu, Al, and MoW, respectively.
  • Z is a value obtained by dividing the optical film thickness of the crystallization control layer 140 by the wavelength of the laser beam, and k is an integer starting from 0. If (Formula 3) is satisfied, the absorption efficiency of the laser light at the convex portion of the amorphous silicon layer 130 and the portion below the convex portion can be increased.
  • a of FIG. 7 has shown the range where Z satisfy
  • the convex portion of the channel layer is formed of the crystalline silicon layer 131, and both sides of the convex portion are formed of the amorphous silicon layer 130. Therefore, it is possible to achieve both excellent on characteristics and excellent off characteristics.
  • FIG. 9 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this embodiment.
  • the first crystalline silicon layer 130 is replaced with the second crystalline silicon layer 230, and the crystalline silicon layer 131 is replaced with the first crystalline silicon layer 231.
  • the first crystalline silicon layer 130 is replaced with the second crystalline silicon layer 230, and the crystalline silicon layer 131 is replaced with the first crystalline silicon layer 231.
  • the thin film transistor is formed on the substrate 100, the gate electrode 110 formed on the substrate 100, the gate insulating layer 120 formed on the gate electrode 110, and the gate insulating layer 120 above the gate electrode 110.
  • the first crystalline silicon layer 231 as the first silicon layer and the second crystalline silicon as the second silicon layer formed on both sides of the first crystalline silicon layer 231 on the gate insulating layer 120 A layer 230, a source electrode 171 formed above one of the second crystalline silicon layers 230, and a drain electrode 172 formed above the other of the second crystalline silicon layers 230, the first crystalline
  • the silicon layer 231 and the second crystalline silicon layer 230 are formed by irradiating the amorphous silicon layer with laser light, and are formed on the second crystalline silicon layer 230.
  • the average particle diameter of Murrell crystal average particle size smaller than the crystals contained in the first crystalline silicon layer 231. Further, a contact layer 162 formed between the second crystalline silicon layer 230 and the source electrode 171 and a contact layer 161 formed between the second crystalline silicon layer 230 and the drain electrode 172 are provided.
  • the first crystalline silicon layer 231 and the second crystalline silicon layer 230 are semiconductor layers formed on the gate insulating layer 120 and constitute a channel layer whose carrier movement is controlled by the voltage of the gate electrode 110. .
  • the first crystalline silicon layer 231 and the second crystalline silicon layer 230 are made of a crystalline silicon layer, and are made polycrystalline by irradiating the amorphous silicon of the amorphous silicon layer with laser. Formed).
  • the first crystalline silicon layer 231 and the second crystalline silicon layer 230 may be silicon layers having a mixed crystal structure of amorphous silicon and crystalline silicon layers.
  • the average grain size of crystals contained in the first crystalline silicon layer 231 is not less than 40 nm and not more than 1 ⁇ m, and the average grain size of crystals contained in the second crystalline silicon layer 230 is not less than 10 nm and less than 40 nm.
  • the channel layer has a convex part and a flat part on the surface.
  • the film thickness (flat portion) from the bottom surface of the channel layer (bottom surfaces of the first crystalline silicon layer 231 and the second crystalline silicon layer 230) to the surface of the flat portion (upper surface of the second crystalline silicon layer 230). is thinner than the thickness from the bottom surface of the channel layer to the top surface of the convex portion (the top surface of the first crystalline silicon layer 231) (thickness of the convex portion).
  • the convex portion of the channel layer is located above the gate electrode 110, and both ends thereof are located inside the both ends of the gate electrode 110.
  • FIG. 10 is a cross-sectional view schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to this embodiment.
  • the thin film transistor manufacturing method includes a first step of preparing the substrate 100, a second step of forming the gate electrode 110 on the substrate 100, a third step of forming the gate insulating layer 120 on the gate electrode 110, a gate A fourth step of forming the amorphous silicon layer 330 on the insulating layer 120, a fifth step of forming the crystallization control layer 140 on the amorphous silicon layer 330, and the crystallization control layer 140 are combined with the gate electrode 110.
  • a sixth step of patterning so as to leave a region above and a laser beam is continuously irradiated to the patterned crystallization control layer 140 and the amorphous silicon layer 330 on which the crystallization control layer 140 is not formed.
  • the non-crystalline silicon layer 330 in which the crystallization control layer 140 is formed is used as the first crystalline silicon layer 231, and the non-bonding in which the crystallization control layer 140 is not formed.
  • the crystallization control layer 140 is an absorptance increasing layer that increases the absorptance with respect to laser light of a portion of the amorphous silicon layer 330 where the crystallization control layer 140 is formed.
  • the absorption rate of the amorphous silicon layer 330 with respect to the laser light is the absorption of the convex portion of the amorphous silicon layer 330 and the portion below the convex portion corresponding to the lower portion of the crystallization control layer 140.
  • the first crystallinity includes a crystal having an average grain size larger than the absorptance of the both sides of the convex portion of the amorphous silicon layer 330 and larger than the average grain size of crystals contained in the second crystalline silicon layer 230.
  • a silicon layer 231 is formed.
  • a glass substrate is prepared as the substrate 100 as shown in FIG.
  • a gate electrode 110 having a predetermined shape is formed on the substrate 100.
  • a gate insulating layer 120 is formed on the substrate 100 and the gate electrode 110 so as to cover the gate electrode 110.
  • an amorphous silicon layer 330 made of amorphous silicon is continuously formed on the gate insulating layer 120 by plasma CVD or the like. To do. Note that the amorphous silicon layer 330 is made of the same material as the amorphous silicon layer 130.
  • the crystallization control layer 140 is formed on the non-crystalline silicon layer 330.
  • a part of the amorphous silicon layer 330 and the crystallization control layer 140 are continuously etched away.
  • the convex portion of the amorphous silicon layer 330 is formed by self-alignment, and the side surface of the lower amorphous silicon layer 330 and the side surface of the upper crystallization control layer 140 are flush with each other.
  • the convex part of the layer 330 is formed.
  • the non-crystalline silicon layer 330 is formed into a first crystalline silicon layer 231 and a second crystalline silicon layer 230 by laser annealing.
  • a predetermined laser beam is moved relative to the substrate 100 in a certain direction, and the amorphous silicon layer 330 is crystallized using the laser beam, so that the first crystalline silicon layer 231 and the second crystalline silicon layer 231 A crystalline silicon layer 230 is generated.
  • a dehydrogenation process is performed on the formed amorphous silicon layer 330.
  • the first crystalline silicon layer 231 and the second crystalline silicon layer 230 are formed by making the amorphous silicon layer 330 polycrystalline (including microcrystals) by laser annealing.
  • the laser beam scans the amorphous silicon layer 330 in the order of one flat portion, the convex portion, and the other flat portion of the amorphous silicon layer 330, and the film thickness of the flat portion is the film thickness of the convex portion. Since it is thinner, the absorption rate of the laser beam in the flat portion is low. Therefore, in the amorphous silicon layer 330, the first crystalline silicon layer 231 having a large average crystal grain size is formed on the convex portion and the portion below the convex portion, but the crystalline portion is formed on the flat portions on both sides of the convex portion. A second crystalline silicon layer 230 having a small average grain size is formed.
  • the laser light source of the laser light is a laser having a wavelength in the visible light region.
  • the laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and preferably a green laser having a wavelength of 473 nm to 561 nm.
  • the laser light having a wavelength in the visible light region is preferably light in a continuous oscillation mode or a pseudo continuous oscillation mode. This is because when the laser light having a wavelength in the visible light region is in a pulse oscillation mode other than the continuous oscillation mode or the pseudo continuous oscillation mode, the amorphous silicon layer 330 is irradiated with the laser light discontinuously.
  • the amorphous silicon layer 330 cannot always be kept in a molten state.
  • the reason why the pseudo continuous oscillation mode is also included is that the amorphous silicon layer 330 can be maintained in its molten state by being reheated by applying a pulse before it is cooled to below its melting point. Therefore, a preferred embodiment of the quasi-continuous oscillation mode is one in which the amorphous silicon layer 330 can be reheated by applying a pulse before it is cooled to below its melting point, and the molten state can be maintained.
  • the laser light having a wavelength in the visible light region may be light emitted from a solid-state laser device or light emitted from a laser device using a semiconductor laser element.
  • a density variation of less than 5% is preferred.
  • the convex portion of the amorphous silicon layer 330 is formed from the bottom surface of the amorphous silicon layer 330 so that the laser beam does not attenuate until it reaches directly above the gate insulating layer 120. It is preferable that the convex part is formed so that the film thickness up to the upper surface of the film is 100 nm or less.
  • the amorphous silicon layer 330 is formed from the bottom surface of the amorphous silicon layer 330. It is preferable that the convex portion is formed so that the film thickness up to the upper surface of both sides of the convex portion is 10 nm or more.
  • the extinction coefficient is 0.01 or less with respect to the wavelength of the laser light of FIG.
  • a film such as silicon oxide or silicon nitride is preferably formed as the gate insulating layer 120.
  • the extinction coefficient is 0.01 or less with respect to the wavelength of the laser light of FIG. It is preferable to form a film such as silicon oxide or silicon nitride as the crystallization control layer 140.
  • the amorphous silicon layer 330 is irradiated with the laser beam condensed linearly, and there are, for example, two irradiation methods as described above.
  • the crystallization control layer 140 is removed by wet etching.
  • the crystallization control layer 140 is made of silicon oxide, hydrofluoric acid is used, and when it is made of silicon nitride, phosphoric acid is used as an etching solution.
  • a contact layer 160 to be contact layers 161 and 162 is formed so as to extend from the upper surface of the convex portion of the first crystalline silicon layer 231 to the flat portion.
  • the contact layer 160 is formed so as to cover the upper and side surfaces of the convex portion of the first crystalline silicon layer 231 and the upper surface of the flat portion of the second crystalline silicon layer 230.
  • a resist material is applied on the contact layer 160, and exposure and development are performed to form a resist patterned into a predetermined shape. Thereafter, the contact layer 160 and the channel layer (second crystalline silicon layer 230) are etched using this resist as a mask, thereby patterning the contact layer 160 and the channel layer into an island shape. Then, as shown in FIG. 10J, a source / drain metal film 170 to be the source electrode 171 and the drain electrode 172 is formed so as to cover the contact layer 160.
  • a source electrode 171 and a drain electrode 172 and contact layers 161 and 162 corresponding to the source electrode 171 and the drain electrode 172 are formed by using a photolithography method and an etching method.
  • the convex portion of the channel layer is formed of the first crystalline silicon layer 231 having a large average crystal grain size, and both sides of the convex portion are small in the average crystal grain size.
  • a bicrystalline silicon layer 230 is formed. Therefore, it is possible to achieve both excellent on characteristics and excellent off characteristics.
  • Modification Example 1 of the thin film transistor according to the first and second embodiments of the present invention will be described below.
  • a modification of the thin film transistor according to the first embodiment will be described, but it is needless to say that the modification can be applied to the thin film transistor according to the second embodiment.
  • FIG. 11 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this modification.
  • the first and second embodiments are that the gate insulating layer 120 has a two-layer structure and includes a silicon nitride layer 121 and a silicon oxide layer 122 formed on the silicon nitride layer 121. Different from form. The following description will focus on differences from the first and second embodiments.
  • This thin film transistor includes a substrate 100, a gate electrode 110, a gate insulating layer 120, a crystalline silicon layer 131, an amorphous silicon layer 130, a source electrode 171 and a drain electrode 172, and contact layers 162 and 161. Prepare.
  • the capacitance of the series capacitor formed by the silicon nitride layer 121 and the silicon oxide layer 122 is equal to the capacitance of the single-layer silicon oxide layer 122 having a thickness of 100 nm to 140 nm. It has such a film thickness.
  • the manufacturing method of the thin film transistor of this modification is the same as the manufacturing method shown in FIG. 2, but in the step of FIG. 2C, the silicon nitride layer 121 and the silicon oxide layer formed on the silicon nitride layer 121 are used.
  • 2 is different from the manufacturing method of FIG. 2 in that a gate insulating layer 120 composed of 122 is formed. Since the gate insulating layer 120 has a two-layer structure, the laser light of the laser annealing in FIG. 2G is easily reflected by the gate insulating layer 120, so that the laser light absorption rate of the amorphous silicon layer 130 is increased. be able to.
  • FIG. 12 shows the crystal of the crystalline silicon layer 131 when the absorption rate of the laser beam of the amorphous silicon layer 130 and the scan speed of the laser beam are changed in the step of FIG. It is a figure which shows the change of sex.
  • changing the absorptance of the amorphous silicon layer 130 is realized by changing the thickness of the amorphous silicon layer 130, that is, the thickness of the channel layer.
  • the laser output is 40 kW / cm 2
  • the gate electrode 110 is 50 nm thick MoW
  • the gate insulating layer 120 is 65 nm thick silicon nitride layer 121
  • the 85 nm thick silicon oxide layer 122 is A sample consisting of
  • a-Si in FIG. 12 indicates that the crystalline silicon layer 131 does not crystallize as crystalline silicon but becomes amorphous silicon
  • SPC indicates the average grain size of the crystalline silicon layer 131.
  • Ex & .SPC indicates that the average particle diameter of the crystalline silicon layer 131 is approximately 40 nm or more and less than 60 nm
  • p-Si indicates the crystalline silicon layer.
  • the average particle size of 131 is about 60 nm or more and 1 ⁇ m or less
  • “abration” indicates that the crystalline silicon layer 131 does not function as a channel layer.
  • an amorphous silicon layer and a crystalline silicon layer can be formed by changing the scanning speed of laser annealing and the absorptance of the amorphous silicon layer 130. Even when the scan speed is constant, the absorption rate of the amorphous silicon layer 130 in which the crystallization control layer 140 is formed and the absorption rate of the amorphous silicon layer 130 in which the crystallization control layer is not formed. By making a difference of 1% or more, the amorphous silicon layer 130 in the flat part of the channel layer and the crystalline silicon layer 131 in the convex part can be formed.
  • the absorptance of the amorphous silicon layer 330 on which the crystallization control layer 140 is formed and the crystallization control layer 140 are not formed.
  • the first crystalline silicon layer 231 of the channel layer and the second crystalline silicon layers 230 on both sides thereof can be formed.
  • FIG. 13A shows an amorphous silicon layer 130 when the thickness of the amorphous silicon layer 130 and the thickness of the gate insulating layer 120 are changed in the step of FIG. It is a contour map which shows the calculation result of the absorptivity.
  • the lower horizontal axis indicates the optical thickness of the amorphous silicon layer 130, that is, the value obtained by integrating the refractive index of the amorphous silicon layer 130 with the thickness of the amorphous silicon layer 130.
  • the value divided by the wavelength of light is shown.
  • the left vertical axis shows the optical thickness obtained by converting the gate insulating layer 120 composed of the silicon nitride layer 121 and the silicon oxide layer 122 by the refractive index of the silicon oxide layer 122, that is, the silicon nitride layer 121 has a thickness of silicon nitride.
  • the sum of the value obtained by integrating the refractive index of the layer 121 and the value obtained by integrating the refractive index of the silicon oxide layer 122 with the thickness of the silicon oxide layer 122 is integrated with the refractive index of the silicon oxide layer 122 and the wavelength of the laser beam.
  • the value divided by the value is shown.
  • the film thickness (film thickness) of the gate insulating layer 120 is plotted with the film thickness of the amorphous silicon layer 130 when the laser beam wavelength is set to 532 nm without being normalized by the laser beam wavelength.
  • the thickness of the 120 nm single-layer silicon oxide layer 122 is shown on the right vertical axis. Further, on the right vertical axis, the film thickness ratio of the silicon oxide layer 122 and the silicon nitride layer 121 is also indicated by “film thickness of the silicon oxide layer 122 / film thickness of the silicon nitride layer 121”.
  • the gate electrode 110 is made of MoW and the crystallization control layer 140 is 0 nm.
  • FIG. 13B to 13D are diagrams showing examples of values obtained by converting the values on the vertical axis in FIG. 13A into the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 included in the gate insulating layer 120.
  • FIG. FIG. 13A is a diagram showing examples of values obtained by converting the values on the vertical axis in FIG. 13A into the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 included in the gate insulating layer 120.
  • FIGS. 13B and 13D show values obtained by calculating the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 at a wavelength of 532 nm.
  • FIGS. 13C and 13D show values obtained by calculating the film thicknesses of the silicon oxide layer 122 and the silicon nitride layer 121 at wavelengths of 561 nm and 473 nm, respectively.
  • the relative dielectric constants of the silicon oxide layer 122 and the silicon nitride layer 121 are calculated as 4.1 and 7.9, respectively.
  • the refractive index of the amorphous silicon layer 130 is integrated with the film thickness from the bottom surface of the amorphous silicon layer 130 on which the 140 is formed to the top surface of the convex portion of the amorphous silicon layer 130 on which the crystallization control layer 140 is formed.
  • the value obtained by dividing the optical film thickness of the amorphous silicon layer 130 by the wavelength of the laser beam is X, and the gate insulating layer 120 composed of the silicon nitride layer 121 and the silicon oxide layer 122 is formed as a silicon oxide layer.
  • the silicon oxide layer 122 has an optical film thickness converted by the refractive index of 122, that is, a value obtained by adding the refractive index of the silicon nitride layer 121 to the film thickness of the silicon nitride layer 121 and the film thickness of the silicon oxide layer 122.
  • a value obtained by dividing the sum of the refractive index and the sum of the refractive index of the silicon oxide layer 122 and the laser light wavelength is Y, and X and Y are the following (Formula 4) and (Formula 5).
  • the laser beam absorptance of the convex portion of the non-crystalline silicon layer 130 and the lower portion thereof includes the maximum absorptivity, for example, 50% or more It can be.
  • 12A shows a range where X and Y satisfy the following (formula 4) and (formula 5), and B in FIG. 12 shows that X and Y satisfy the following (formula 6) and (formula 7). The range is shown.
  • the gate insulating layer 120 since the gate insulating layer 120 has a two-layer structure, the laser light absorption rate of the amorphous silicon layer 130 can be increased. Therefore, for example, the on-current can be increased by increasing the average crystal grain size of the crystalline silicon layer 131 of the channel layer.
  • Modification Example 2 of the thin film transistor according to the first and second embodiments of the present invention will be described below.
  • a modification of the thin film transistor according to the first embodiment will be described, but it is needless to say that the modification can be applied to the thin film transistor according to the second embodiment.
  • FIG. 14 is a cross-sectional view schematically showing a configuration of a thin film transistor according to this modification.
  • This thin film transistor includes a film thickness of the crystalline silicon layer 131 or the first crystalline silicon layer 231 as the first silicon layer and a film of the amorphous silicon layer 130 or the second crystalline silicon layer 230 as the second silicon layer.
  • the thin film transistor is different from the thin film transistors according to the first and second embodiments in that the thickness is the same.
  • This thin film transistor is a channel etch type bottom gate thin film transistor for a display device, and includes a substrate 100, a gate electrode 110 formed on the substrate 100, a gate insulating layer 120 formed on the gate electrode 110, A crystalline silicon layer 131 formed on the gate insulating layer 120 and above the gate electrode 110; and an amorphous silicon layer formed on both sides of the crystalline silicon layer 131 on the gate insulating layer 120.
  • the film thickness of the silicon layer 131 and the film thickness of the amorphous silicon layer 130 are the same.
  • the bottom surface of the crystalline silicon layer 131 of the channel layer and the bottom surface of the amorphous silicon layer 130 are flush and form the same plane, and the top surface of the crystalline silicon layer 131 and the top surface of the amorphous silicon layer 130 are also formed. Similarly, the same plane is formed on the same plane.
  • the crystalline silicon layer 131 is located above the gate electrode 110, and both ends thereof are located inside the both ends of the gate electrode 110. That is, the gate length of the gate electrode 110 is longer than the electrode interval defined by the opening between the source electrode 171 and the drain electrode 172.
  • both sides of the crystalline silicon layer 131 of the channel layer, that is, the amorphous silicon layer 130 of the channel layer serve as a charge transfer path.
  • Both ends of the gate electrode 110 are located on the inner side than both ends of the channel layer (the end of the amorphous silicon layer 130 opposite to the crystalline silicon layer 131).
  • the positions of the opposing end portions (opening end portions) of the source electrode 171 and the drain electrode 172 (contact layers 161 and 162) are both ends of the crystalline silicon layer 131 (the crystalline silicon layer 131 and the amorphous silicon layer 130). And the position of the interface.
  • FIG. 15 is a cross-sectional view schematically showing the configuration of each step in the method of manufacturing a thin film transistor according to this modification.
  • the thin film transistor manufacturing method includes a first step of preparing the substrate 100, a second step of forming the gate electrode 110 on the substrate 100, a third step of forming the gate insulating layer 120 on the gate electrode 110, a gate
  • the fourth step of forming the amorphous silicon layer 130 on the insulating layer 120, the fifth step of forming the crystallization control layer 140 on the amorphous silicon layer 130, and the crystallization control layer 140 are combined with the gate electrode 110.
  • a sixth step of patterning so as to leave a region above the substrate, and laser light is continuously irradiated to the patterned crystallization control layer 140 and the amorphous silicon layer 130 on which the crystallization control layer 140 is not formed.
  • the non-crystalline silicon layer 130 in which the crystallization control layer 140 is formed is used as the crystalline silicon layer 131, and the non-crystallinity in which the crystallization control layer 140 is not formed.
  • a ninth step of forming the drain electrode 172 above the other of the non-crystalline silicon layer 130 is a seventh step of leaving the recon layer 130 as the amorphous silicon layer 130, an eighth step of removing the patterned crystallization control layer 140, and forming a source electrode 171 on one side of the amorphous silicon layer 130.
  • a glass substrate is prepared as the substrate 100.
  • a gate electrode 110 having a predetermined shape is formed on the substrate 100.
  • a gate insulating layer 120 is formed on the substrate 100 and the gate electrode 110 so as to cover the gate electrode 110.
  • an amorphous silicon layer 130 made of amorphous silicon is continuously formed on the gate insulating layer 120 by plasma CVD or the like. To do.
  • a crystallization control layer 140 is formed on the amorphous silicon layer 130 by plasma CVD or the like, and a part of the crystallization control layer 140 is removed by etching.
  • a part of the amorphous silicon layer 130 is made into a crystalline silicon layer 131 by a laser annealing method. Specifically, a predetermined laser beam is moved relative to the substrate 100 in a certain direction, and the amorphous silicon layer 130 is crystallized using the laser beam to generate the crystalline silicon layer 131.
  • the crystallization control layer 140 is removed by wet etching.
  • a contact layer 160 to be the contact layers 161 and 162 is formed so as to extend from the upper surface of the crystalline silicon layer 131 to the upper surface of the amorphous silicon layer 130.
  • a resist material is applied on the contact layer 160, and exposure and development are performed to form a resist patterned into a predetermined shape. Thereafter, as shown in FIG. 15 (i), the contact layer 160 and the channel layer (amorphous silicon layer 130) are etched using this resist as a mask, so that the contact layer 160 and the channel layer are formed in an island shape. Pattern.
  • a source / drain metal film 170 to be the source electrode 171 and the drain electrode 172 is formed so as to cover the contact layer 160.
  • a resist material is applied onto the source / drain metal film 170, exposed and developed, and then patterned into a predetermined shape. Form. Thereafter, as shown in FIG. 15 (k), wet etching is performed using this resist as a mask to pattern the source / drain metal film 170, thereby forming a source electrode 171 and a drain electrode 172 having predetermined shapes. At this time, etching stops at the contact layer 160, and the contact layer 160 is exposed.
  • the resist on the source electrode 171 and the drain electrode 172 is removed, and the contact layer 160 is patterned by performing dry etching using the source electrode 171 and the drain electrode 172 as a mask. Thereby, a pair of contact layers 161 and 162 having a predetermined shape can be formed.
  • the patterning of the source / drain metal film 170 and the contact layer 160 is such that the positions of the opposite ends of the source electrode 171 and the drain electrode 172 (contact layers 161 and 162) coincide with the positions of both ends of the crystalline silicon layer 131. To be done.
  • the positions of the opposite end portions of the source electrode 171 and the drain electrode 172 coincide with the positions of both ends of the crystalline silicon layer 131. It may be changed according to. For example, as shown in FIG. 16, when importance is placed on the on-characteristic (FIG. 16A), the opposing ends of the source electrode 171 and the drain electrode 172 (contact layers 161 and 162) are the crystalline silicon layer 131. It is located so as to penetrate inside from both ends, and is located above the crystalline silicon layer 131. Therefore, the crystalline silicon layer 131 and the source electrode 171 have an overlapping region, and the crystalline silicon layer 131 and the drain electrode 172 have an overlapping region. When importance is attached to off characteristics (FIG.
  • the opposing ends of the source electrode 171 and the drain electrode 172 are formed from the both ends of the crystalline silicon layer 131 to the amorphous silicon layer. It is located so as to penetrate into the side of 130 and is located above the amorphous silicon layer 130.
  • the ends of the opposing source electrode 171 and drain electrode 172 are formed above the crystalline silicon layer 131 in FIG. 16A, but in FIG. 16B and FIG. It is formed above the conductive silicon layer 130.
  • the thin film transistor of this modification it is possible to achieve both excellent on characteristics and excellent off characteristics for the same reason as in the first embodiment.
  • Modification Example 3 of the thin film transistor according to the first and second embodiments of the present invention will be described below.
  • a modification of the thin film transistor according to the first embodiment will be described, but it is needless to say that the modification can be applied to the thin film transistor according to the second embodiment.
  • FIG. 17 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this modification.
  • the contact layers 161 and 162 are formed so as to straddle from the upper surface of the amorphous silicon layer 130 to the side surfaces of the amorphous silicon layer 130 and the upper surface of the gate insulating layer 120, and the gate electrode 110.
  • the thin film transistor is different from the thin film transistor according to the modification 2 in that both ends of the channel layer are located outside the both ends of the channel layer. That is, it differs from the thin film transistor according to Modification 2 in that the on-current is increased by injecting carriers also from the side surface of the amorphous silicon layer 130.
  • FIG. 18 is a cross-sectional view schematically showing the configuration of each step in the method for manufacturing a thin film transistor according to this modification.
  • the gate electrode 110 is formed wide so that the gate electrode 110 is located outside the island-shaped channel layer, and the contact layer 160 is formed after the channel layer is patterned into an island shape. This is different from the method for manufacturing the thin film transistor according to the first modification.
  • a glass substrate is prepared as a substrate 100 as shown in FIG.
  • a gate electrode 110 having a predetermined shape is formed on the substrate 100.
  • a gate insulating layer 120 is formed on the substrate 100 and the gate electrode 110 so as to cover the gate electrode 110.
  • an amorphous silicon layer 130 made of amorphous silicon is continuously formed on the gate insulating layer 120 by plasma CVD or the like. To do.
  • a crystallization control layer 140 is formed on the amorphous silicon layer 130 by plasma CVD or the like, and a part of the crystallization control layer 140 is removed by etching.
  • a part of the amorphous silicon layer 130 is formed into a crystalline silicon layer 131 by laser annealing.
  • the crystallization control layer 140 is removed by wet etching.
  • a resist material is applied on the channel layers (crystalline silicon layer 131 and amorphous silicon layer 130), and exposed and developed to form a resist patterned in a predetermined shape. Thereafter, as shown in FIG. 18H, the channel layer is patterned into an island shape by etching the channel layer using this resist as a mask.
  • contact layers 161 and 162 are formed so as to extend from the upper surface of the crystalline silicon layer 131 to the upper and side surfaces of the amorphous silicon layer 130 and the upper surface of the gate insulating layer 120.
  • a contact layer 160 is formed.
  • a source / drain metal film 170 to be the source electrode 171 and the drain electrode 172 is formed so as to cover the contact layer 160.
  • a resist material is applied onto the source / drain metal film 170, exposed and developed, and then patterned into a predetermined shape. Form. Thereafter, as shown in FIG. 18K, wet etching is performed using this resist as a mask to pattern the source / drain metal film 170, thereby forming a source electrode 171 and a drain electrode 172 having a predetermined shape. At this time, etching stops at the contact layer 160, and the contact layer 160 is exposed.
  • the resist on the source electrode 171 and the drain electrode 172 is removed, and the contact layer 160 is patterned by performing dry etching using the source electrode 171 and the drain electrode 172 as a mask. Thereby, a pair of contact layers 161 and 162 having a predetermined shape can be formed.
  • the thin film transistor of this modification it is possible to achieve both excellent on characteristics and excellent off characteristics for the same reason as in the first embodiment.
  • FIG. 19 is a cross-sectional view schematically showing the configuration of the thin film transistor according to this comparative example.
  • This thin film transistor includes a substrate 100, a gate electrode 110, a gate insulating layer 120, a crystalline silicon layer 131, an amorphous silicon layer 130, a source electrode 171 and a drain electrode 172, and contact layers 162 and 161. Prepare.
  • This thin film transistor is the same as the first and second embodiments in that the crystalline silicon layer 131 is formed by irradiating the amorphous silicon layer 130 with laser light using the source electrode 171 and the drain electrode 172 as a mask. Different.
  • the positions of the opposite end portions of the source electrode 171 and the drain electrode 172 are crystalline silicon. It corresponds to the position of both ends of the layer 131.
  • the opposite end portions of the source electrode 171 and the drain electrode 172 are intruded into the inside from both ends of the crystalline silicon layer 131 to improve the on-characteristics, or both ends of the crystalline silicon layer 131
  • both sides of the channel layer are the amorphous silicon layer 130, and both sides of the channel layer are crystalline silicon. It can not be. Therefore, the average grain size of the crystalline silicon on both sides of the channel layer is increased, the on-current is increased on both sides of the channel layer as compared with the case of amorphous silicon, or the crystalline silicon on both sides of the channel layer is increased. While reducing the average grain size and increasing the on-current on both sides of the channel layer as compared to the case of amorphous silicon, the off-current is higher than that on the both sides of the channel layer using crystalline silicon having a large average grain size. Depending on the desired thin film transistor design, it cannot be made differently.
  • amorphous silicon 130 below the source electrode 171 and the drain electrode 172 is amorphous silicon 130, and the proportion of the amorphous silicon layer in the channel layer of the thin film transistor is large (C and D in FIG. 19). Since the amorphous silicon layer acts as a resistance component and becomes a barrier for a current path horizontal to the channel layer, the resistance component in the horizontal direction of the channel layer is increased as compared with the first and second embodiments.
  • the film thickness of the crystalline silicon layer 131 and the film thickness of the amorphous silicon layer 130 are the same, when the film thickness of the crystalline silicon layer 131 and the film thickness of the amorphous silicon layer 130 are different, That is, compared with the case where the film thickness from the bottom surface to the top surface of the amorphous silicon layer 130 is smaller than the film thickness from the bottom surface to the top surface of the crystalline silicon layer 131, the vertical direction of the channel layer by the amorphous silicon layer The resistance component of increases.
  • the thin film transistors according to the first and second embodiments can realize excellent on characteristics and excellent off characteristics as compared with the thin film transistors according to this comparative example.
  • FIG. 20 is an external view of a display device according to the third embodiment of the present invention.
  • FIG. 21 is a partially cutaway perspective view of the organic EL panel according to the present embodiment.
  • the display device 340 is a display device including an organic EL panel, and includes the thin film transistor of the first or second embodiment, and the thin film transistor drives the organic EL panel.
  • the display device 340 includes an organic EL panel 320 using the thin film transistor of the first or second embodiment as a switching transistor or a driving transistor of an active matrix substrate.
  • the organic EL panel 320 includes an active matrix substrate 321, a plurality of pixels 322 arranged in a matrix on the active matrix substrate 321, and a pixel circuit connected to the pixels 322 and arranged in an array on the active matrix substrate 321.
  • a source line 327 and a gate line 328 are provided.
  • the organic EL layer 325 is configured by laminating layers such as an electron transport layer, a light emitting layer, and a hole transport layer.
  • FIG. 22 is a diagram showing a circuit configuration of the pixel 322 of the organic EL panel 320 of FIG.
  • the pixel 322 includes a drive transistor 331, a switching transistor 332, an organic EL element 333, and a capacitor 334.
  • the drive transistor 331 is a transistor that drives the organic EL element 333
  • the switching transistor 332 is a transistor for selecting the pixel 322.
  • the source electrode 332S of the switching transistor 332 is connected to the source line 327, the gate electrode 332G is connected to the gate line 328, and the drain electrode 332D is connected to the capacitor 334 and the gate electrode 331G of the driving transistor 331.
  • drain electrode 331D of the drive transistor 331 is connected to the power supply line 335, and the source electrode 331S is connected to the anode of the organic EL element 333.
  • the organic EL display device using the organic EL panel has been described.
  • the thin film transistor of the first or second embodiment can also be applied to a transistor that drives the liquid crystal panel of the liquid crystal display device.
  • the display device includes a liquid crystal panel, and includes the thin film transistor according to the first or second embodiment, and the thin film transistor drives the liquid crystal panel.
  • the thin-film transistor, its manufacturing method, and the display apparatus of this invention were demonstrated based on embodiment, this invention is not limited of these embodiment.
  • the present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.
  • the display device of the above-described embodiment can be used as a flat panel display, and can be applied to an electronic apparatus having any display unit such as a television set, a personal computer, and a mobile phone.
  • the thickness of the crystalline silicon layer 131 and the thickness of the amorphous silicon layer 130 are the same, or the thickness of the first crystalline silicon layer 231 and the second crystallinity.
  • the film thickness of the silicon layer is assumed to be the same, but “same” at this time includes a state in which there is a step formed by laser light irradiation. For example, as shown in the top view of FIG. 23A (upper view of the step of FIG. 15F or FIG. 18F), laser light is irradiated to the amorphous silicon layer 130 in forming the crystalline silicon layer 131.
  • FIG. 23B the cross-sectional view of the step of FIG. 15F or FIG. 18F
  • a step is formed between the surface of the crystalline silicon layer 131 and the surface of the amorphous silicon layer 130. Therefore, the state where there is such a step is also included in the “same” in the present invention. Note that the change in the bulge amount with respect to the input energy of the laser light to the amorphous silicon layer 130 is as shown in FIG. 23C.
  • the present invention can be used for a thin film transistor, a method for manufacturing the same, and a display device, and in particular, can be used for a display device such as a television set, a personal computer and a mobile phone, or various electric devices having a thin film transistor.
  • Substrate 110 331G, 332G Gate electrode 120 Gate insulating layer 121 Silicon nitride layer 122 Silicon oxide layer 130, 330 Amorphous silicon layer 131 Crystalline silicon layer 140 Crystallization control layer 160, 161, 162 Contact layer 170 Source Drain metal film 171, 331S, 332S Source electrode 172, 331D, 332D Drain electrode 230 Second crystalline silicon layer 231 First crystalline silicon layer 320 Organic EL panel 321 Active matrix substrate 322 Pixel 323 Pixel circuit 324 Anode 325 Organic EL layer 326 Cathode 327 Source line 328 Gate line 331 Drive transistor 332 Switching transistor 333 Organic EL element 334 Capacitor 35 power supply line 340 display device 401, 402, 403, 404 layer

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un transistor à couches minces offrant des caractéristiques supérieures à la fois de marche et d'arrêt. Le transistor à couches minces comprend : un substrat (100), une électrode de grille (110); une couche d'isolation de grille (120), une couche de silicium cristallin (131) formée sur la couche d'isolation de grille (120) et au-dessus de l'électrode de grille (110), une couche de silicium non cristallin (130) formée sur la couche d'isolation de grille (120) et sur les deux côtés de la couche de silicium cristallin (131), et une électrode source (171) et une électrode drain (172). La couche de silicium cristallin (131) et la couche de silicium non cristallin (130) sont formées par irradiation de la couche de silicium non cristallin par une lumière laser.
PCT/JP2011/004353 2011-07-29 2011-07-29 Transistor à couches minces et son procédé de fabrication WO2013018126A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2011/004353 WO2013018126A1 (fr) 2011-07-29 2011-07-29 Transistor à couches minces et son procédé de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2011/004353 WO2013018126A1 (fr) 2011-07-29 2011-07-29 Transistor à couches minces et son procédé de fabrication

Publications (1)

Publication Number Publication Date
WO2013018126A1 true WO2013018126A1 (fr) 2013-02-07

Family

ID=47628708

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/004353 WO2013018126A1 (fr) 2011-07-29 2011-07-29 Transistor à couches minces et son procédé de fabrication

Country Status (1)

Country Link
WO (1) WO2013018126A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110178226A (zh) * 2019-02-22 2019-08-27 京东方科技集团股份有限公司 薄膜晶体管、像素结构、显示装置和制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006019527A (ja) * 2004-07-01 2006-01-19 Dainippon Printing Co Ltd 多結晶シリコン薄膜の製造方法、薄膜トランジスタの製造方法、及びシリコン薄膜付き基板
JP2008311425A (ja) * 2007-06-14 2008-12-25 Advanced Lcd Technologies Development Center Co Ltd 光吸収性キャップ膜の形成方法、半導体膜の結晶化方法、及び薄膜トランジスタの製造方法
JP2009290192A (ja) * 2008-05-26 2009-12-10 Samsung Mobile Display Co Ltd 薄膜トランジスタ、薄膜トランジスタの製造方法及び有機電界発光表示装置
JP2010186967A (ja) * 2009-02-13 2010-08-26 Sharp Corp 薄膜トランジスタおよびその製造方法
JP2010199529A (ja) * 2009-01-30 2010-09-09 Sharp Corp 薄膜トランジスタの製造方法
JP2011014595A (ja) * 2009-06-30 2011-01-20 Casio Computer Co Ltd 薄膜トランジスタ及び薄膜トランジスタの製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006019527A (ja) * 2004-07-01 2006-01-19 Dainippon Printing Co Ltd 多結晶シリコン薄膜の製造方法、薄膜トランジスタの製造方法、及びシリコン薄膜付き基板
JP2008311425A (ja) * 2007-06-14 2008-12-25 Advanced Lcd Technologies Development Center Co Ltd 光吸収性キャップ膜の形成方法、半導体膜の結晶化方法、及び薄膜トランジスタの製造方法
JP2009290192A (ja) * 2008-05-26 2009-12-10 Samsung Mobile Display Co Ltd 薄膜トランジスタ、薄膜トランジスタの製造方法及び有機電界発光表示装置
JP2010199529A (ja) * 2009-01-30 2010-09-09 Sharp Corp 薄膜トランジスタの製造方法
JP2010186967A (ja) * 2009-02-13 2010-08-26 Sharp Corp 薄膜トランジスタおよびその製造方法
JP2011014595A (ja) * 2009-06-30 2011-01-20 Casio Computer Co Ltd 薄膜トランジスタ及び薄膜トランジスタの製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110178226A (zh) * 2019-02-22 2019-08-27 京东方科技集团股份有限公司 薄膜晶体管、像素结构、显示装置和制造方法
CN110178226B (zh) * 2019-02-22 2022-07-26 京东方科技集团股份有限公司 薄膜晶体管、像素结构、显示装置和制造方法

Similar Documents

Publication Publication Date Title
US9929274B2 (en) Thin-film transistor, method for fabricating thin-film transistor, and display device
KR101280827B1 (ko) 어레이 기판 및 이의 제조방법
KR101410402B1 (ko) 박막 트랜지스터의 제조 방법, 박막 트랜지스터, 및디스플레이 장치
US8912054B2 (en) Thin-film semiconductor device and method of manufacturing the same
US8796692B2 (en) Thin-film semiconductor device and method for fabricating thin-film semiconductor device
JP2020004861A (ja) 薄膜トランジスタ、表示装置及び薄膜トランジスタの製造方法
JP5820402B2 (ja) 薄膜トランジスタ装置及び薄膜トランジスタ装置の製造方法
KR20100051484A (ko) 폴리실리콘을 이용한 박막트랜지스터를 포함하는 어레이 기판 및 이의 제조방법
WO2012172617A1 (fr) Transistor à couche mince et procédé de fabrication d'un transistor à couche mince
WO2012117439A1 (fr) Dispositif semiconducteur à couches minces et procédé de fabrication de celui-ci
WO2013021416A1 (fr) Dispositif semi-conducteur en couches minces et procédé de fabrication de dispositif semi-conducteur en couches minces
WO2013118233A1 (fr) Procédé de fabrication d'un dispositif à semiconducteur à film mince et dispositif à semiconducteur à film mince
JP2020004860A (ja) 薄膜トランジスタ、表示装置及び薄膜トランジスタの製造方法
JP6085758B2 (ja) 薄膜トランジスタ及び薄膜トランジスタの製造方法
JP2008085091A (ja) 薄膜トランジスタの製造方法、薄膜トランジスタ、および表示装置
US9236254B2 (en) Substrate having thin film and method of thin film formation
WO2013001579A1 (fr) Dispositif à transistor à couche mince et procédé de production d'un dispositif à transistor à couche mince
JP2013161963A (ja) 薄膜トランジスタ、薄膜トランジスタの製造方法、及び表示装置
US8530900B2 (en) Method for selectively forming crystalline silicon layer regions above gate electrodes
WO2013018126A1 (fr) Transistor à couches minces et son procédé de fabrication
KR20100130523A (ko) 폴리실리콘을 이용한 박막트랜지스터를 포함하는 어레이 기판 및 이의 제조방법
JP2003318108A (ja) 薄膜トランジスタの作製方法
WO2013018123A1 (fr) Transistor à couches minces et procédé de fabrication de celui-ci
KR20110075518A (ko) 어레이 기판의 제조방법
WO2013118234A1 (fr) Procédé de fabrication d'un dispositif à semiconducteur à film mince et dispositif à semiconducteur à film mince

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11870269

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11870269

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP