WO2015096312A1 - Array substrate and manufacturing method thereof, and display device - Google Patents

Abstract

Provided are an array substrate and manufacturing method thereof, and a display device, the array substrate manufacturing method comprising: forming patterns of an active layer (21), a source electrode (22), a drain electrode (23), data lines and a pixel electrode (25) on a base substrate (1) through a one-time patterning process; forming the pattern of an insulating layer; forming patterns of a gate (27) and gate lines through the one-time patterning process. In the array substrate manufacturing method, the array substrate and the display device of the present invention, the manufacturing of the array substrate needs to be completed through the patterning process only twice, requiring fewer and simpler manufacturing steps, greatly reducing manufacturing complexity and costs, thus significantly improving production efficiency and economic benefit.

Description

 Array substrate, manufacturing method thereof and display device

 The present invention relates to the field of display, and in particular, to an array substrate, a manufacturing method thereof, and a display device. Background technique

 The existing method for fabricating an array substrate for a multi-dimensional electric field display panel can be completed by 6-7 patterning processes. Each patterning process includes the formation of an etched material, photoresist coating, exposure and development, etching, and photoresist removal. For example, a common method of fabricating an array substrate includes:

 Forming a pattern including a common electrode, a common electrode line, a gate, and a gate line by a first patterning process;

 Forming an active layer by a second patterning process;

 Forming a via hole by a third patterning process;

 Forming a pattern including a source and a drain through a fourth patterning process;

 Forming an insulating layer by a fifth patterning process;

 A pattern including a pixel electrode is formed by a sixth patterning process.

 It can be seen that the existing fabrication method of the array substrate has the disadvantages of complicated manufacturing process, low production efficiency, high cost and low economic efficiency. Summary of the invention

 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for fabricating an array substrate having a simple fabrication process, high production efficiency, low cost, and economical efficiency, an array substrate produced by the method, and a display device including the array substrate.

 According to a first aspect of the present invention, a method for fabricating an array substrate is provided, comprising: forming a pattern including an active layer, a source, a drain, a data line, and a pixel electrode on a substrate by a patterning process;

 Forming a pattern including an insulating layer;

A pattern including a gate and a gate line is formed by one patterning process. In one example, the step of forming a pattern of an active layer, a source, a drain, a data line, and a pixel electrode on a base substrate by one patterning process includes:

 Forming a semiconductor film on the base substrate;

 Coating a photoresist on the semiconductor film, exposing and developing the photoresist through a two-tone mask, completely retaining the photoresist corresponding to the active layer region, partially retaining the source, the drain, and the data a photoresist corresponding to the line and the pixel electrode region, completely removing the photoresist in the remaining region to expose the semiconductor film;

 Etching the exposed semiconductor film;

 The photoresist is subjected to ashing treatment to thin the photoresist corresponding to the active layer region and expose the semiconductor film in a region other than the active layer region;

 Forming the exposed semiconductor film into a conductor by plasma treatment to form a pattern of a source, a drain, a data line, and a pixel electrode;

 The remaining photoresist is removed.

 In one example, the step of forming the pattern of the gate and the gate lines by one patterning process further includes forming a pattern of the common electrode lines and the comb-shaped common electrodes.

 In one example, the steps of forming the pattern of the gate and the gate lines by one patterning process, and the pattern of the common electrode lines and the comb-shaped common electrodes include:

 Forming a transparent conductive film and a metal film sequentially on the insulating layer;

 Coating a photoresist on the metal film, exposing and developing the photoresist through a two-tone mask, completely retaining the photoresist corresponding to the gate, the gate line and the common electrode line region, and partially retaining the comb a photoresist corresponding to the common electrode region, removing the photoresist in the remaining region to expose the metal film;

 Etching the exposed metal film and the transparent conductive film underneath;

 The photoresist is ashed to thin the photoresist corresponding to the gate, the gate line and the common electrode line region, and expose a metal film in a region other than the gate, the gate line and the common electrode line region; An exposed metal film;

 The remaining photoresist is removed to form a pattern of gate, gate lines, common electrode lines, and comb common electrodes.

 In one example, the pixel electrode is comb-shaped.

In one example, the material of the semiconductor film is selected from the group consisting of indium gallium oxide and indium gallium tin oxide. At least one of an indium tin oxide.

 According to a second aspect of the present invention, an array substrate is provided, including a plurality of gate lines formed on a base substrate, a plurality of data lines, and a plurality of pixel units defined by a plurality of gate lines and a plurality of data lines Each of the pixel units includes a thin film transistor and a pixel electrode connected to the thin film transistor, and the pixel electrode, the data line, the active layer, the source and the drain of the thin film transistor are disposed in the same layer.

 In one example, the array substrate further includes an insulating layer disposed on the pixel electrode, the data line, the active layer, the source, and the drain; and a gate disposed above the insulating layer.

 In one example, the array substrate further includes a common electrode line disposed over the insulating layer and a comb-shaped common electrode connected to the common electrode line.

 In one example, the gate, the gate line, and the common electrode line are disposed above the common electrode. In one example, the pixel electrode is comb-shaped.

 In one example, the material of the active layer, the source, and the drain of the pixel electrode, the data line, and the thin film transistor is at least one selected from the group consisting of indium gallium oxide, indium gallium tin oxide, and indium tin oxide. .

 According to a third aspect of the invention, there is provided a display device comprising the above array substrate. DRAWINGS

 In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

 1 is a flow chart of a method of fabricating an array substrate according to an embodiment of the invention;

 2 is a flow chart of forming a pattern including an active layer, a source, a drain, a data line, and a pixel electrode, in accordance with an embodiment of the present invention;

 3 is a flow chart of forming a pattern including a gate, a gate line, a common electrode, and a common electrode line, in accordance with an embodiment of the present invention;

 4a to 16a are schematic cross-sectional views showing an array substrate of a method for fabricating an array substrate according to an embodiment of the invention;

 4b to FIG. 16b are schematic plan views of an array substrate according to an embodiment of the present invention, wherein FIGS. 4a to 16a are cross-sectional views taken along line A-A of FIG. 4b to FIG. 16b;

FIG. 17 is a schematic cross-sectional structural view of an array substrate according to an embodiment of the present invention. detailed description

 The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

 An embodiment of the present invention provides a method for fabricating an array substrate, as shown in FIG. 1, which may include:

 Step S1: forming a pattern of an active layer, a source, a drain, a data line, and a pixel electrode on the base substrate by one patterning process;

 Step S2: forming a pattern of the insulating layer;

 Step S3: forming a pattern of the gate and the gate line by one patterning process.

 In step S2, on the pattern formed in step S1, a pattern of an insulating layer is formed by depositing the insulating layer, wherein the deposition may be performed by any of the existing deposition methods, and in this embodiment, a vapor deposition method is preferred.

 In this embodiment, the array substrate may be a top gate thin film transistor, so that a pattern of gate lines and gate lines is formed in the last step S3. Step S3 may include, for example, forming a gate and a gate line using a mask by one patterning process. The patterning process includes depositing an etched material, coating, exposing, developing, etching, and stripping of the photoresist.

 In the method for fabricating the array substrate according to the embodiment, only one step of the patterning process is used in each of the steps S1 and S3, and the steps are small and simple compared to the 6-7 times of the patterning process used in the prior art. It is fast, which greatly improves production efficiency, reduces production costs and improves economic efficiency.

 In an example, as shown in FIG. 2, the step S1 may include:

 S101: As shown in Figs. 4a and 4b, a semiconductor thin film 2 is formed on the base substrate 1. For example, the semiconductor thin film 2 may be formed by various methods such as deposition by chemical vapor deposition (CVD), sputtering, or the like, which is not limited herein.

S102: as shown in FIG. 5a and FIG. 5b, coating a photoresist on the semiconductor film 2, exposing and developing the photoresist through a two-tone mask, so as to correspond to an active layer region after development. The photoresist 31 is completely retained, corresponding to the source, drain, data lines, and photoresist regions of the pixel electrode regions. The portions 33, 32, 35, and 34 are retained and have a thickness smaller than the thickness of the photoresist 31, and the photoresist corresponding to the remaining region is completely removed to expose the semiconductor thin film 2. The two-tone mask can be a halftone mask or a gray mask.

 S103: The exposed semiconductor film 2 is etched as shown in Figs. 6a and 6b.

 S104: as shown in FIG. 7a and FIG. 7b, the photoresist is ashed to remove a portion of the remaining photoresist 32, 33, 34, 35, and the photoresist 31 corresponding to the active layer region is thinned, thereby The semiconductor thin film 2 of the region other than the active layer region is exposed.

 S105: As shown in Figs. 8a and 8b, the exposed semiconductor film 2 is changed into a conductor by plasma treatment, thereby forming patterns of the source electrode 42, the drain electrode 43, the data line 46, and the pixel electrode 45. By the plasma treatment, the material of the exposed semiconductor thin film 2 is changed, and the semiconductor becomes a conductor. Due to the protection of the photoresist, the material of the semiconductor film corresponding to the active layer region does not change during the plasma treatment, and the semiconductor layer can still be used as the active layer of the thin film transistor.

 S106: removing the remaining photoresist 31 to expose the active layer 41. In this case, the active layer 41, the source electrode 42, the drain electrode 43, and the data line 46 of the thin film transistor are formed on the base substrate 1. And the pixel electrodes 45, and they are all located in the same layer.

 In the present embodiment, since the semiconductor thin film 2 is formed into a conductor by plasma processing, the source electrode 42, the drain electrode 43, the data line 46, and the pixel electrode 45 are formed, thereby forming the active layer 41, the source electrode 42, the drain electrode 43, The data line 46 and the pixel electrode 45 require only one patterning process. These components need to be completed by 3-5 patterning processes in the existing fabrication process, and each patterning process includes at least the formation of the etched material, the coating of the photoresist, the exposure and development, the etching, and the etching. Photoresist removal. Therefore, in contrast, the method for fabricating the array substrate of the present embodiment greatly reduces the complexity and cost of the manufacturing process and improves the production efficiency.

 The pixel electrode 45 may be a comb-shaped pixel electrode (or a strip-shaped, slit-like pixel electrode) as described in Figs. 8a and 8b, or may be a flat-shaped pixel electrode.

 In one example, as shown in FIG. 9a and FIG. 9b, the step S2 may include: a base substrate on which the active layer 41, the source electrode 42, the drain electrode 43, the data line 46, and the pixel electrode 45 are formed The insulating layer 5 is formed (by deposition, spin coating or printing, etc.). The insulating layer 5 may be composed of, for example, at least one of silicon nitride, silicon oxide, or silicon oxynitride.

If the array substrate in all embodiments of the present invention is used to fabricate TN (Twisted Nematic, Twist In the curved column type liquid crystal display panel, the pixel electrode 45 is preferably formed as a flat pixel electrode. Since the common electrode is located on the opposite substrate (for example, the color filter substrate) disposed opposite to the array substrate, it is not necessary to form the common electrode and the common electrode line in step S3, and only the gate electrode and the gate line are formed. In one example, step S3 may include: depositing a gate metal film on the base substrate 1 on which the insulating layer 5 is formed, and then forming a pattern of the gate and the gate lines by a patterning process, the gate and the gate lines are integrally formed, and the gate It is formed above the corresponding active layer 41.

 When the fabrication method of the present embodiment is used to fabricate a multi-dimensional electric field type (e.g., ADS type or IPS type) array substrate, it is also necessary to form a comb-shaped common electrode and a common electrode line connecting the comb-shaped common electrodes on the substrate. In one example, the step S3 may include: forming a pattern of the gate and the gate line by one patterning process, and a pattern of the comb-shaped common electrode and the common electrode line. As shown in FIG. 3, the step S3 may include, for example:

 S301: As shown in FIGS. 10a to 10b, a transparent conductive film 6 is formed (by deposition, spin coating, printing, etc.) on the insulating layer 5, and is shown on the transparent conductive film 6 as shown in FIGS. 11a to 11B. Forming (by deposition, spin coating or printing, etc.) a metal film 7;

 S302: as shown in FIG. 12a to FIG. 12b, a photoresist is coated on the metal thin film 7, and the photoresist is exposed and developed through a two-tone mask to make a gate, a gate line and a common electrode line. The photoresists 81 and 82 corresponding to the regions are completely retained, so that the photoresist 83 corresponding to the comb-shaped common electrode region is partially retained, and the thickness of the photoresist 83 is smaller than the thickness of the photoresists 81 and 82, and the light in the remaining region is removed. The glue is peeled to expose the metal film 7.

 S303: The exposed metal thin film 7 and the transparent conductive film 6 are etched as shown in Figs. 13a to 13b.

S304: as shown in FIG. 14a to FIG. 14b, removing the photoresist 83 corresponding to the comb-shaped common electrode region by using an ashing process, and thinning the photoresists 81 and 82 corresponding to the gate, the gate lines, and the common electrode line region, Thereby exposing a metal thin film 7 in a region other than the gate, the gate line and the common electrode line region;

 S305: etching the exposed metal film 7 as shown in FIG. 15a to FIG. 15b;

 S306: removing the remaining photoresists 81 and 82 to form a gate as shown in FIGS. 16a to 16b.

101. A pattern of the gate line 104, the comb-shaped common electrode 102, and the common electrode line 103. In the present embodiment, the gate electrode 101 is composed of a gate metal portion in which the gate line 104 overlaps the active layer 41 and a transparent conductive film 6 therebelow.

As the metal thin film 7, a single-layer film formed of a metal such as Cr, W, Ti, Ta, Mo, Al, Cu or the like and an alloy thereof, or a composite film composed of a plurality of metal thin films can be used. Transparent conductive film 6 ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) can be used.

 In this embodiment, the gate electrode 101, the gate line 104, and the common electrode line 103 can be considered to be only composed of a metal thin film, and the gate electrode 101, the gate line 104, and the common electrode line 103 are located at the comb-shaped common electrode 102. Above. It is also considered that the gate electrode 101, the gate line 104, and the common electrode line 103 are each composed of two parts, and a metal thin film and a transparent conductive film are sequentially arranged from top to bottom. In this case, since both the metal thin film and the transparent conductive film are conductors, not only the conductivity of the gate electrode 101, the gate line 104, and the common electrode line 103 is maintained, but also the light-shielding property of the metal film is maintained.

 In the present embodiment, the gate electrode 101, the gate line 104, the common electrode 102, and the common electrode line 103 are formed by one patterning process, which greatly reduces the complexity and cost of the fabrication process, and improves the production efficiency.

 The material of the semiconductor thin film 2 may be at least one of indium gallium oxide, indium gallium tin oxide, and indium tin oxide. Indium gallium oxide (IGZO) is preferred because of its high carrier mobility, so that the thin film transistor formed using the material has a fast reaction rate, thereby increasing the reaction rate of the array substrate.

 In summary, in the method for fabricating an array substrate according to the embodiment, the fabrication of the array substrate is completed by only two patterning processes, which is simple and quick to manufacture, high in production efficiency, reduces the number of masks, and reduces light. Loss of consumables such as glue and developer, which reduces manufacturing costs and improves production efficiency and economic efficiency.

Another embodiment of the present invention further provides an array substrate, wherein the array substrate is fabricated by using the above array substrate fabrication method. As shown in FIG. 17, the array substrate may include: a plurality of gate lines formed on the base substrate 1, a plurality of data lines (not shown), and a plurality of gate lines and a plurality of data lines intersecting each other. a pixel unit (not shown); wherein each pixel unit includes a thin film transistor (not shown) and a pixel electrode 25 connected to the thin film transistor, the pixel electrode 25, the data line, and the thin film transistor are active Layer 21, source 22 and drain 23 are on the same layer. However, in the prior art, the active layer is usually located above the source 22 and the drain 23. As shown in FIG. 17, the pixel electrode 25 is on the surface of the base substrate 1. Since the array substrate described in this embodiment has the active layer 21, the source 22, the drain 23, the data line, and the pixel electrode 25 disposed on the same layer, the fabrication process can be completed only by one patterning process, so the fabrication process is simple and fast. And reduce the number of masks, reduce the loss of photoresist, developer and other consumables, thereby reducing manufacturing costs and improving Production efficiency and economic benefits.

 In one example, the array substrate may further include an insulating layer 29 on the pixel electrode 25, the active layer 21, the source 22, the drain 23, and the data line; and a gate above the insulating layer 29. Extreme 27. The gate 27 and the gate line are integrally formed, and the gate line transmits a signal for turning on or off the thin film transistor.

 In the array substrate described in this embodiment, the thin film transistor is of a top gate type. If the array substrate of the present embodiment is used to fabricate a TN-type liquid crystal display panel, the common electrode disposed opposite to the pixel electrode 25 is disposed on a counter substrate (such as a color filter substrate) disposed opposite to the array substrate, so that the array is It is not necessary to make a common electrode and a common electrode line in the substrate, but only a gate electrode and a gate line need to be formed, and can be fabricated by a common patterning process.

 When the array substrate described in this embodiment is used to fabricate a multi-dimensional electric field type (for example, ADS type or IPS type) liquid crystal display panel, a common electrode and a common electrode line for supplying a voltage to the common electrode are also required to be formed on the array substrate. And the common electrode is a comb-shaped common electrode. In this case, the array substrate of the embodiment may further include a common electrode line 28 disposed above the insulating layer 29 and a comb-shaped common electrode 26 connected to the common electrode line 28. Further, the gate 27, the gate line and the common electrode line 28 are located above the common electrode 26.

 With the array substrate described in this embodiment, the formation of the common electrode 26, the common electrode line 28, the gate 27 and the gate line is completed by only one patterning process, which is easy to manufacture, low in cost of consumables and equipment, and economical. Good benefits and other advantages.

 In one example, as shown in FIG. 17, the pixel electrode 25 in the present embodiment is a comb-shaped pixel electrode 25. In other examples, the pixel electrode 25 may also be a plate electrode located within the pixel area.

 The material of the pixel electrode 25, the data line, and the active layer 21, the source 22, and the drain 23 of the thin film transistor may be selected from at least one of indium gallium oxide, indium gallium tin oxide, and indium tin oxide. . Preferably, they are all made of IGZO.

 The active layer 21 is a semiconductor layer, and the IGZO itself is a semiconductor, and the source 21, the drain 22, the data line, and the pixel electrode 25 are all conductors. Therefore, in the manufacturing process, the IGZO is converted into a conductor by using a laser process. Ensure the quality of the array substrate.

 In summary, the array substrate described in this embodiment has the advantages of simple structure, low manufacturing cost, and good economic efficiency.

In the above embodiments of the array substrate and the method for fabricating the same, the top gate thin film transistor is taken as an example. Ming, but not limited to this. For the array substrate of the bottom gate thin film transistor, it is only necessary to exchange the active layer 21, the source 22, the drain 23, the pixel electrode 25 and the data line in the same layer in FIG. 17 with the layer above the insulating layer 29, That is, the active layer 21, the source 22, the drain 23, the pixel electrode 25, and the data line are located above the insulating layer 29, and the gate 27, the gate line, the common electrode 26, and the common electrode line 28 are located under the insulating layer 29. In the manufacturing method, it is only necessary to adjust the order of the above steps S1 and S3, and the steps S3-S2-S1 can be made, and the manufacturing process of each step is unchanged.

 Another embodiment of the present invention further provides a display device comprising the array substrate fabricated by the method for fabricating the array substrate of the embodiment of the invention, or the array substrate according to the embodiment of the invention. The display device may be any product or component having a display function such as an electronic paper, a liquid crystal display panel, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

 In the array substrate, the manufacturing method thereof and the display device of the above-mentioned embodiments of the present invention, the fabrication of the array substrate is completed only by two patterning processes with respect to the conventional fabrication process, so that the fabrication steps are few and simple, and the fabrication is greatly reduced. The complexity and cost, which greatly improve production efficiency and economic efficiency.

 The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

claims 1. A method for manufacturing an array substrate, including: Patterns of active layers, source electrodes, drain electrodes, data lines and pixel electrodes are formed on the base substrate through a patterning process; forming a pattern of insulating layers; and The patterns of gate electrodes and gate lines are formed through a patterning process. 2. The array substrate manufacturing method according to claim 1, wherein the step of forming the pattern of the active layer, source electrode, drain electrode, data line and pixel electrode on the base substrate through a patterning process includes: Form a semiconductor thin film on the base substrate; Coat photoresist on the semiconductor film, expose and develop the photoresist through a two-tone mask, completely retain the photoresist corresponding to the active layer area, and partially retain the source, drain, and data The photoresist corresponding to the lines and pixel electrode areas is completely removed to expose the semiconductor film; Etching the exposed semiconductor film; Ashing the photoresist to thin the photoresist corresponding to the active layer area and expose the semiconductor film in areas other than the active layer area; The exposed semiconductor film is turned into a conductor through plasma treatment to form patterns of source electrodes, drain electrodes, data lines and pixel electrodes; and Remove remaining photoresist. 3. The array substrate manufacturing method according to claim 1 or 2, wherein the step of forming the pattern of the gate electrode and the gate line through a one-time patterning process further includes forming the pattern of the common electrode line and the comb-shaped common electrode. 4. The array substrate manufacturing method according to claim 3, wherein the step of forming the patterns of gate electrodes and gate lines, as well as the patterns of common electrode lines and comb-shaped common electrodes through one patterning process includes: A transparent conductive film and a metal film are formed in sequence on the insulating layer; Coat photoresist on the metal film, expose and develop the photoresist through a two-tone mask, completely retain the photoresist corresponding to the gate electrode, gate line and common electrode line area, and partially retain the photoresist. Leave the photoresist corresponding to the comb-shaped common electrode area, and remove the photoresist in the remaining area to expose the metal film; Etch the exposed metal film and the transparent conductive film underneath; Ashing the photoresist to thin the photoresist corresponding to the gate electrode, gate line and common electrode line area, exposing the metal film in the area except the gate electrode, gate line and common electrode line area; etching Corrosion of exposed metal films; The remaining photoresist is removed to form patterns of gate electrodes, gate lines, common electrode lines and comb-shaped common electrodes. 5. The array substrate manufacturing method according to any one of claims 1 to 4, wherein the pixel electrode is a Hashio. 6. The array substrate manufacturing method according to any one of claims 2 to 5, wherein the semiconductor thin film is made of at least one selected from the group consisting of indium gallium oxide, indium gallium tin oxide, and indium tin oxide. 7. An array substrate, including a plurality of gate lines, a plurality of data lines formed on a base substrate, and a plurality of pixel units defined by the intersections of the plurality of gate lines and the plurality of data lines; wherein each pixel unit includes a thin film The transistor and the pixel electrode connected to the thin film transistor, the pixel electrode, the data line, the active layer, the source electrode and the drain electrode of the thin film transistor are arranged on the same layer. 8. The array substrate according to claim 7, wherein the array substrate further comprises an insulating layer disposed on the pixel electrode, data line, active layer, source electrode and drain electrode; and The upper gate. 9. The array substrate according to claim 8, wherein the array substrate further includes a 10. The array substrate according to claim 9, wherein the gate electrode, gate line and common electrode line are arranged above the common electrode. 11. The array substrate according to any one of claims 7-10, wherein the pixel electrode is comb-shaped. 12. The array substrate according to any one of claims 7 to 10, wherein the material of the pixel electrode, the data line and the active layer, source electrode and drain electrode of the thin film transistor is selected from the group consisting of indium gallium oxide, indium gallium oxide and indium gallium oxide. At least one of tin oxide and indium tin oxide. 13. A display device, comprising the array substrate according to any one of claims 7-12.