[go: up one dir, main page]

WO2016192211A1 - Dispositif et procédé pour envoyer une interconnexion inter-puces, dispositif et procédé pour recevoir une interconnexion inter-puces, et système - Google Patents

Dispositif et procédé pour envoyer une interconnexion inter-puces, dispositif et procédé pour recevoir une interconnexion inter-puces, et système Download PDF

Info

Publication number
WO2016192211A1
WO2016192211A1 PCT/CN2015/087690 CN2015087690W WO2016192211A1 WO 2016192211 A1 WO2016192211 A1 WO 2016192211A1 CN 2015087690 W CN2015087690 W CN 2015087690W WO 2016192211 A1 WO2016192211 A1 WO 2016192211A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
inter
processor
conversion circuit
bit
Prior art date
Application number
PCT/CN2015/087690
Other languages
English (en)
Chinese (zh)
Inventor
赵守磊
于岗
Original Assignee
青岛海信信芯科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 青岛海信信芯科技有限公司 filed Critical 青岛海信信芯科技有限公司
Publication of WO2016192211A1 publication Critical patent/WO2016192211A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication

Definitions

  • the present invention relates to the field of integrated circuit technologies, and in particular, to a transmitting and receiving device for inter-chip interconnection, and a transmitting and receiving method and system.
  • SOC System On Chip
  • ICs integrated circuits
  • IS integrated systems
  • the SOC usually uses an FPGA (Field-Programmable Gate Array) to customize the logic function module. Therefore, the FPGA function verification must be performed during the SOC development process. However, as the SOC logic size becomes larger and larger, it is difficult for a single FPGA to realize the function of the entire SOC. Therefore, in FPGA verification, functional division must be performed, and the functions of the SOC are separately verified in two or more FPGAs.
  • FPGA Field-Programmable Gate Array
  • the SOC function is realized by two FPGA interconnections of FPGA_1 and FPGA_2, and at this time, FPGA_1 and FPGA_2 are directly interconnected. If you need to send the i-bit signal (Signal_1 to Signal_i) from FPGA_1 to FPGA_2, you need to send the i-bit signal through i pins, and FPGA_2 also needs i pins to receive the i-bit signal. At this time, i pins are required in both FPGA_1 and FPGA_2, as shown in Figure 1.
  • Embodiments of the present invention provide a method and system for transmitting and receiving an inter-chip interconnect, and a transmitting and receiving method, and a system for reducing a used pin and reducing a signal connected between at least two FPGAs when inter-chip interconnection is implemented.
  • the complexity of the traces of the lines which in turn reduces the complexity of inter-chip interconnects.
  • an embodiment of the present invention provides an apparatus for transmitting inter-chip interconnection, including: a parallel-serial data conversion circuit, at least one transmission pin; an output end of the parallel-serial data conversion circuit and the at least one transmission lead a pin connection; an input end of the parallel data conversion circuit is coupled to the data transmission processor; and the parallel data conversion circuit is configured to acquire n-bit parallel data from the data transmission processor according to a vld/rdy handshake protocol Converting the n-bit parallel data into m-bit transmission data, and transmitting the m-bit transmission data to the receiving device of the inter-chip interconnect through the m transmit pins according to the vld/rdy handshake protocol; n is an integer greater than 1, and m is an integer greater than 0 and less than n.
  • an embodiment of the present invention provides a receiving device for inter-chip interconnection, including: at least one receiving pin, a serial-to-parallel data conversion circuit; an input end of the serial-to-parallel data conversion circuit and the at least one receiving lead a pin connection, an output end of the serial-to-parallel data conversion circuit is connected to a data processor; the serial-to-parallel data conversion circuit is configured to acquire an inter-chip interconnection transmitting device through m receiving pins according to a vld/rdy handshake protocol Transmitted m-bit transmission data, converting the m-bit transmission data into n-bit parallel Data, and transmitting the n-bit parallel data to a data processor according to a vld/rdy handshake protocol; the m is an integer greater than 0; the n is an integer greater than m.
  • an embodiment of the present invention provides a method for transmitting an inter-chip interconnect, including: an inter-chip interconnecting transmitting device acquires n-bit parallel data according to a vld/rdy handshake protocol; the n is an integer greater than 1; The n-bit parallel data is converted into m-bit transmission data; the m is an integer greater than 0 and less than n; and the m-bit transmission data is sent to the m transmit pins according to the vld/rdy handshake protocol to Receiver for inter-chip interconnection.
  • an embodiment of the present invention provides a method for receiving an inter-chip interconnection, including: receiving, by an inter-chip interconnect, an m-bit transmitted by a transmitting device of an inter-chip interconnect through m receiving pins according to a vld/rdy handshake protocol. Transmitting data; the m is an integer greater than 0; converting the m-bit transmission data into n-bit parallel data, and transmitting the n-bit parallel data to the data processing according to the vld/rdy handshake protocol And causing the data processor to process the n-bit parallel data; the n is an integer greater than m.
  • an embodiment of the present invention provides a system for inter-chip interconnection, including: a device for transmitting inter-chip interconnection, and a receiving device for inter-chip interconnection; wherein the transmitting device for inter-chip interconnection is the above embodiment
  • the transmitting device for inter-chip interconnection; the receiving device for inter-chip interconnection is the receiving device for inter-chip interconnection described in the above embodiment.
  • the embodiment of the invention provides a transmitting and receiving device for inter-chip interconnection, a transmitting and receiving method and a system, and a transmitting device for inter-chip interconnection includes: a parallel data conversion circuit, at least one transmitting pin; wherein, parallel data conversion The input of the circuit is coupled to the data transmitting processor, and the output of the serial data conversion circuit is coupled to at least one of the transmit pins.
  • a parallel data conversion circuit for acquiring n-bit parallel data from the data transmission processor according to the vld/rdy handshake protocol, converting n-bit parallel data into m-bit transmission data, and m according to the vld/rdy handshake protocol
  • the bit transfer data is sent to the receiving device of the inter-chip interconnect via m transmit pins.
  • the transmitting device for inter-chip interconnection can convert the n-bit parallel data to be transmitted to the m-bit transmission data through the parallel-serial data conversion circuit, and further, the m-bit transmission data can be transmitted to the slice by only m transmission pins. Interconnected receiving device.
  • the transmitting device for inter-chip interconnection needs n transmitting pins to transmit n-bit parallel data to the receiving device of the inter-chip interconnection.
  • the data can be transmitted only by requiring m transmit pins, thereby reducing the use of pins when inter-chip interconnection is implemented, thereby reducing the complexity of the traces of the signal lines connected between at least two FPGAs. This reduces the complexity of inter-chip interconnects.
  • FIG. 1 is a schematic structural diagram of interconnection between FPGAs in the prior art
  • FIG. 2 is a schematic structural diagram of a device for transmitting inter-chip interconnection according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of another apparatus for transmitting inter-chip interconnection according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of another apparatus for transmitting inter-chip interconnection according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another apparatus for transmitting inter-chip interconnection according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a receiving device for inter-chip interconnection according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of another apparatus for receiving inter-chip interconnection according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another apparatus for receiving inter-chip interconnection according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic flowchart of a method for sending inter-chip interconnection according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic flowchart diagram of a method for receiving inter-chip interconnection according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a system for inter-chip interconnection according to an embodiment of the present invention.
  • An embodiment of the present invention provides a transmitting device for inter-chip interconnection. As shown in FIG. 2, the present invention includes: a parallel data conversion circuit 11 and at least one transmitting pin 12.
  • the output of the parallel data conversion circuit 11 is connected to at least one of the transmission pins 12.
  • the input of the parallel data conversion circuit 11 is connected to a data transmission processor.
  • the parallel data conversion circuit 11 is configured to acquire n-bit parallel data from the data transmission processor according to the vld/rdy handshake protocol, and convert the n-bit parallel data into m-bit transmission data, and according to the vld/rdy handshake protocol
  • the m-bit transmission data is transmitted through m transmission pins 12 to the inter-chip interconnected receiving device.
  • n is an integer greater than one.
  • m is an integer greater than 0 and less than n.
  • the parallel data in the embodiment of the present invention refers to data including data to be processed, and/or control data, and/or address data.
  • Transmission data also refers to data containing data to be processed, and/or control data, and/or address data.
  • n-bit parallel data can be generated according to actual needs.
  • This n-bit parallel data is sent to the inter-chip interconnected transmitting device.
  • the parallel-serial data conversion circuit 11 in the inter-chip interconnection transmitting apparatus can determine the number of bits of the transmission data based on the number of transmission pins that can be used by the inter-chip interconnection transmitting apparatus, that is, determine m.
  • the n-bit parallel data is divided into k groups, each group of m bits, so that each group of data is used as transmission data, and n-bit parallel data can be converted into m-bit transmission data, and the m-bit transmission data is transmitted through m transmissions.
  • the foot is sent to the receiving device of the inter-chip interconnection.
  • the transmission data can be adjusted according to the transmit pin data that can be used, so that the adjusted transmission data is sent through the transmit pin that can be used.
  • Send enhance the flexibility of inter-chip interconnection, thus reducing the complexity of inter-chip interconnection.
  • k is an integer greater than zero.
  • n-bit parallel data is divided into k groups and each group is m bits
  • the last group can be processed by zero-padding. Fill in the m position by zero padding.
  • the components are usually connected by an on-chip bus, that is, the data transmitting processor is connected to the parallel-serial data conversion circuit 11 through the on-chip bus.
  • the protocol of the on-chip bus for example, AXI (Advanced eXtensible Interface) protocol, APB (Advanced Peripheral Bus) protocol, etc.
  • AXI Advanced eXtensible Interface
  • APB Advanced Peripheral Bus
  • the vld (valid, valid) / rdy (ready) handshake protocol is a protocol for transmitting the respective current states of each other before the data is transmitted by different components.
  • the vld/rdy handshake protocol is a protocol compatible with the on-chip bus protocol.
  • the vrd_s signal is mainly transmitted, and the rdy_s signals transmit their respective current states to each other and perform data transmission through the data channel.
  • the vld_s signal is an identification signal of whether the data sent by the sending end is valid data. For example, when the vld_s signal is 1, it indicates that the data sent by the sender is valid data. When the vld_s signal is 0, it means that the data sent by the sender is invalid data.
  • the rdy_s signal is an identification signal of whether the receiving end can receive the transmitted data. For example, when the rdy_s signal is 1, it means that the receiving end can receive the transmitted data. When the rdy_s signal is 0, it means that the receiving end cannot receive the transmitted data.
  • Data channel for transferring data That is to say, the data to be transmitted is transmitted to other components through this data channel.
  • the last_s signal can also be passed in the vld/rdy handshake protocol.
  • the last_s signal is the last data indication identification signal of a transmission. Since one transmission can transmit a plurality of data, and the last data is identified by the signal, the data of the last_s signal carried by the receiving device data can be notified to be the last data, and the transmission of the current data is completed. In this way, the internal states of the synchronous transmitting device and the receiving device that can be interconnected between the chips are provided. The stability of the transmission.
  • last_s signal is an optional signal, and in the vld/rdy handshake protocol, there may be no last_s signal, which can reduce the occupied transmit pin.
  • the vld_s signal, the rdy_s signal and the last_s signal in the vld/rdy handshake protocol need to be transmitted using a different transmit pin than the transmitted data.
  • the inter-chip interconnected transmitting device needs to use the m-bit transmit pin to transmit the transmitted data, the other three transmit pins are required to transmit the vld_s signal, the rdy_s signal, and the last_s signal.
  • the parallel data conversion circuit is configured to acquire n-bit parallel data from the data transmission processor according to the vld/rdy handshake protocol. That is, the parallel data conversion circuit 11 receives the n-bit parallel data transmitted by the data transmission processor, and first receives the vld_s sent by the data transmission processor to the parallel data conversion circuit 11 indicating that the data transmitted by the transmitting end is valid data. The signal, at this time, after the parallel data conversion circuit 11 receives the vld_s signal, it can learn from the vld_s signal that the data sent by the data transmission processor is valid data.
  • the parallel data conversion circuit 11 transmits to the data transmission processor a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the rdy_s signal can be used to know that the parallel data conversion circuit 11 can receive the transmitted data.
  • the data transmission processor can pass the data channel. The n-bit parallel data is sent to the parallel-serial data conversion circuit 11.
  • the parallel data conversion circuit 11 After receiving the n-bit parallel data, the parallel data conversion circuit 11 changes the rdy_s signal sent by the data transmission processor to the receiving end to receive the transmitted data to a rdy_s signal indicating that the receiving end cannot receive the transmitted data, and transmits To the data sending processor. At this time, the data transmission processor knows from the received rdy_s signal that the parallel data conversion circuit 11 cannot receive the parallel data, and at this time, the data transmission processor no longer transmits the data to the parallel data conversion circuit 11. After the parallel data conversion circuit 11 transmits data to the n-bit parallel data, it can be divided into k groups of m bits each.
  • the parallel data conversion circuit 11 transmits the m-bit transmission data to the receiving device connected to the inter-chip via the m transmission pins 12 according to the vld/rdy handshake protocol. That is, the parallel data conversion circuit 11 transmits the m-bit transmission data to the m transmission pins to Before the inter-chip interconnected receiving device, the receiving device that communicates to the inter-chip interconnect through a transmitting pin first indicates that the data sent by the transmitting end is the vld_s signal of the valid data, and the receiving device that receives the inter-chip interconnect receives the vld_s signal. Thereafter, the data transmitted to the parallel data conversion circuit 11 can be known as valid data based on the vld_s signal.
  • the parallel data conversion circuit 11 transmits a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the parallel data conversion circuit 11 transmits a set of transmission data to the receiving device connected to the inter-chip when the rdy of the receiving device connected to the inter-chip is instructed to receive the transmitted data until the k-group transmission data is transmitted to the slice. Interconnected receiving device.
  • the parallel data conversion circuit 11 may generate a last signal when transmitting the last set of transmission data, to characterize the data as the last transmission data, and send it together with the last group of transmission data to the receiving device of the inter-chip interconnection. At this time, it is necessary to transmit data to m bits through m transmit pins, and send the last signal through another transmit pin.
  • the parallel data conversion circuit 11 can transmit the k sets of transmission data to the receiving device of the inter-chip interconnection through the m transmission pins, and can change the rdy_s signal transmitted to the data transmission processor indicating that the receiving end cannot receive the transmitted data. For example, the rdy_s signal indicating that the receiving end can receive the transmitted data is sent to the data transmitting processor.
  • the vld_s signal when the vld_s signal is a high level signal indicating that the data transmitted by the transmitting end is valid data, the vld_s signal received by the parallel data converting circuit 11 is a high level signal.
  • the rdy_s signal is a high level signal indicating that the receiving end can receive the transmitted data, the rdy_s signal received by the data transmitting processor is a high level signal.
  • the vld_s signal may also indicate that the data sent by the transmitting end is valid data by other signals, for example, by a low level signal, which is not limited by the present invention.
  • the rdy_s signal can also indicate that the receiving end can receive the transmitted data through other signals, for example, by using a low level signal, which is not limited by the present invention.
  • the vld_s signal indicating that the data sent by the transmitting end is valid data may be the same signal as the rdy_s signal indicating that the receiving end can receive the transmitted data, and may be different signals, for example, the vld_s signal passes the low level.
  • Signal The data sent by the transmitting end is indicated as valid data, and the rdy_s signal indicates that the receiving end can receive the transmitted data through a high level signal.
  • the invention is not limited thereto.
  • the parallel data conversion circuit 11 can know the data transmission processing according to the received vld_s signal.
  • the data to be transmitted by the device is invalid data, so the parallel data conversion circuit 11 does not process the data transmitted by the data transmission processor.
  • the parallel data conversion circuit 11 sends a rdy_s signal indicating that the receiving end cannot receive the transmitted data to the data transmission processor, the data transmission processor can know that the parallel data conversion circuit 11 cannot receive the transmitted data according to the received rdy_s signal. Therefore, the data transmitting processor no longer transmits the parallel data to the parallel data conversion circuit 11.
  • n of the n-bit parallel data is predetermined. It is related to the on-chip bus used.
  • the width of the transmission data can be determined based on the number of transmission pins that can be used by the inter-chip interconnecting device and the number of receiving pins that can be used by the inter-chip interconnected receiving device. If only six pins are available for the inter-chip interconnecting device and eight pins are available for the inter-chip interconnecting device, the two pins in the inter-chip interconnecting device can be used as the transmitting vld_s signal.
  • the inter-chip interconnecting transmitting apparatus can use 128 to 4 parallel-serial data converting circuits 11 to convert 128-bit parallel data into parallel 4-bit transfer data by the parallel-serial data converting circuit 11, and transmit it to the 4-bit transmitting pin through four transmitting pins.
  • Receiver for inter-chip interconnection The receiving device to the inter-chip interconnect can use a pin as a receiving pin for receiving the vld_s signal, and receive the vld_s signal sent by the transmitting device of the inter-chip interconnect through the receiving pin.
  • the other pin is used as a transmit pin for transmitting the rdy_s signal, and the rDY_s signal is sent to the inter-chip interconnecting device through the transmit pin.
  • the rDY_s signal is sent to the inter-chip interconnecting device through the transmit pin.
  • four pins are selected as receive pins for receiving transmission data.
  • the transmitting device for inter-chip interconnection further includes: Asynchronous FIFO (First Input First Out, first in first out) processor 13.
  • Asynchronous FIFO First Input First Out, first in first out
  • the input of the parallel data conversion circuit 11 and the data transmission processor include: the input of the asynchronous FIFO processor 13 is connected to the data transmission processor, the output of the asynchronous FIFO processor 13 and the input of the parallel data conversion circuit 11 connection.
  • the asynchronous FIFO processor 13 is configured to acquire and store n bits of parallel data from the data transmitting processor.
  • the parallel data conversion circuit 11 is specifically configured to acquire n-bit parallel data from the asynchronous FIFO processor 13 according to the vld/rdy handshake protocol.
  • the asynchronous FIFO processor 13 is disposed between the data transmitting processor and the parallel data conversion 12, and the data transmitting processor can send the generated n-bit parallel data to the asynchronous FIFO processor 13, and the asynchronous FIFO processor 13 Store. And, the parallel data conversion 12 acquires n-bit parallel data to be converted from the asynchronous FIFO processor 13.
  • the data transmission processor is spaced apart from the parallel data conversion 12 by the asynchronous FIFO processor 13, and the operation clock frequency of the data transmission processor and the parallel data conversion circuit 11 can be different.
  • the data transmission rate of the data transmission processor and the parallel data conversion circuit 11 can be different, so that the data transmission rate of the parallel data conversion circuit 11 and the subsequent stage processor can be improved, thereby improving the efficiency of data transmission;
  • the transmission processor is out of synchronization with the running clock frequency of the parallel data conversion circuit 11, and the operating clock frequency of the parallel data conversion circuit 11 can be dynamically adjusted according to the frequency actually supported by the transmission pin, and the flexibility and reliability are also improved.
  • the parallel data conversion circuit 11 acquires n-bit parallel data according to the vld/rdy handshake protocol, meaning that the parallel data conversion circuit 11 acquires n-bit parallel data from the asynchronous FIFO processor 13 in accordance with the vld/rdy handshake protocol. That is, before the asynchronous FIFO processor 13 transmits n-bit parallel data to the parallel-to-serial data conversion circuit 11, the parallel data conversion circuit 11 first transmits a vld_s signal indicating that the data transmitted by the transmitting end is valid data, and After receiving the vld_s signal, the string data conversion circuit 11 can learn from the vld_s signal that the data sent to it by the asynchronous FIFO processor 13 is valid data.
  • the parallel-serial data conversion circuit 11 can receive the valid data transmitted from the asynchronous FIFO processor 13, the parallel-serial data conversion circuit 11 transmits to the asynchronous FIFO processor 13 a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the asynchronous FIFO processor 13 can learn that the parallel data conversion circuit 11 can receive the transmitted data according to the rdy_s signal.
  • the asynchronous FIFO processor 13 can pass the data channel.
  • the n-bit parallel data is sent to the parallel-serial data conversion circuit 11, and the parallel-serial data conversion circuit 11 acquires n-bit parallel data to be converted from the asynchronous FIFO processor 13.
  • the asynchronous FIFO processor 13 acquires n-bit parallel data from the data transmitting processor, it can also be acquired according to the vld/rdy handshake protocol.
  • the data transmitting processor Before transmitting the n-bit parallel data to the asynchronous FIFO processor 13, the data transmitting processor first sends a vld_s signal indicating that the data sent by the transmitting end is valid data to the asynchronous FIFO processor 13, and the asynchronous FIFO processor 13 receives the data. After the vld_s signal, the data sent by the data sending processor to the vld_s signal can be known as valid data.
  • the asynchronous FIFO processor 13 sends a rdy_s signal to the data transmitting processor indicating that the receiving end can receive the transmitted data.
  • the data transmitting processor receives the rdy_s signal sent by the asynchronous FIFO processor 13
  • the n-bit parallel data is sent to the asynchronous FIFO processor 13 through the data channel.
  • the data sending processor in the embodiment of the present invention may be a processor integrated in the transmitting device of the inter-chip interconnect, or may be a processor independent of the inter-chip interconnecting transmitting device, which is not Make restrictions.
  • transposition of the inter-chip interconnect further includes: a synchronous FIFO processor 14.
  • the output of the parallel data conversion circuit 11 and the at least one transmit pin 12 are connected to include:
  • the input of the synchronous FIFO processor 14 is coupled to the output of the parallel data conversion circuit 11, and the output of the synchronous FIFO processor 14 is coupled to at least one of the transmit pins 12.
  • the parallel data conversion circuit 11 is specifically configured to transmit the m-bit transmission data to the synchronous FIFO processor 14 according to the vld/rdy handshake protocol.
  • the synchronous FIFO processor 14 is configured to receive and store m-bit transmission data, and send the m-bit transmission data through the m transmission pins 12 according to the vld/rdy handshake protocol. Receiver to inter-chip interconnect.
  • the synchronous FIFO processor 14 is disposed between the parallel data conversion circuit 11 and the transmission pin 12, and the serial data conversion circuit 11 can transmit the converted m-bit transmission data to the synchronous FIFO processor 14, by synchronization.
  • the FIFO processor 14 performs storage. And when the transmission data can be transmitted through the transmission pin 12, the synchronous FIFO processor 14 transmits its stored m-bit transmission data to the receiving device of the inter-chip interconnection through the m transmission pins 12.
  • the parallel data conversion circuit 11 is spaced apart from the transmission pin 12 by the synchronous FIFO processor 14, so that the data transmission rate can be improved.
  • the synchronous FIFO processor 14 transmits the m-bit transmission data to the receiving device of the inter-chip interconnect through the m transmitting pins 12 according to the vld/rdy handshake protocol, that is, the synchronous FIFO processor 14 transmits the inter-chip interconnected receiving device.
  • the vld_s signal indicating that the data sent by the transmitting end is valid data is sent to the receiving device connected to the inter-chip.
  • the inter-chip interconnecting receiving device can learn according to the vld_s signal.
  • the data sent to it by the synchronous FIFO processor 14 is valid data.
  • the receiving device of the inter-chip interconnection transmits to the synchronous FIFO processor 14 a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the rdy_s signal can be used to learn that the receiving device of the inter-chip interconnect can receive the transmitted data.
  • the synchronous FIFO processor 14 can pass the m. Transmit pins 12 transmit m-bit transmission data to the receiving device of the inter-chip interconnect.
  • the rdy_s signal used by the receiving device of the inter-chip interconnect is directly transmitted to the parallel data conversion circuit 11.
  • the delay time of the rdy_s signal from the receiving device of the inter-chip interconnection to the parallel data conversion circuit 11 is relatively large, and the running clock frequency is small, that is, the running clock period is large to ensure that the rdy_s signal arrives and the data is converted in one cycle. Circuit 11, the data transmission rate is low.
  • the delay time of the rdy_s signal is directly transmitted from the receiving device of the inter-chip interconnect to the synchronous FIFO processor 14, with respect to the rdy_s signal from the receiving device connected to the chip to the parallel data conversion circuit.
  • the delay time of 11 is reduced; at the same time, the synchronous FIFO processor 14 regenerates the rdy_s signal to the parallel data conversion circuit 11, from the synchronous FIFO processor 14 to the parallel data conversion circuit 11.
  • the time delay relative to the rdy_s signal from the receiving device connected to the parallel data conversion circuit 11 is also reduced, so that the clock frequency is operated at this time, from the receiving device connected to the inter-chip to the rdy_s signal.
  • the operating clock frequency at the time of the string data conversion circuit 11 is increased, that is, the running clock period is reduced, so that the data transfer rate is improved by the synchronous FIFO processor 14.
  • the parallel data conversion circuit 11 sends the converted m-bit transmission data to the synchronous FIFO processor 14 according to the vld/rdy handshake protocol, that is, the parallel data conversion circuit 11 sends the data to the synchronous FIFO processor 14.
  • the synchronous FIFO processor 14 Before transmitting the m-bit data, the synchronous FIFO processor 14 first sends a vld_s signal indicating that the data sent by the transmitting end is valid data. After receiving the vld_s signal, the synchronous FIFO processor 14 can learn and serialize the vld_s signal according to the vld_s signal. The data to which the data conversion circuit 11 transmits is valid data.
  • the synchronous FIFO processor 14 transmits to the parallel data conversion circuit 11 a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the parallel data conversion circuit 11 receives the rdy_s signal sent by the synchronous FIFO processor 14, the rdy_s signal can be used to know that the synchronous FIFO processor 14 can receive the transmitted data.
  • the parallel data conversion circuit 11 can pass the data.
  • the channel transmits the m-bit transmission data to the synchronous FIFO processor 14.
  • the transmitting device for inter-chip interconnection described above further includes an IOP (I/O Processor) 15 as shown in FIG. 5.
  • IOP I/O Processor
  • the output of the synchronous FIFO processor 14 is coupled to the at least one transmit pin 12.
  • the output of the synchronous FIFO processor 14 is coupled to the input of the IOP 15, and the output of the IOP 15 is coupled to at least one transmit pin 12.
  • the synchronous FIFO processor 14 is specifically configured to send m-bit transmission data to the IOP 15 according to the vld/rdy handshake protocol.
  • the IOP 15 is configured to receive m bits of transmission data and transmit the m bits of transmission data to the receiving devices of the inter-chip interconnect using the m transmit pins 12.
  • the IOP 15 is disposed between the synchronous FIFO processor 14 and the at least one transmit pin 12, such that the IOP 15 can fetch the m-bit transfer data from the synchronous FIFO processor 14, and when the inter-chip interconnected receiving device can receive the transmitted data, m send Pin 12 is sent to the receiving device of the inter-chip interconnect.
  • the synchronous FIFO processor 14 transmits the m-bit transmission data to the m transmission pins 12, since the synchronous FIFO processor 14 needs to perform related logic processing therein, it is transmitted to the m transmission pins 12, which causes synchronization.
  • the FIFO processor 14 sends the transmission data to the m transmit pins 12 for a large delay time, and the running clock frequency is small, that is, the running clock period is large to ensure that the m-bit transmission data is transmitted to the m in one cycle. Transmit pin 12, which results in a lower data transfer rate.
  • the IOP 15 is disposed between the synchronous FIFO processor 14 and the at least one transmit pin 12, and the synchronous FIFO processor 14 can send the m-bit transfer data to the IOP 15 delay time first, with respect to the synchronous FIFO processor 14 The delay time for transmitting data to the m transmit pins 12 is reduced.
  • the delay time for the IOP 15 to transmit the m-bit transmission data to the m transmission pins 12 is also reduced with respect to the delay time that the synchronous FIFO processor 14 transmits m to the transmission pins 12 for the transmission data.
  • the operating clock frequency at this time is increased relative to the synchronous clock processor 14 when m is transmitted data to the m transmitting pins 12, that is, the running clock period is reduced, so the synchronous IOP 15 is passed. Increased data transfer rate.
  • the synchronous FIFO processor 14 sends the converted m-bit transmission data to the IOP 15 according to the vld/rdy handshake protocol, that is, the synchronous FIFO processor 14 sends an indication transmission to the IOP 15 before transmitting the m-bit transmission data to the IOP 15.
  • the data sent by the terminal is the vld_s signal of the valid data.
  • the IOP 15 can learn, according to the vld_s signal, that the data sent by the synchronous FIFO processor 14 is valid data.
  • the IOP 15 can receive the valid data transmitted by the synchronous FIFO processor 14, the IOP 15 sends a rdy_s signal to the synchronous FIFO processor 14 indicating that the receiving end can receive the transmitted data.
  • the synchronous FIFO processor 14 receives the rdy_s signal sent by the IOP 15, it can be known from the rdy_s signal that the IOP 15 can receive the transmitted data.
  • the synchronous FIFO processor 14 can transmit the m-bit transmission data to the IOP 15 through the data channel.
  • the IOP 15 also needs to use the vld/rdy handshake protocol when transmitting the converted m-bit transmission data through the m transmission pins 12 to the receiving device of the inter-chip interconnect, that is, the IOP 15 transmits the m-bit to the receiving device connected to the inter-chip.
  • the vld_s signal indicating that the data sent by the transmitting end is valid data is sent to the receiving device connected to the inter-chip.
  • the receiving device connected between the slices can know that the data sent by the IOP 15 to the data is valid data according to the vld_s signal.
  • the receiving device connected between the chips can receive the valid data transmitted by the IOP 15, the receiving device of the inter-chip interconnection transmits to the IOP 15 a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the IOP 15 can learn that the receiving device of the inter-chip interconnect can receive the transmitted data according to the rdy_s signal.
  • the IOP 15 can transmit the m bit through the m transmitting pins 12. The transmission data is sent to the receiving device of the inter-chip interconnection.
  • the rdy_s can be sent to the inter-chip interconnecting device.
  • the signal, and the inter-chip interconnected transmitting device must be connected to the receiving device connected to the inter-chip when the rdy_s signal sent by the receiving device that receives the inter-chip interconnection is a signal indicating that the receiving end can receive the transmitted data, then inter-chip interconnection
  • the data transmitted by the receiving device at the transmitting end of the transmitting device waiting for the inter-chip interconnection is the vld_s signal of the valid data, and the transmitting device of the inter-chip interconnecting device can receive the transmitted data rdy_s at the receiving end of the receiving device waiting for the inter-chip interconnection.
  • the signal, which causes the transmitted data to never be sent, causes a deadlock.
  • the IOP 15 In order to avoid deadlock between the transmitting device and the receiving device of the inter-chip interconnection, when the Ird15 receives the rdy_s signal sent by the receiving device connected to the inter-chip interconnect to indicate that it cannot receive the transmitted data, the IOP 15 still sends the data indicating the transmitting end. The data is transmitted for the vld_s signal and m bits of the valid data. At this time, the m-bit transmission data sent by the IOP 15 does not change until the Ird15 receives the rdy_s signal sent by the receiving device of the inter-chip interconnect as indicating that it can receive the transmitted data.
  • inter-chip interconnection refers to the interconnection between chips or the interconnection between FPGAs.
  • An embodiment of the present invention provides an apparatus for transmitting inter-chip interconnects, including: a parallel-serial data conversion circuit, at least one transmit pin; wherein an output of the parallel-serial data conversion circuit is coupled to at least one transmit pin.
  • the parallel data conversion circuit is configured to acquire n-bit parallel data according to the vld/rdy handshake protocol, convert n-bit parallel data into m-bit transmission data, and pass m-bit transmission data according to the vld/rdy handshake protocol.
  • Send The pin is sent to the receiving device of the inter-chip interconnect.
  • the transmitting device for inter-chip interconnection can convert the n-bit parallel data to be transmitted to the m-bit transmission data through the parallel-serial data conversion circuit, and further, the m-bit transmission data can be transmitted to the slice by only m transmission pins.
  • Interconnected receiving device Compared with the prior art, the transmitting device for inter-chip interconnection requires n transmitting pins to transmit n-bit parallel data to the receiving device of the inter-chip interconnection, and the present invention can complete data by only requiring m transmitting pins.
  • the transmission realizes the reduction of the used pins when implementing inter-chip interconnection, thereby reducing the complexity of the routing of the signal lines connected between at least two FPGAs, thereby reducing the complexity of inter-chip interconnection.
  • the transmitting device of the inter-chip interconnection can acquire n-bit parallel data according to the vld/rdy handshake protocol, and after transmitting the m-bit transmission data, send the m-bit transmission data through m sending pins according to the vld/rdy handshake protocol.
  • the receiving device is connected to the inter-chip interconnect, so that the on-chip total protocol can be compatible in the inter-chip interconnecting device, and the compatibility performance is improved.
  • An embodiment of the present invention provides a receiving device for inter-chip interconnection, as shown in FIG. 6, comprising: at least one receiving pin 21, and a serial-to-parallel data conversion circuit 22.
  • the input of the serial-to-parallel data conversion circuit 22 is coupled to at least one receive pin 21, and the output is coupled to a data processor.
  • the serial-to-parallel data conversion circuit 22 is configured to acquire m-bit transmission data sent by the inter-chip interconnection transmitting device through the m receiving pins 21 according to the vld/rdy handshake protocol, and convert the m-bit transmission data into n-bit parallel data. And send n bits of parallel data to the data processor according to the vld/rdy handshake protocol.
  • n is an integer greater than m.
  • the parallel-serial data converting circuit 22 of the receiving device connected between the chips can be connected through the inter-chip transmitting device.
  • the m receiving pins 21 receive the transmission data of m bits.
  • the parallel-serial data conversion circuit 22 temporarily stores it until n-bit data is received, thereby realizing the conversion of the m-bit transmission data to the n-bit parallel data. After converting to n-bit parallel data, it can be sent to the data processor, causing the data processor to process the n-bit parallel data accordingly.
  • the data processor in the embodiment of the present invention may be interconnected between slices.
  • a processor in the receiving device may be a processor independent of the inter-chip interconnecting receiving device, which is not limited by the present invention.
  • n-bit parallel data includes not only the data to be processed to be used but also control data, address data and the like related to the data to be processed.
  • n in the n-bit parallel data is predetermined. It is related to the on-chip bus used.
  • the components are usually connected by an on-chip bus, that is, the receiving pin 21 is connected to the parallel-serial data conversion circuit 22 through the on-chip bus.
  • the protocol of the on-chip bus for example, AXI (Advanced eXtensible Interface) protocol, APB (Advanced Peripheral Bus) protocol, etc.
  • AXI Advanced eXtensible Interface
  • APB Advanced Peripheral Bus
  • the serial-to-parallel data conversion circuit 22 is configured to acquire, by using the m receiving pins 21, the m-bit transmission data sent by the inter-chip interconnecting device according to the vld/rdy handshake protocol, that is, the inter-chip interconnecting transmitting device is Before transmitting the m-bit transmission data to the receiving device connected between the chips, the vld_s signal indicating that the data transmitted by the transmitting end is valid data is sent to the receiving device interconnected between the chips, and the serial-to-parallel data conversion circuit 22 can pass the receiving pin. 21 receives the vld_s signal, and can learn, according to the vld_s signal, that the data sent by the transmitting device connected between the slices is valid data.
  • the serial-to-parallel data conversion circuit 22 can receive the valid data transmitted by the inter-chip interconnecting transmitting device, the serial-to-parallel data converting circuit 22 instructs the transmitting device of the inter-chip interconnect to receive the rdy_s signal of the transmitted data.
  • the serial-to-parallel data conversion circuit 22 can receive the m-bit transmission data transmitted from the inter-chip interconnected transmission device through the m reception pins 21.
  • the serial-to-parallel data conversion circuit 22 transmits n-bit parallel data to the data processor according to the vld/rdy handshake protocol, that is, the serial-to-parallel data conversion circuit 22 converts the m-bit transmission data into n-bit parallel data, and then Before the data processor sends the n-bit parallel data, the data processor sends a vld_s signal indicating that the data sent by the sender is valid data. After receiving the vld_s signal, the data processor can obtain the string according to the vld_s signal. The data to which the data conversion circuit 22 transmits is valid data.
  • the data processor transmits to the serial-to-parallel data conversion circuit 22 a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the serial-to-parallel data conversion circuit 22 receives the rdy_s signal sent by the data processor, it can be learned according to the rdy_s signal that the data processor can receive the transmitted data.
  • the serial-to-parallel data conversion circuit 22 can pass n bits through the data channel. Parallel data is sent to the data processor.
  • the vld_s signal indicating that the data sent by the transmitting end is valid data may be the same signal as the rdy_s signal indicating that the receiving end can receive the transmitted data, and may be different signals, for example, the vld_s signal passes the low level.
  • the signal indicates that the data sent by the transmitting end is valid data
  • the rdy_s signal indicates that the receiving end can receive the transmitted data through a high level signal.
  • the invention is not limited thereto.
  • the serial-to-parallel data conversion circuit 22 sends a vld_s signal indicating that the data sent by the transmitting end is invalid data to the data processor, the data processor can know that the serial-to-parallel data conversion circuit 22 is to be obtained according to the received vld_s signal. The transmitted data is invalid data, so the data processor does not process the data transmitted by the serial-to-parallel data conversion circuit 22.
  • the serial-to-parallel data conversion circuit 22 can know that the data processor cannot receive the transmitted data according to the received rdy_s signal. Therefore, the serial to parallel data conversion circuit 22 no longer transmits parallel data to the data processor.
  • the receiving device for inter-chip interconnection described above, as shown in FIG. 7, further includes an asynchronous FIFO processor 23.
  • the output of the serial to parallel data conversion circuit 22 is coupled to the data processor including the output of the serial to parallel data conversion circuit 22 coupled to the input of the asynchronous FIFO processor 23.
  • the output of the asynchronous FIFO processor 23 is coupled to the data processor.
  • the serial-to-parallel data conversion circuit 22 is specifically configured to transmit n-bit parallel data to the asynchronous FIFO processor 23 according to the vld/rdy handshake protocol.
  • the asynchronous FIFO processor 23 is further configured to receive and store n bits of parallel data, and send n bits of parallel data to the data processor according to the vld/rdy handshake protocol.
  • the asynchronous FIFO processor 23 is disposed in the serial-to-parallel data conversion circuit 22 and Between the data processors, the serial-to-parallel data conversion circuit 22 transmits its converted n-bit parallel data to the asynchronous FIFO processor 23, which is stored by the asynchronous FIFO processor 23, and the data processor can be obtained from the asynchronous FIFO processor 23. N-bit parallel data, so that when the data processor cannot receive n-bit parallel data, the serial-to-parallel data conversion circuit 22 can first cache the converted n-bit parallel data to the asynchronous FIFO processor 23, thereby ensuring the slice.
  • the inter-connected transmitting device transmits data normally.
  • serial to parallel data conversion circuit 22 is spaced apart from the data processor by the asynchronous FIFO processor 23, and the serial clock data conversion circuit 22 and the data processor may operate at different clock frequencies. That is, the data transmission rate of the serial-to-parallel data conversion circuit 22 and the data processor can be different, which can increase the data transmission rate of the serial-to-parallel data conversion circuit 22, thereby improving the efficiency of data transmission.
  • the serial-to-parallel data conversion circuit 22 sends its converted n-bit parallel data to the asynchronous FIFO processor 23 in accordance with the vld/rdy handshake protocol, that is, the serial-to-parallel data conversion circuit 22 transmits n bits to the asynchronous FIFO processor 23.
  • the asynchronous FIFO processor 23 Before the parallel data, the asynchronous FIFO processor 23 first sends a vld_s signal indicating that the data sent by the transmitting end is valid data. After receiving the vld_s signal, the asynchronous FIFO processor 23 can learn the serial data conversion according to the vld_s signal. The data that circuit 22 sends to it is valid data.
  • the asynchronous FIFO processor 23 transmits to the serial-to-parallel data conversion circuit 22 a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the serial-to-parallel data conversion circuit 22 receives the rdy_s signal sent by the asynchronous FIFO processor 23, it can be learned from the rdy_s signal that the asynchronous FIFO processor 23 can receive the transmitted data.
  • the serial-to-parallel data conversion circuit 22 can pass the data.
  • the channel sends n bits of parallel data to the asynchronous FIFO processor 23.
  • the asynchronous FIFO processor 23 When the asynchronous FIFO processor 23 sends the n-bit parallel data to the data processor, it can also forward the data according to the vld/rdy handshake protocol, that is, before the asynchronous FIFO processor 23 sends the n-bit parallel data to the data processor.
  • the processor sends a vld_s signal indicating that the data sent by the transmitting end is valid data. After receiving the vld_s signal, the data processor can learn, according to the vld_s signal, that the data sent by the asynchronous FIFO processor 23 is valid data.
  • the data processor can receive the valid data sent by the asynchronous FIFO processor 23, the data processor goes to the asynchronous FIFO processor 23 Sending a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the asynchronous FIFO processor 23 receives the rdy_s signal sent by the data processor, it can be learned according to the rdy_s signal that the data processor can receive the transmitted data.
  • the asynchronous FIFO processor 23 can parallel the n bits through the data channel. The data is sent to the data processor, causing the data processor to acquire n bits of parallel data to be converted from the asynchronous FIFO processor 13.
  • the receiving device for inter-chip interconnection described above, as shown in FIG. 8, further includes a synchronous FIFO processor 24.
  • the input of the serial-to-parallel data conversion circuit 22 to the at least one receiving pin 21 includes:
  • the input of the serial to parallel data conversion circuit 22 is coupled to the output of the synchronous FIFO processor 24, and the input of the synchronous FIFO processor 24 is coupled to at least one receive pin 21.
  • the synchronous FIFO processor 24 is configured to receive m-bit transmission data transmitted by the inter-chip interconnected transmitting device through the m receiving pins 21 according to the vld/rdy handshake protocol, and store the m-bit transmission data.
  • the serial-to-parallel data conversion circuit 21 is specifically configured to acquire m-bit transmission data transmitted from the synchronization device of the inter-chip interconnect from the synchronous FIFO processor 24 according to the vld/rdy handshake protocol.
  • the synchronous FIFO processor 24 is disposed between the serial-to-parallel data conversion circuit 22 between the receiving pins 21, and the inter-chip interconnecting transmitting device transmits the m-bit transmission data to the inter-chip interconnected receiving device, and inter-chip interconnection
  • the m receiving pins 21 of the receiving device transmit the received data to the synchronous FIFO processor 24, and the synchronous FIFO processor 24 stores the received m-bit transmitted data.
  • the serial to parallel data conversion circuit 22 can acquire m bits of transmission data in the synchronous FIFO processor 24 and convert it.
  • the synchronous FIFO processor 24 can first buffer the transmission data transmitted by the inter-chip interconnection transmitting apparatus, thereby ensuring the normal transmission of the inter-chip interconnection transmitting apparatus.
  • the inter-chip interconnecting transmitting device first transmits the data sent by the transmitting end to the receiving device interconnected between the slices before transmitting the m-bit transmission data to the receiving device interconnected between the slices.
  • the synchronous FIFO processor 24 can receive the vld_s signal through the receiving pin 21, and can learn from the vld_s signal that the data sent by the inter-chip interconnecting device is valid data.
  • the synchronous FIFO processor 24 instructs the transmitting device connected between the slices to receive the rdy_s signal of the transmitted data.
  • the synchronous FIFO processor 24 can receive the m-bit transmission data transmitted by the transmitting device of the inter-chip interconnection through the m receiving pins 21.
  • the serial-to-parallel data conversion circuit 22 acquires the m-bit transmission data transmitted from the inter-chip interconnected transmitting device from the synchronous FIFO processor 24 according to the vld/rdy handshake protocol, that is, the synchronous FIFO processor 24 acquires the m-bit transmission data. Then, the serial data conversion circuit 22 can send a vld_s signal indicating that the data sent by the transmitting end is valid data. After receiving the vld_s signal, the serial data conversion circuit 22 can learn the synchronous FIFO processor 24 according to the vld_s signal. The data sent to it is valid data.
  • the serial-to-parallel data conversion circuit 22 can receive the valid data transmitted by the synchronous FIFO processor 24, the serial-to-parallel data conversion circuit 22 transmits to the synchronous FIFO processor 24 a rdy_s signal indicating that the receiving end can receive the transmitted data.
  • the synchronous FIFO processor 24 can learn that the serial-to-parallel data conversion circuit 22 can receive the transmitted data according to the rdy_s signal.
  • the synchronous FIFO processor 24 can transmit the m-bit transmission data to the data channel to the data channel.
  • the serial to parallel data conversion circuit 22 is described in this time, the serial to parallel data conversion circuit 22.
  • the embodiment of the invention provides a receiving device for inter-chip interconnection, comprising: at least one receiving pin, a serial-to-parallel data conversion circuit.
  • the input end of the serial-to-parallel data conversion circuit is connected to at least one receiving pin, and the output end of the serial-to-parallel data conversion circuit is connected to the data processor.
  • a serial-to-parallel data conversion circuit for acquiring m-bit transmission data transmitted by a transmitting device of an inter-chip interconnect through m receiving pins according to a vld/rdy handshake protocol, converting m-bit transmission data into n-bit parallel data, and The n-bit parallel data is sent to the data processor according to the vld/rdy handshake protocol.
  • the inter-chip interconnected transmission device converts n-bit parallel data into m-bit transmission data and transmits it to the inter-chip interconnected receiving device through m transmitting pins
  • the receiving device can receive the m receiving signals through the m receiving pins.
  • the foot receives m bits of transmission data. And convert it to n-bit parallel data.
  • the transmitting device for inter-chip interconnection requires n transmitting pins to transmit n-bit parallel data to the receiving device of the inter-chip interconnection, and the present invention can only require m transmitting pins and Data can be transmitted by m receiving pins, which reduces the use of pins during inter-chip interconnection, thereby reducing the complexity of the routing of signal lines connected between at least two FPGAs, thereby reducing the chip.
  • the complexity of the interconnection is n transmitting pins to transmit n-bit parallel data to the receiving device of the inter-chip interconnection, and the present invention can only require m transmitting pins and Data can be transmitted by m receiving pins, which reduces the use of pins during inter-chip interconnection, thereby reducing the complexity of the routing of signal lines connected between at least two FPGAs, thereby reducing the chip. The complexity of the interconnection.
  • An embodiment of the present invention provides a method for transmitting an inter-chip interconnection, as shown in FIG. 9, including:
  • the transmitting device of the inter-chip interconnect acquires n-bit parallel data according to the vld/rdy handshake protocol.
  • n is an integer greater than one.
  • the transmitting device of the inter-chip interconnection can acquire n-bit parallel data of the receiving device that needs to be transmitted to the inter-chip interconnect from the data transmitting processor.
  • the inter-chip interconnected transmitting device acquires the n-bit parallel data that needs to be transmitted to the receiving device of the inter-chip interconnect, it can be buffered first.
  • n is an integer greater than 0 and less than n.
  • the transmitting device of the inter-chip interconnect can convert the transmitted data into m-bit transmission data according to the number of actually available transmitting pins.
  • the inter-chip interconnected transmission device converts the buffered n-bit parallel data into m-bit transmission data according to the number of actually available transmission pins. After converting to m-bit transmission data, the m-bit transmission data can be buffered first.
  • the m-bit transmission data is sent to the receiving device of the inter-chip interconnect through the m transmit pins according to the vld/rdy handshake protocol.
  • the m-bit transmission data is transmitted to the inter-chip interconnection through the m transmission pins according to the vld/rdy handshake protocol. Device.
  • the inter-chip interconnected transmitting device transmits the m-bit transmission data of the buffer to the m-segment receiving device via the m transmit pins according to the vld/rdy handshake protocol.
  • the embodiment of the invention provides a method for transmitting inter-chip interconnection, which is applied to a transmitting device for inter-chip interconnection.
  • the inter-chip interconnected transmitting device acquires n-bit parallel data according to the vld/rdy handshake protocol, and converts n-bit parallel data into m-bit transmitted data. And according to the vld/rdy handshake protocol, the m-bit transmission data is sent to the receiving device of the inter-chip interconnect through the m transmission pins.
  • the transmitting device for inter-chip interconnection can convert the n-bit parallel data to be transmitted to the m-bit transmission data through the parallel-serial data conversion circuit, and further, the m-bit transmission data can be transmitted to the slice by only m transmission pins.
  • Interconnected receiving device Compared with the prior art, the transmitting device for inter-chip interconnection requires n transmitting pins to transmit n-bit parallel data to the receiving device of the inter-chip interconnection, and the present invention can complete data by only requiring m transmitting pins.
  • the transmission realizes the reduction of the used pins when implementing inter-chip interconnection, thereby reducing the complexity of the routing of the signal lines connected between at least two FPGAs, thereby reducing the complexity of inter-chip interconnection.
  • An embodiment of the present invention provides a method for receiving inter-chip interconnection, as shown in FIG. 10, including:
  • the receiving device of the inter-chip interconnect acquires the m-bit transmission data sent by the transmitting device of the inter-chip interconnection through the m receiving pins according to the vld/rdy handshake protocol.
  • n is an integer greater than zero.
  • the inter-chip interconnected receiving device can use the m transmitting devices connected to the inter-chip according to the vld/rdy handshake protocol.
  • the m receiving pins corresponding to the pins acquire the m-bit transmission data transmitted by the transmitting device connected between the slices.
  • the receiving device of the inter-chip interconnection may first cache the data.
  • n is an integer greater than m.
  • the inter-chip interconnected transmitting device receives the m-bit transmission data according to the vld/rdy handshake protocol
  • the m-bit transmission data is converted into n-bit parallel data.
  • the n-bit parallel data is sent to the data processor according to the vld/rdy handshake protocol. In this way, The data processor can process the n-bit parallel data accordingly.
  • the transmitting device of the inter-chip interconnect may convert the buffered m-bit transmission data into n-bit parallel data according to the vld/rdy handshake protocol.
  • the converted n-bit parallel data is buffered, and the buffered n-bit parallel data is sent to the data processor.
  • the embodiment of the invention provides a method for receiving inter-chip interconnection, and the receiving device for inter-chip interconnection acquires m-bit transmission data transmitted by the transmitting device of the inter-chip interconnection through m receiving pins according to the vld/rdy handshake protocol.
  • the m-bit transfer data is converted into n-bit parallel data, and n-bit parallel data is transmitted to the data processor according to the vld/rdy handshake protocol.
  • the inter-chip interconnected transmission device converts n-bit parallel data into m-bit transmission data and transmits it to the inter-chip interconnected receiving device through m transmitting pins
  • the receiving device can receive the m receiving signals through the m receiving pins.
  • the foot receives m bits of transmission data.
  • the transmitting device for inter-chip interconnection requires n transmitting pins to transmit n-bit parallel data to the receiving device of the inter-chip interconnection, and the present invention can only require m transmitting pins and m receiving leads.
  • the data can be sent at the foot, which reduces the use of pins during inter-chip interconnection, thereby reducing the complexity of the routing of the signal lines connected between at least two FPGAs, thereby reducing the complexity of inter-chip interconnection. Sex.
  • the embodiment of the invention provides a system for inter-chip interconnection, as shown in FIG. 11, comprising: a transmitting device 31 for inter-chip interconnection, and a receiving device 32 for inter-chip interconnection.
  • the inter-chip interconnecting transmitting device 31 is the inter-chip interconnecting transmitting device described in the above embodiment.
  • the receiving device 32 for inter-chip interconnection is the receiving device for inter-chip interconnection described in the above embodiment.
  • the embodiment of the invention provides a transmitting and receiving device for inter-chip interconnection, a transmitting and receiving method and a system, and a transmitting device for inter-chip interconnection includes: a parallel data conversion circuit, at least one transmitting pin; wherein, parallel data conversion The input of the circuit is coupled to the data transmitting processor, and the output of the serial data conversion circuit is coupled to at least one of the transmit pins.
  • a parallel data conversion circuit for acquiring n-bit parallel data from a data transmission processor according to a vld/rdy handshake protocol, and converting n-bit parallel data into m-bit transmission Data, and the m-bit transmission data is sent to the receiving device of the inter-chip interconnect through m transmit pins according to the vld/rdy handshake protocol.
  • the transmitting device for inter-chip interconnection can convert the n-bit parallel data to be transmitted to the m-bit transmission data through the parallel-serial data conversion circuit, and further, the m-bit transmission data can be transmitted to the slice by only m transmission pins. Interconnected receiving device.
  • the transmitting device for inter-chip interconnection requires n transmitting pins to transmit n-bit parallel data to the receiving device of the inter-chip interconnection, and the present invention can complete data by only requiring m transmitting pins.
  • the transmission realizes the reduction of the used pins when implementing inter-chip interconnection, thereby reducing the complexity of the routing of the signal lines connected between at least two FPGAs, thereby reducing the complexity of inter-chip interconnection.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the above-described integrated unit implemented in the form of a software functional unit can be stored in a computer readable storage medium.
  • the software functional units described above are stored in a storage medium and include instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform portions of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, and a read only memory. (Read-Only Memory, ROM for short), random access memory (RAM), disk or optical disk, and other media that can store program code.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif et un procédé pour envoyer une interconnexion inter-puces, un dispositif et un procédé pour recevoir une interconnexion inter-puces, et un système, qui se rapportent au domaine technique des circuits intégrés. Le dispositif d'envoi comprend : un circuit de conversion de données parallèle-série (11) et au moins une broche d'envoi (12). Une borne d'entrée du circuit de conversion de données parallèle-série est connectée à un processeur de transmission de données, et une borne de sortie du circuit de conversion de données parallèle-série est connectée à la ou aux broches d'envoi. Le circuit de conversion de données parallèle-série est configuré pour acquérir, selon un protocole d'établissement de liaison vld/rdy, des données parallèles à n bits à partir du processeur de transmission de données (101), convertir les données parallèles à n bits en données de transmission à m bits (102), et envoyer, selon le protocole d'établissement de liaison vld/rdy, les données de transmission à m bits à un dispositif de réception d'interconnexion inter-puces au moyen des m broches d'envoi (103), où n est un nombre entier supérieur à 1, et m est un nombre entier supérieur à 0 et inférieur à n. La présente invention peut s'appliquer à une scène de transmission de données.
PCT/CN2015/087690 2015-06-04 2015-08-20 Dispositif et procédé pour envoyer une interconnexion inter-puces, dispositif et procédé pour recevoir une interconnexion inter-puces, et système WO2016192211A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510305010.0A CN104991883A (zh) 2015-06-04 2015-06-04 片间互联的发送、接收装置及发送、接收方法及系统
CN201510305010.0 2015-06-04

Publications (1)

Publication Number Publication Date
WO2016192211A1 true WO2016192211A1 (fr) 2016-12-08

Family

ID=54303699

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/087690 WO2016192211A1 (fr) 2015-06-04 2015-08-20 Dispositif et procédé pour envoyer une interconnexion inter-puces, dispositif et procédé pour recevoir une interconnexion inter-puces, et système

Country Status (2)

Country Link
CN (1) CN104991883A (fr)
WO (1) WO2016192211A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112699077A (zh) * 2020-12-30 2021-04-23 上海安路信息科技股份有限公司 Fpga芯片及fpga子芯片的互联方法
CN116450569A (zh) * 2023-06-14 2023-07-18 苏州浪潮智能科技有限公司 一种片间互联系统、一种数据传输方法
CN116822445A (zh) * 2023-08-25 2023-09-29 成都金支点科技有限公司 一种用于高速并行计算的片间总线协议实现方法
CN117376116A (zh) * 2023-10-08 2024-01-09 苏州异格技术有限公司 虚拟交换机的配置方法、装置、计算机设备及存储介质

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107426076B (zh) * 2017-07-18 2020-06-30 成都天锐星通科技有限公司 一种电子设备、信息处理方法及信息传输方法
CN119283810B (zh) * 2024-12-16 2025-05-09 苏州国芯科技股份有限公司 安全气囊控制电路、集成电路芯片及安全气囊系统

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7058120B1 (en) * 2002-01-18 2006-06-06 Xilinx, Inc. Integrated high-speed serial-to-parallel and parallel-to-serial transceiver
US7086025B1 (en) * 2003-10-23 2006-08-01 Adaptec, Inc. Programmable logic device partitioning method for application specific integrated circuit prototyping
CN101719177A (zh) * 2009-11-02 2010-06-02 北京中星微电子有限公司 系统建模和仿真的方法及装置
CN101833502A (zh) * 2010-04-15 2010-09-15 上海华为技术有限公司 Asic芯片验证方法和可编程门阵列
CN102567587A (zh) * 2012-01-04 2012-07-11 青岛海信信芯科技有限公司 Fpga互联装置及方法
CN104025069A (zh) * 2011-12-15 2014-09-03 马维尔国际贸易有限公司 用于fpga原型化的串行接口
CN104239239A (zh) * 2013-06-17 2014-12-24 瑞祺电通股份有限公司 在线同步备份系统方法及其装置
CN104298634A (zh) * 2014-09-24 2015-01-21 四川九洲电器集团有限责任公司 基于fpga和dsp的数据传输系统

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7058120B1 (en) * 2002-01-18 2006-06-06 Xilinx, Inc. Integrated high-speed serial-to-parallel and parallel-to-serial transceiver
US7086025B1 (en) * 2003-10-23 2006-08-01 Adaptec, Inc. Programmable logic device partitioning method for application specific integrated circuit prototyping
CN101719177A (zh) * 2009-11-02 2010-06-02 北京中星微电子有限公司 系统建模和仿真的方法及装置
CN101833502A (zh) * 2010-04-15 2010-09-15 上海华为技术有限公司 Asic芯片验证方法和可编程门阵列
CN104025069A (zh) * 2011-12-15 2014-09-03 马维尔国际贸易有限公司 用于fpga原型化的串行接口
CN102567587A (zh) * 2012-01-04 2012-07-11 青岛海信信芯科技有限公司 Fpga互联装置及方法
CN104239239A (zh) * 2013-06-17 2014-12-24 瑞祺电通股份有限公司 在线同步备份系统方法及其装置
CN104298634A (zh) * 2014-09-24 2015-01-21 四川九洲电器集团有限责任公司 基于fpga和dsp的数据传输系统

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112699077A (zh) * 2020-12-30 2021-04-23 上海安路信息科技股份有限公司 Fpga芯片及fpga子芯片的互联方法
CN112699077B (zh) * 2020-12-30 2024-03-29 上海安路信息科技股份有限公司 Fpga芯片及fpga子芯片的互联方法
CN116450569A (zh) * 2023-06-14 2023-07-18 苏州浪潮智能科技有限公司 一种片间互联系统、一种数据传输方法
CN116450569B (zh) * 2023-06-14 2023-08-15 苏州浪潮智能科技有限公司 一种片间互联系统、一种数据传输方法
CN116822445A (zh) * 2023-08-25 2023-09-29 成都金支点科技有限公司 一种用于高速并行计算的片间总线协议实现方法
CN116822445B (zh) * 2023-08-25 2023-11-03 成都金支点科技有限公司 一种用于高速并行计算的片间总线协议实现方法
CN117376116A (zh) * 2023-10-08 2024-01-09 苏州异格技术有限公司 虚拟交换机的配置方法、装置、计算机设备及存储介质
CN117376116B (zh) * 2023-10-08 2024-05-17 苏州异格技术有限公司 虚拟交换机的配置方法、装置、计算机设备及存储介质

Also Published As

Publication number Publication date
CN104991883A (zh) 2015-10-21

Similar Documents

Publication Publication Date Title
WO2016192211A1 (fr) Dispositif et procédé pour envoyer une interconnexion inter-puces, dispositif et procédé pour recevoir une interconnexion inter-puces, et système
US10802995B2 (en) Unified address space for multiple hardware accelerators using dedicated low latency links
US10468078B2 (en) Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communication
US11669472B2 (en) Frequency translation circuitry for an interconnection in an active interposer of a semiconductor package
US11537543B2 (en) Technique for handling protocol conversion
US9530464B2 (en) Semiconductor apparatus and data bit inversion
CN112231161B (zh) 多芯片调试方法及多芯片调试装置
WO2017171997A1 (fr) Procédé, appareil et système pour communiquer entre de multiples protocoles
CN102567587A (zh) Fpga互联装置及方法
CN117421268A (zh) 一种互联系统、设备及网络
KR100807443B1 (ko) 기회적 판독 완료 결합
CN101026528A (zh) 一种同步串行接口装置
US6208645B1 (en) Time multiplexing of cyclic redundancy functions in point-to-point ringlet-based computer systems
EP3550439B1 (fr) Système de traitement d'informations, circuit intégré à semi-conducteur et procédé de traitement d'informations
CN114301485B (zh) 接口组件和数据传输方法
CN111274193A (zh) 数据处理装置及方法
WO2022266959A1 (fr) Circuit et procédé de test de puce
US20090113092A1 (en) Signal converter for debugging that expands fifo capacity
CN114443530B (zh) 基于TileLink的芯片互联电路及数据传输方法
US11636061B2 (en) On-demand packetization for a chip-to-chip interface
CN115905069A (zh) 一种基于bmc芯片的usb数据传输方法及装置
CN101576867B (zh) 一种扩展通用异步串行接口方法、装置和系统
CN202662010U (zh) Fpga互联装置、验证板及soc系统
US12093202B2 (en) DBI encoding device and DBI encoding method
CN221899549U (zh) 多芯片互联装置、主板及电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15893867

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15893867

Country of ref document: EP

Kind code of ref document: A1