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WO2016116005A1 - Procédé et appareil de traitement de phase - Google Patents

Procédé et appareil de traitement de phase Download PDF

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Publication number
WO2016116005A1
WO2016116005A1 PCT/CN2016/070903 CN2016070903W WO2016116005A1 WO 2016116005 A1 WO2016116005 A1 WO 2016116005A1 CN 2016070903 W CN2016070903 W CN 2016070903W WO 2016116005 A1 WO2016116005 A1 WO 2016116005A1
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WO
WIPO (PCT)
Prior art keywords
phase
data signal
disturbance
offset
optical power
Prior art date
Application number
PCT/CN2016/070903
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English (en)
Chinese (zh)
Inventor
张理维
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2016116005A1 publication Critical patent/WO2016116005A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H04B10/516—Details of coding or modulation
    • H04B10/548—Phase or frequency modulation
    • H04B10/556—Digital modulation, e.g. differential phase shift keying [DPSK] or frequency shift keying [FSK]

Definitions

  • the present invention relates to the field of communications, and in particular to a phase processing method and apparatus.
  • the RZ clock In a system of optical transmission clock modulation (for example, RZ clock modulation), in order to maintain the best transmission performance of the system, the RZ clock is aligned with the center of the data signal to be transmitted.
  • RZ clock modulation for example, RZ clock modulation
  • the alignment state of the RZ clock signal and the data signal will deviate from the alignment state, resulting in deterioration of transmission performance, for example, edge jitter causes RZ data signal eye diagram Compression, the transmission side optical power detection error increases.
  • the present invention provides a phase processing method and apparatus to at least solve the problem of deterioration in transmission performance due to misalignment of a clock signal and a data signal existing in the related art.
  • a phase processing method comprising: adding a phase disturbance of a predetermined amplitude to a data signal; and controlling the data signal and the clock signal to perform phase alignment processing according to the phase disturbance.
  • the phase disturbance comprises positive perturbation and/or negative perturbation.
  • performing phase alignment processing on the data signal and the clock signal according to the phase disturbance comprises: adding a predetermined number of phase offsets on the data signal during a period of the phase disturbance; collecting corresponding to the a voltage of the phase-shifted optical power; determining a target phase offset added to the data signal according to the collected voltage of the optical power; controlling the data signal and the clock signal to perform phase by using the target phase offset Align processing.
  • determining, according to the collected voltage of the optical power, the target phase offset added to the data signal comprises: selecting a phase offset when the collected optical power is zero or a phase difference from zero is less than a predetermined threshold; Determining the selected phase offset is the target phase offset.
  • the data signal is a four-phase relative in a zero-to-four phase relative phase shift keying RZ-DQPSK system Phase shift keying DQPSK data.
  • a phase processing apparatus comprising: an adding module configured to add a phase disturbance of a predetermined amplitude to a data signal; a control module configured to control the data signal according to the phase disturbance and The clock signal is phase aligned.
  • the phase disturbance comprises positive perturbation and/or negative perturbation.
  • control module includes: an adding unit, configured to add a predetermined number of phase offsets on the data signal during a period of the phase disturbance; and an acquiring unit configured to collect corresponding to the phase offset a voltage of the shifted optical power; a determining unit configured to determine a target phase offset added to the data signal according to the collected voltage of the optical power; and a control unit configured to control the phase shift using the target
  • the data signal and the clock signal are phase aligned.
  • the determining unit includes: a selecting subunit, configured to select a phase offset when the collected optical power is zero or a phase difference from zero is less than a predetermined threshold; determining a subunit, configured to determine the selected phase The offset is the phase offset of the destination.
  • the data signal is four phase relative phase shift keyed DQPSK data in a zero-to-four phase relative phase shift keyed RZ-DQPSK system.
  • a phase disturbance of a predetermined amplitude is added to the data signal; and the phase alignment processing is performed according to the phase disturbance to control the data signal and the clock signal, thereby solving the problem that the clock signal and the data signal are not aligned due to the related art.
  • the performance of the transmission performance is degraded, thereby achieving the effect of achieving alignment of the clock signal and the data signal.
  • FIG. 1 is a flow chart of a phase processing method according to an embodiment of the present invention.
  • FIG. 2 is a block diagram showing the structure of a phase processing apparatus according to an embodiment of the present invention.
  • FIG. 3 is a block diagram showing the structure of a control module 24 in a phase processing device according to an embodiment of the present invention
  • FIG. 4 is a block diagram showing the structure of the determining unit 36 in the phase processing apparatus according to an embodiment of the present invention.
  • FIG. 5 is a transmission block diagram of an RZ-DQPSK system according to an embodiment of the present invention.
  • FIG. 6 is a detailed block diagram of transmission of an RZ-DQPSK system in accordance with an embodiment of the present invention.
  • Figure 7 is an eye diagram of a monitoring point in accordance with an embodiment of the present invention.
  • FIG. 8a is a monitoring eye diagram 1 of a phase mismatch in an RZ-DQPSK system according to an embodiment of the present invention
  • 8b is a second embodiment of a monitoring point in phase mismatch in an RZ-DQPSK system according to an embodiment of the present invention.
  • FIG. 8c is a third embodiment of a monitoring point in the phase mismatch in the RZ-DQPSK system according to an embodiment of the present invention.
  • FIG. 9 is a diagram showing relationship between phase shift and light output power according to an embodiment of the present invention.
  • FIG. 10 is a block diagram showing the principle of a clock data phase shift controller according to an embodiment of the present invention.
  • FIG. 11 is a timing diagram of a perturbation cycle in accordance with an embodiment of the present invention.
  • FIG. 12 is a timing diagram of a clock data phase shift controller in accordance with an embodiment of the present invention.
  • FIG. 13 is a block diagram showing a control structure of a MUX phase display lookup table LUT according to an embodiment of the present invention.
  • FIG. 1 is a flowchart of a phase processing method according to an embodiment of the present invention. As shown in FIG. 1, the process includes the following steps:
  • Step S102 adding a phase disturbance of a predetermined amplitude to the data signal
  • Step S104 performing phase alignment processing according to the phase disturbance control data signal and the clock signal.
  • the phase alignment processing is performed on the data signal and the clock signal by adding a phase disturbance in the data signal, thereby solving the problem that the transmission performance is degraded due to misalignment of the clock signal and the data signal existing in the related art, thereby achieving The effect of aligning the clock signal and the data signal is achieved.
  • phase disturbances described above may be of various types.
  • positive perturbations may be added or negative perturbations may be added when phase disturbance is added.
  • phase alignment processing according to the phase disturbance control data signal and the clock signal, a plurality of manners may be adopted.
  • the phase may be processed in the following manner: in the phase of the phase disturbance, in the data signal Adding a predetermined number of phase offsets; collecting a voltage corresponding to the optical power of the phase offset; determining a target phase offset added to the data signal according to the voltage of the collected optical power; using the target phase offset control data
  • the signal and clock signals are phase aligned.
  • determining the target phase offset added to the data signal according to the collected voltage of the optical power may adopt a scheme of: selecting a phase offset when the collected optical power is zero or a phase difference from zero is less than a predetermined threshold; determining the selected phase The offset is the target phase offset. That is, when the optical power is zero or close to zero, the phase of the data signal and the clock signal are aligned, and therefore, the characteristic can be utilized to determine the phase offset that causes the phase of the data signal and the clock signal to be aligned.
  • the above technical solution can be applied to a plurality of systems.
  • the above technical solution can be applied to a zero-quadrature phase-shift keyed RZ-DQPSK system, and the data signal is Four-phase relative phase shift keying DQPSK data in the RZ-DQPSK system.
  • a phase processing device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 2 is a block diagram showing the structure of a phase processing apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus includes an adding module 22 and a control module 24. The apparatus will be described below.
  • the adding module 22 is arranged to add a phase disturbance of a predetermined amplitude to the data signal; the control module 24 is connected to the adding module 22, and is arranged to perform phase alignment processing on the data signal and the clock signal according to the phase disturbance.
  • phase disturbance described above may include positive perturbation and/or negative perturbation.
  • control module 24 includes an adding unit 32, an acquiring unit 34, a determining unit 36, and a control unit 38.
  • the device control module 24 will be described below.
  • the adding unit 32 is arranged to add a predetermined number of phase offsets on the data signal during the period of the phase disturbance;
  • the collecting unit 34 is connected to the adding unit 32, and is configured to collect the voltage corresponding to the optical power of the phase shift a determining unit 36, coupled to the collecting unit 34, configured to determine a target phase offset added to the data signal according to the voltage of the collected optical power;
  • the control unit 38 is coupled to the determining unit 36, and configured to utilize the target phase
  • the offset control data signal and the clock signal are phase aligned.
  • the determining unit 36 includes a selecting subunit 42 and a determining subunit 44.
  • the determining unit 36 will be described below. .
  • the selecting subunit 42 is arranged to select a phase offset when the collected optical power is zero or a phase difference from zero is less than a predetermined threshold; the determining subunit 44 is connected to the selecting subunit 42 and is set to determine the selected phase offset. Phase offset.
  • the data signal may be four-phase relative phase shift keying DQPSK data in a zero-to-four phase relative phase shift keying RZ-DQPSK system.
  • a method and an implementation device for automatically controlling the alignment of the RZ clock and the transmission data are also proposed in the embodiment of the present invention.
  • the DQPSK system is taken as an example to explain the present invention.
  • the phase relationship between the RZ clock and the transmitted data can be automatically aligned according to the change caused by the perturbation.
  • the RZ clock phase is fixed, and only the phase shift of the data signal is added, which has little effect on the jitter of the RZ optical signal.
  • FIG. 5 is a transmission block diagram of an RZ-DQPSK system according to an embodiment of the present invention
  • FIG. 6 is a detailed block diagram of transmission of an RZ-DQPSK system according to an embodiment of the present invention.
  • Output port phase end, cancellation end.
  • the phase end output is the RZ-DQPSK signal
  • the light output of the cancellation end is connected to the backlight monitoring diode MPD to generate a photocurrent proportional to the light output intensity.
  • FIG. 6 includes three related optical signal detection points A, B, and C, wherein the A point is used for the DQPSK modulator to output the DQPSK optical signal, and the B point is the DQPSK for the RZ modulation.
  • the phase end of the device, point C is the cancellation output of the RZ modulator.
  • Fig. 7, is an eye diagram of a monitoring point according to an embodiment of the present invention.
  • FIG. 8a is a monitoring eye diagram of a phase mismatch in an RZ-DQPSK system according to an embodiment of the present invention.
  • FIG. 8b is a monitoring eye diagram 2 and FIG. 8c of a phase mismatch in an RZ-DQPSK system according to an embodiment of the present invention.
  • It is a monitoring point eye diagram 3 in the case of phase mismatch in the RZ-DQPSK system according to the embodiment of the present invention, wherein the uppermost picture in FIG. 8a, FIG. 8b, and FIG. 8c is a schematic diagram of the data clock alignment state, and the middle figure is the constructive The end output photo eye diagram, the bottommost diagram is the destructive end output eye diagram.
  • FIG. 9 is a relationship diagram of phase shift and light output power according to an embodiment of the present invention.
  • FIG. 9 shows clock data mismatch and RZ phase. The relationship between the average optical power after normalization.
  • the device that controls the alignment of the data clock is the optical power minimum point lock controller.
  • FIG. 10 is a block diagram showing the clock data phase shifting controller according to an embodiment of the present invention.
  • the phase dither produces an optical power perturbation that causes a slight change in the Vtz of the MPD output.
  • the Auto-zero loop will eliminate the DC level of Vtz's stable DC signal, only amplifying the phase micro
  • the Auto-zero loop is disabled during the time slice of the perturbation signal, and the loop is enabled between positive and negative perturbations, ie, when the non-perturbative time slice is enabled.
  • the clock data alignment controller samples the Ts sampling period plus the voltage Va of the MPD output after the perturbation, and the clock phase correlation detector averages the Ns positive perturbations to produce an average positive perturbation PHp, and averages Ns negative perturbations. Average negative perturbation PHn.
  • the integrator updates the enable output according to the three different voltage state inputs described below.
  • the step size of the clock phase perturbation is set by Kdf.
  • the forward phase offset is added to the phase shifters of data I, Q, which produces a positive phase shift of IQ data relative to the RZ clock. Then set a suitable delay, so that the high gain amplifier in the figure is configured, Va is acquired, PHp is updated, the control loop is removed from the forward phase offset, and the Auto-zero loop restores Va to zero.
  • the negative phase shift is added to the phase shifters of data I, Q, which produces a negative phase shift of IQ data relative to the RZ clock. Then set a suitable delay so that the high gain amplifier in the figure is configured, Va is acquired, PHn is updated, the control loop is removed from the negative phase offset, and the Auto-zero loop restores Va to zero.
  • FIG. 11 is a timing diagram of a perturbation period according to an embodiment of the present invention
  • FIG. 12 is a timing diagram of a clock data phase shift controller according to an embodiment of the present invention.
  • the correlation detector SD is Ns positive.
  • the phase offset and the Ns negative phase offset sample values are averaged to produce an error signal for Vdiff, and then the error signal value is symbolized.
  • the clock data phase shift integrator obtains the symbolized error signal and enables the output, and simultaneously updates the phase value of IQ.
  • FIG. 13 is a block diagram of a control structure of a MUX phase display lookup table LUT according to an embodiment of the present invention. As shown in FIG. 13, a method of clock and data phase shifting is different in different MUXs, so the phase of the clock data offset controller is executed. The manner of movement is also different. In the practice of the present invention, a lookup table can be used to convert the output of the clock data phase shift controller to the phase change of IQ.
  • the present invention effectively solves the problem that the clock signal and the data signal are not correct.
  • the problem of deterioration of transmission performance leads to the alignment of the clock signal and the data signal.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the phase processing method and apparatus provided by the embodiments of the present invention have the following beneficial effects: solving the problem that the transmission performance is degraded due to misalignment of the clock signal and the data signal existing in the related art, thereby achieving the realization of the clock signal.
  • the effect of aligning with the data signal is described above.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Optical Communication System (AREA)

Abstract

La présente invention concerne un procédé et un appareil de traitement de phase, le procédé consistant : à ajouter, à un signal de données, une perturbation de phase ayant une amplitude prédéterminée ; et à amener le signal de données et un signal d'horloge à réaliser un traitement d'alignement de phase selon la perturbation de phase. La présente invention résout le problème dans l'état de la technique associé selon lequel une détérioration des performances d'émission est provoquée par un mauvais alignement du signal d'horloge et du signal de données, et obtient ainsi l'effet de l'alignement du signal d'horloge et du signal de données.
PCT/CN2016/070903 2015-01-20 2016-01-14 Procédé et appareil de traitement de phase WO2016116005A1 (fr)

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CN201510027968.8A CN105871533A (zh) 2015-01-20 2015-01-20 相位处理方法及装置
CN201510027968.8 2015-01-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116775546A (zh) * 2023-06-30 2023-09-19 海光信息技术股份有限公司 用于芯粒互联接口的数据传输方法及芯粒互联接口

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1304820A1 (fr) * 2000-07-06 2003-04-23 NEC Corporation Emetteur optique et systeme de transmission par fibre optique utilisant cet emetteur.
CN101084634A (zh) * 2004-12-15 2007-12-05 泰科电讯（美国）有限公司 用于光学信号发送器中的偏置和对齐控制的方法和设备
CN101176281A (zh) * 2005-05-18 2008-05-07 华为技术有限公司 保持光数据调制和周期调制光源间时间对准的方法和系统
CN101552642A (zh) * 2008-03-31 2009-10-07 华为技术有限公司 一种归零码调制脉冲与传输数据对齐的方法和装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101212257B (zh) * 2006-12-31 2011-06-15 华为技术有限公司 一种用于产生多种码型光归零码信号的光发射机及其方法
CN101494501B (zh) * 2008-01-25 2012-04-25 华为技术有限公司 多码型光发射机和光信号产生的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1304820A1 (fr) * 2000-07-06 2003-04-23 NEC Corporation Emetteur optique et systeme de transmission par fibre optique utilisant cet emetteur.
CN101084634A (zh) * 2004-12-15 2007-12-05 泰科电讯（美国）有限公司 用于光学信号发送器中的偏置和对齐控制的方法和设备
CN101176281A (zh) * 2005-05-18 2008-05-07 华为技术有限公司 保持光数据调制和周期调制光源间时间对准的方法和系统
CN101552642A (zh) * 2008-03-31 2009-10-07 华为技术有限公司 一种归零码调制脉冲与传输数据对齐的方法和装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116775546A (zh) * 2023-06-30 2023-09-19 海光信息技术股份有限公司 用于芯粒互联接口的数据传输方法及芯粒互联接口

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