WO2017033950A1 - Electronic circuit substrate - Google Patents
Electronic circuit substrate Download PDFInfo
- Publication number
- WO2017033950A1 WO2017033950A1 PCT/JP2016/074586 JP2016074586W WO2017033950A1 WO 2017033950 A1 WO2017033950 A1 WO 2017033950A1 JP 2016074586 W JP2016074586 W JP 2016074586W WO 2017033950 A1 WO2017033950 A1 WO 2017033950A1
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- WIPO (PCT)
- Prior art keywords
- inductor
- electronic circuit
- capacitor
- circuit board
- closed conductor
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims abstract description 38
- 239000004020 conductor Substances 0.000 claims abstract description 94
- 239000003990 capacitor Substances 0.000 claims abstract description 59
- 230000003071 parasitic effect Effects 0.000 claims abstract description 22
- 230000008878 coupling Effects 0.000 abstract description 12
- 238000010168 coupling process Methods 0.000 abstract description 12
- 238000005859 coupling reaction Methods 0.000 abstract description 12
- 230000004907 flux Effects 0.000 description 28
- 230000000694 effects Effects 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
Definitions
- the present invention relates to an electronic circuit board.
- a CPU main processing unit
- the operating voltage tends to decrease in order to reduce the power consumption.
- a large current fluctuation noise current
- a multilayer capacitor as a smoothing capacitor is arranged around the CPU so as to be connected to a power supply, and is frequently used as a countermeasure for stabilizing the power supply.
- the current is supplied from the multilayer capacitor to the CPU by quick charge / discharge when the current fluctuates at a high speed, thereby suppressing the voltage fluctuation of the power source.
- ESL Equivalent Series Inductance
- Patent Document 1 Patent Document 2, or Patent Document 3
- the internal electrodes and the side terminals are arranged so that the currents flowing in the adjacent terminal electrodes are opposite to each other.
- a multilayer capacitor has been proposed in which the mutual inductance is made negative, the parasitic inductor component of the capacitor is reduced, and low ESL is realized.
- an object of the present invention is to provide an electronic circuit board that can reduce an equivalent series inductance that is a parasitic inductance of a capacitor or an inductance of wiring of a mounting board.
- the electronic circuit board of the present invention includes a mounting board having a DC power supply layer and a ground layer, and a capacitor, and the capacitor is connected to the DC power supply layer and the ground layer via wiring and mounted on the mounting board.
- a first inductor that is a parasitic inductor component of the capacitor and a second inductor that is an inductor component of the wiring are connected in series, and at least one of the first inductor and the second inductor is magnetically connected. It has a closed conductor loop to be coupled.
- At least one of the first inductor and the second inductor is magnetically coupled to the closed conductor loop, so that the first inductor and the second inductor can be coupled according to Faraday's law.
- a counter electromotive force is generated in the closed conductor loop so as to prevent the time fluctuation of the magnetic flux corresponding to at least one of the inductances.
- the closed conductor loop is configured by a wiring pattern formed inside the mounting board or on the surface of the mounting board.
- the closed conductor loop is configured by the wiring pattern in the mounting board, thereby mainly preventing the time fluctuation of the magnetic flux corresponding to the inductance of the second inductor which is the inductor component of the wiring.
- the inductance (equivalent series inductance) of the wiring of the mounting board can be mainly reduced.
- a part of the closed conductor loop is one of the DC power supply layer and the ground layer.
- unnecessary wiring can be reduced by using either the DC power supply layer or the ground layer as a part of the closed conductor loop.
- a component having a conductor pattern is mounted on the mounting board, and at least a part of the closed conductor loop is the conductor pattern.
- At least a part of the closed conductor loop is a conductor pattern of a component mounted on the mounting board, so that the inductance of the first inductor that is a parasitic inductor component of the capacitor is mainly used. Can be prevented, and the parasitic inductance (equivalent series inductance) of the capacitor can be mainly reduced.
- the capacitor and the component are integrally formed.
- the capacitor and the part having the conductor pattern that is at least a part of the closed conductor loop are integrally formed, whereby the first inductor that is the parasitic inductor component of the capacitor is It can be coupled to the closed conductor loop with a magnetically large coupling coefficient.
- the parasitic inductance (equivalent series inductance) of the capacitor can be greatly reduced.
- the electronic circuit board of the present invention preferably has a plurality of the closed conductor loops.
- the electronic circuit board which can reduce the equivalent series inductance of the wiring of a capacitor
- FIG. 1 is a perspective view of an electronic circuit board according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along line AA in FIG. 9 is a cross-sectional view taken along line BB in FIG. 1 or a cross-sectional view taken along line DD in FIG.
- FIG. 12 is a cross-sectional view of the part cut along line EE in FIG. 11.
- FIG. 12 is a cross-sectional view of a part cut along line FF in FIG. 11.
- FIG. 1 is a perspective view showing a configuration example of an electronic circuit board 1 according to the first embodiment of the present invention
- FIG. 2 is a cross-sectional view taken along line AA of FIG.
- FIG. 3 is a sectional view taken along line BB in FIG.
- the electronic circuit board 1 includes a mounting substrate 111 having a ground layer 101 and a DC power supply layer 102 and a capacitor 104
- the capacitor 104 includes the ground layer 101 and the DC power supply layer 102.
- the capacitor 104 includes the ground layer 101 and the DC power supply layer 102.
- the capacitor 104 has a plurality of first internal electrodes 1041 and a plurality of second internal electrodes 1042, and each first internal electrode 1041 and each second internal electrode 1042 are stacked via a dielectric 1043. ing.
- the capacitor 104 includes a first terminal electrode 1044 and a second terminal electrode 1045.
- the plurality of first internal electrodes 1041 are connected to the first terminal electrode 1044, and the plurality of second internal electrodes 1042 are The second terminal electrode 1045 is connected.
- the first terminal electrode 1044 is connected to the ground layer 101 through the wiring 103a, and the second terminal electrode 1045 is connected to the DC power supply layer 102 through the wiring 103b.
- the capacitor 104 (capacitance component thereof) and the first inductor 301 that is a parasitic inductor component of the capacitor 104 and the wiring 103a. , 103b, the second inductor 302, which is the inductor component, is connected in series.
- the first internal electrode 1041 and the second internal electrode 1042 is drawn for short.
- the electronic circuit board 1 has a wiring pattern 105 formed on the surface of the mounting board 111.
- the electronic circuit board 1 has a closed conductor loop 110 formed by connecting both ends of the wiring pattern 105 to the DC power supply layer 102 via wirings 103 c and 103 d formed inside the mounting substrate 111.
- the equivalent circuit of the closed conductor loop 110 is represented by connecting an inductor 303, which is an inductor component of the closed conductor loop 110, and a resistor 304, which is a resistance component, in series in a loop shape.
- the inductor 303 of the closed conductor loop 110 is mainly composed of the second inductor 302 that is an inductor component of the wirings 103a and 103b. , Coupled through the generated magnetic field. Due to this coupling, a counter electromotive force is generated in the closed conductor loop 110 so as to prevent the time fluctuation of the magnetic flux generated by the noise current passing through the wirings 103a and 103b according to Faraday's law (the closed circuit loop 110 is generated by this counter electromotive force).
- the magnetic flux generated by the eddy current generated in the circuit is generated so as to prevent the time fluctuation of the magnetic flux generated by the noise current passing through the wirings 103a and 103b).
- the inductance (equivalent series inductance) of the second inductor 302 that is the inductor component of the wirings 103a and 103b can be mainly reduced.
- the inductance L is defined by the following formula (1) using the current I, the magnetic flux density B, the area S, and the time t. Considering this definition, the inductance is proportional to the time variation of the magnetic flux B ⁇ dS. Therefore, the inductance can be reduced by suppressing the time variation of the generated magnetic flux.
- FIG. 4 shows a loop conductor 201 which is a closed conductor.
- the magnetic flux 202 penetrating the inside of the loop of the loop conductor 201 is generated, an electromotive force is generated in a direction that cancels the generated magnetic flux 202 according to Faraday's law, an eddy current 204 flows in the loop conductor 201, and is opposite to the magnetic flux 202.
- Directional magnetic flux 203 is generated, and temporal fluctuation of the magnetic flux is suppressed.
- a closed conductor loop 110 is formed by connecting both ends of the wiring pattern 105 to the DC power supply layer 102 via wirings 103c and 103d.
- an electromotive force is generated in a direction that prevents an increase in magnetic flux generated by the flow of the noise current 108, and an eddy current 107 opposite to the noise current 108 flows through the closed conductor loop 110. This prevents the time fluctuation of the magnetic flux generated by.
- the equivalent series inductance of the second inductor 302 that is the inductor component of the wirings 103a and 103b of the mounting substrate 111 is reduced. be able to.
- the electronic circuit board 1 includes the mounting substrate 111 having the DC power supply layer 102 and the ground layer 101, and the capacitor 104.
- the first inductor 301 which is the parasitic inductor component of the capacitor 104
- the second inductor 302 which is the inductor component of the wirings 103a and 103b, are connected in series, and are mounted on the mounting substrate 111. Since the closed conductor loop 110 magnetically coupled to the inductor 302 is provided, the magnetic flux coupling corresponding to the inductance of the second inductor 302 is obtained by Faraday's law by magnetically coupling the second inductor 302 and the closed conductor loop 110. Back electromotive force is generated in closed conductor loop 110 to prevent time fluctuation That. Thereby, the equivalent series inductance which is the inductance of the wirings 103a and 103b of the mounting substrate 111 can be reduced.
- the closed conductor loop 110 is configured by wiring patterns (wirings 103 c and 103 d, the wiring pattern 105 and the DC power supply layer 102) formed inside the mounting board 111 or on the surface of the mounting board 111. Therefore, the time variation of the magnetic flux corresponding to the inductance of the second inductor 302 which is the inductor component of the wirings 103a and 103b is prevented, and the inductance (equivalent series inductance) of the wirings 103a and 103b of the mounting substrate 111 is mainly used. Can be reduced.
- a part of the closed conductor loop 110 is the DC power supply layer 102, and therefore, unnecessary wiring can be reduced by using the DC electrode layer 102 as a part of the closed conductor loop 110.
- FIG. 5 shows an equivalent circuit example of the electronic circuit board 1 when the closed conductor loop 110 and the second inductor 302 by the wirings 103a and 103b are magnetically coupled.
- This equivalent circuit example is equivalent to a capacitor 104 connected in series between the DC power supply layer 102 and the ground layer 101, a first inductor 301 that is a parasitic inductor of the capacitor 104, and wirings 103 a and 103 b of the mounting substrate 111.
- This is a resistance component of a closed conductor loop 110 formed by a circuit in which a second inductor 302 that is a series inductor component is connected in series, the wiring pattern 105, the wirings 103c and 103d of the mounting substrate 111, and the DC power supply layer 102.
- a circuit in which a resistor 304 and an inductor 303 that is an inductor component of the closed conductor loop 110 are connected in series, and the second inductor 302 and the inductor 303 of the closed conductor loop 110 are coupled with a coupling coefficient k. is there.
- the capacitance of the capacitor 104 is 1 ⁇ F
- the inductance of the first inductor 301 is 100 pH
- the inductance of the second inductor 302 is 100 pH
- the inductance of the inductor 303 of the closed conductor loop 110 is 1 pH
- the resistance value of the resistor 304 FIG.
- the wiring pattern 105 formed on the surface of the mounting substrate 111 constitutes a part of the closed conductor loop 110, but the wiring pattern 105 may be formed inside the mounting substrate 111. good.
- both ends of the wiring pattern 105 are connected to the DC power supply layer 102 via the wirings 103c and 103d to form the closed conductor loop 110.
- the both ends of 105 may be formed by being connected to the ground layer 101 via wiring formed inside the mounting substrate 111. Even in this case, the same effect as the electronic circuit board 1 of the first embodiment can be obtained. Further, as in the electronic circuit board 2 shown in FIG.
- the closed conductor loop 110 is configured such that both ends of the wiring pattern 105 are connected to the ground layer 101 and the DC power source via the wirings 103 e and 103 f formed inside the mounting substrate 111. It may be formed by being connected to an independent wiring pattern 109 that is not connected to the layer 102.
- FIG. 7 is a cross-sectional view of the electronic circuit board 2 corresponding to the cross-sectional view of the electronic circuit board 1 shown in FIG. As long as the closed conductor loop is formed, the eddy current 107 generated by Faraday's law can reduce the equivalent series inductance that is the inductance of the wiring of the mounting board.
- the electronic circuit board 1 having one closed conductor loop 110 is described. However, even if there are a plurality of closed conductor loops coupled to the second inductor 302 through a generated magnetic field. Good. For example, two closed conductor loops may be formed so as to sandwich a place where the capacitor 104 is mounted. ⁇ Second Embodiment>
- FIG. 8 is a perspective view showing an overall configuration example of the electronic circuit board 3 according to the second embodiment of the present invention.
- the electronic circuit board 3 will be described mainly with respect to differences from the electronic device 1 of the first embodiment, and description of common matters will be omitted as appropriate. Elements common to the electronic device 1 of the first embodiment are denoted by the same reference numerals, and description of the common elements is omitted.
- the electronic circuit board 3 is mounted on the surface of the mounting board 111 with the capacitor 104 connected to the ground layer 101 and the power supply layer 102 via the wirings 103 a and 103 b of the mounting board 111. ing.
- a component 112 having a conductor pattern 305 is mounted on the surface of the mounting board 111.
- two components 112 are mounted on the surface of the mounting board 111 with the capacitor 104 interposed therebetween.
- FIG. 9 is a cross-sectional view taken along the line CC of FIG.
- the component 112 has a conductor pattern 305 as shown in FIGS.
- a dielectric 3043 is formed around the conductor pattern 305.
- the electronic circuit board 3 has a closed conductor loop 310 formed by connecting both ends of the conductor pattern 305 to the DC power supply layer 102 via the wirings 103 g and 103 h of the mounting board 111. Have two.
- the equivalent circuit of the closed conductor loop 310 is represented by connecting an inductor 313 that is an inductor component of the closed conductor loop 310 and a resistor 304 that is a resistance component in series in a loop shape.
- the closed conductor loop 310 is generated with the first inductor 301 that is a parasitic inductor of the capacitor 104 and the second inductor 302 that is an equivalent series inductor of the wirings 103 a and 103 b of the mounting substrate 111 connected to the capacitor 104. Coupling through a magnetic field.
- a cross-sectional view taken along the line DD in FIG. 8 can be represented in FIG. 3 as in the first embodiment.
- the noise current 108 flows through the capacitor 104 through the wirings 103a and 103b and flows into the ground layer 101.
- an electromotive force is generated in a direction that prevents an increase in magnetic flux generated by the flow of the noise current 108, and an eddy current 107 opposite to the noise current 108 flows in the closed conductor loop 310. This prevents time fluctuations of the generated magnetic flux.
- the magnetic flux generated by the eddy current 107 cancels the magnetic flux generated by the noise current 108 inside the capacitor 104 and inside the mounting substrate 111, so that the first inductor 301, which is a parasitic inductor of the capacitor 104, and the wiring of the mounting substrate 111.
- Both of the equivalent series inductances of the second inductor 302, which are the inductor components 103a and 103b, can be reduced.
- FIG. 10 shows an equivalent circuit example for the electronic circuit board 3.
- This equivalent circuit example is equivalent to a capacitor 104 connected in series between the DC power supply layer 102 and the ground layer 101, a first inductor 301 that is a parasitic inductor of the capacitor 104, and wirings 103 a and 103 b of the mounting substrate 111.
- This is a resistance component of a closed conductor loop 310 formed by a circuit in which a second inductor 302 that is a series inductor component is connected in series, a conductor pattern 305, wirings 103g and 103h of a mounting substrate 111, and a DC power supply layer 102.
- the electronic circuit board 3 is formed with a plurality of closed conductor loops 310, it is possible to obtain a greater effect of reducing the equivalent series inductance.
- the larger the coupling coefficient between the closed conductor loop 310 and the first inductor 301 or the second inductor 302 (closer to 1) the more the equivalent series inductance becomes.
- the effect of reducing becomes large, in reality, it is difficult to set the coupling coefficient to 1.
- By having the plurality of closed conductor loops 310 even if the coupling coefficient between each closed conductor loop 310 and the first inductor 301 or the second inductor 301 is smaller than 1, it is generated in each closed conductor loop 310. By adding the effects of the back electromotive force, it is possible to obtain a greater reduction effect of the equivalent series inductance.
- the closed conductor loop 310 may be formed by connecting both ends of the conductor pattern 305 to the ground layer 101 via wiring formed inside the mounting substrate 111.
- the closed conductor loop 310 is connected at both ends of the conductor pattern 305 to independent wiring patterns that are not connected to the ground layer 101 or the DC power supply layer 102 via wiring formed inside the mounting substrate 111. It may be formed by this.
- the closed conductor loop 310 is formed by connecting both ends of the wiring pattern 305 to independent wiring patterns that are not connected to the ground layer 101 or the DC power supply layer 102, and the independent wiring patterns are formed on the mounting substrate. It may be formed on the surface of 111 or inside the component 112. In this case, the parasitic inductance (equivalent series inductance) of the capacitor 104 can be mainly reduced.
- FIG. 11 is a perspective view showing a configuration example of an electronic circuit board 4 according to the third embodiment of the present invention.
- the electronic circuit board 4 will be described mainly with respect to differences from the electronic circuit board 3 of the second embodiment, and description of common matters will be omitted as appropriate. Elements common to the electronic circuit board 3 of the second embodiment are denoted by the same reference numerals, and description of the common elements is omitted.
- the component having the conductor pattern 305 and the capacitor 104 are integrally formed in place of the capacitor 104 and the two components 112 having the conductor pattern 305 in the electronic circuit substrate 3 of the second embodiment.
- the component 411 is mounted on the surface of the mounting substrate 111. In the electronic circuit board 4 shown in FIG. 11, the component 411 shows an example having one conductor pattern 305.
- FIG. 12 is an exploded perspective view of the part 411
- FIG. 13 is a sectional view of the part 411 cut along the line EE in FIG. 11
- FIG. 14 is a part cut along the line FF in FIG. FIG.
- the first internal electrodes 1041 and the second internal electrodes 1042 are alternately stacked with the dielectric 1043 interposed therebetween, and the conductor pattern 305 is connected to the first internal electrodes via the dielectric 1043.
- 1041 and the second internal electrode 1042 are arranged apart from each other.
- the conductor pattern 305 is arranged so that at least a part of the conductor pattern 305 overlaps with the first internal electrode 1041 and the second internal electrode 1042 when viewed from the stacking direction of the first internal electrode 1041 and the second internal electrode 1042. Yes.
- the other points are the same as those of the electronic circuit board 3 of the second embodiment.
- the component 411 in which the capacitor 104 and the component having the conductor pattern 305 that is a part of the closed conductor loop 310 are integrally formed is formed on the mounting substrate 111, so that the parasitic inductor of the capacitor 104 is formed.
- the first inductor 301 as a component can be coupled to the closed conductor loop 310 with a magnetically large coupling coefficient. Thereby, the parasitic inductance (equivalent series inductance) of the capacitor 104 can be greatly reduced.
- the electronic circuit boards of the first to third embodiments described above may be used as a power supply module board such as a DC-DC converter, or a board used in a set of a smartphone, a PC, a notebook PC, or the like. It may be used as a board such as a graphic board, a microcomputer board, a memory board, and a PCI Express board.
- a power supply module board such as a DC-DC converter, or a board used in a set of a smartphone, a PC, a notebook PC, or the like. It may be used as a board such as a graphic board, a microcomputer board, a memory board, and a PCI Express board.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Provided is an electronic circuit substrate capable of reducing equivalent series inductance, which is the parasitic inductance of a capacitor or the inductance of the wiring of a mounting substrate. An electronic circuit substrate 1 having a capacitor 104 and a mounting substrate 111 that has a DC power source layer and a ground layer, the electronic circuit substrate 1 being characterized in that the capacitor 104 is mounted onto the mounting substrate 111 by being connected to the DC power source layer and the ground layer via wiring 103a, 103b, in that a first inductor, which is the parasitic inductor component of the capacitor 104, and a second inductor, which is the inductor component for the wiring 103a, 103b, are connected in series, and by also having a closed conductor loop for magnetically coupling with the first inductor and/or the second inductor.
Description
本発明は、電子回路基板に関するものである。
The present invention relates to an electronic circuit board.
近年、情報処理装置に用いられるCPU(主演算処理装置)は、処理スピードの向上及び高集積化によって、動作周波数が高くなると共に消費電流が著しく増加している。そしてこれに伴い、消費電力を低減化するために動作電圧が減少する傾向にあった。従って、CPUへの電力供給用の電源においては、より高速で大きな電流変動(ノイズ電流)が生じるようになり、この電流変動に伴う電圧変動を電源の許容値内に抑えることが非常に困難になった。この為、平滑用コンデンサとしての積層コンデンサが電源に接続される形でCPUの周辺に配置され、電源の安定化対策に頻繁に使用されるようになった。つまり、電流の高速で過渡的な変動時に素早い充放電によって、この積層コンデンサからCPUに電流を供給して、電源の電圧変動を抑えるようにしていた。
In recent years, a CPU (main processing unit) used in an information processing apparatus has an increased operating frequency and a significantly increased current consumption due to an improvement in processing speed and higher integration. Along with this, the operating voltage tends to decrease in order to reduce the power consumption. Accordingly, in the power supply for supplying power to the CPU, a large current fluctuation (noise current) occurs at a higher speed, and it is very difficult to suppress the voltage fluctuation accompanying the current fluctuation within the allowable value of the power supply. became. For this reason, a multilayer capacitor as a smoothing capacitor is arranged around the CPU so as to be connected to a power supply, and is frequently used as a countermeasure for stabilizing the power supply. In other words, the current is supplied from the multilayer capacitor to the CPU by quick charge / discharge when the current fluctuates at a high speed, thereby suppressing the voltage fluctuation of the power source.
CPUの動作周波数の一層の高周波数化及び動作電圧の一層の低電圧化に伴って、電流変動はより高速且つ大きなものとなり、積層コンデンサ自身が有している等価直列インダクタンス(ESL:Equivalent Series Inductance)が電源の電圧変動に大きく影響するようになった。この結果、電流の変動が生じるのに合わせてこのESLが積層コンデンサの充放電を阻害する為、電源の電圧変動が大きくなり易く、今後のCPUの高速化には適応できなくなりつつあった。
As the operating frequency of the CPU is further increased and the operating voltage is further decreased, the current fluctuation becomes faster and larger, and the equivalent series inductance (ESL: Equivalent Series Inductance) possessed by the multilayer capacitor itself. ) Greatly affects the voltage fluctuation of the power supply. As a result, the ESL inhibits charging / discharging of the multilayer capacitor as the current fluctuates, so that the voltage fluctuation of the power supply tends to increase, and it has become difficult to adapt to future CPU speedup.
これに対し、例えば、特許文献1、特許文献2または特許文献3に示されるような、隣り合う端子電極において流れる電流が相互に逆向きになるように、内部電極および側面端子を配置することで、相互インダクタンスを負にし、コンデンサが持つ寄生のインダクタ成分を減らし、低ESLを実現した積層コンデンサが提案されている。
On the other hand, for example, as shown in Patent Document 1, Patent Document 2, or Patent Document 3, the internal electrodes and the side terminals are arranged so that the currents flowing in the adjacent terminal electrodes are opposite to each other. A multilayer capacitor has been proposed in which the mutual inductance is made negative, the parasitic inductor component of the capacitor is reduced, and low ESL is realized.
特許文献1、特許文献2および特許文献3に記載の技術は、コンデンサ素子単体の寄生インダクタンスを低減させるものであるが、実際にはコンデンサ以外に実装基板の配線のインダクタンスも電源の電圧変動の抑制を阻害する要因になる。本発明は上記事実を考慮し、コンデンサの寄生インダクタンスまたは実装基板の配線のインダクタンスである等価直列インダクタンスを低減し得る電子回路基板を提供することを目的とする。
The techniques described in Patent Document 1, Patent Document 2 and Patent Document 3 reduce the parasitic inductance of the capacitor element alone, but actually, the inductance of the wiring of the mounting board in addition to the capacitor also suppresses the voltage fluctuation of the power supply. It becomes a factor to inhibit. In consideration of the above-described facts, an object of the present invention is to provide an electronic circuit board that can reduce an equivalent series inductance that is a parasitic inductance of a capacitor or an inductance of wiring of a mounting board.
本発明の電子回路基板は、DC電源層とグランド層を有する実装基板とコンデンサとを有し、前記コンデンサが、前記DC電源層と前記グランド層に配線を介して接続されて前記実装基板に実装され、前記コンデンサの寄生インダクタ成分である第1のインダクタと、前記配線のインダクタ成分である第2のインダクタとが直列に接続され、前記第1のインダクタおよび前記第2のインダクタの少なくとも一方と磁気結合する閉導体ループを有することを特徴とする。
The electronic circuit board of the present invention includes a mounting board having a DC power supply layer and a ground layer, and a capacitor, and the capacitor is connected to the DC power supply layer and the ground layer via wiring and mounted on the mounting board. A first inductor that is a parasitic inductor component of the capacitor and a second inductor that is an inductor component of the wiring are connected in series, and at least one of the first inductor and the second inductor is magnetically connected. It has a closed conductor loop to be coupled.
上記特徴の電子回路基板によれば、第1のインダクタおよび第2のインダクタの少なくとも一方と閉導体ループが磁気的に結合することによって、ファラデーの法則により、第1のインダクタおよび第2のインダクタの少なくとも一方のインダクタンスに対応する磁束の時間変動を妨げるように閉導体ループに逆起電力が発生する。これにより、コンデンサの寄生インダクタンス又は実装基板の配線のインダクタンスである等価直列インダクタンスを減少させることができる。
According to the electronic circuit board having the above characteristics, at least one of the first inductor and the second inductor is magnetically coupled to the closed conductor loop, so that the first inductor and the second inductor can be coupled according to Faraday's law. A counter electromotive force is generated in the closed conductor loop so as to prevent the time fluctuation of the magnetic flux corresponding to at least one of the inductances. Thereby, the equivalent series inductance which is the parasitic inductance of a capacitor | condenser or the inductance of the wiring of a mounting board | substrate can be reduced.
さらに、本発明の電子回路基板は、前記閉導体ループは、前記実装基板の内部または前記実装基板の表面に形成された配線パターンによって構成されることが好ましい。
Furthermore, in the electronic circuit board of the present invention, it is preferable that the closed conductor loop is configured by a wiring pattern formed inside the mounting board or on the surface of the mounting board.
上記特徴の電子回路基板によれば、閉導体ループを実装基板内の配線パターンで構成することによって、主に、配線のインダクタ成分である第2のインダクタのインダクタンスに対応する磁束の時間変動を妨げ、実装基板の配線のインダクタンス(等価直列インダクタンス)を主に減らすことができる。
According to the electronic circuit board having the above characteristics, the closed conductor loop is configured by the wiring pattern in the mounting board, thereby mainly preventing the time fluctuation of the magnetic flux corresponding to the inductance of the second inductor which is the inductor component of the wiring. The inductance (equivalent series inductance) of the wiring of the mounting board can be mainly reduced.
さらに、本発明の電子回路基板は、前記閉導体ループの一部は、前記DC電源層または前記グランド層のどちらか一方であることが好ましい。
Furthermore, in the electronic circuit board of the present invention, it is preferable that a part of the closed conductor loop is one of the DC power supply layer and the ground layer.
上記特徴の電子回路基板によれば、閉導体ループの一部として、DC電源層またはグランド層のどちらか一方を用いることで、不要な配線を減らすことができる。
According to the electronic circuit board having the above characteristics, unnecessary wiring can be reduced by using either the DC power supply layer or the ground layer as a part of the closed conductor loop.
さらに、本発明の電子回路基板は、導体パターンを有する部品が前記実装基板に実装され、前記閉導体ループの少なくとも一部は、前記導体パターンであることが好ましい。
In the electronic circuit board of the present invention, it is preferable that a component having a conductor pattern is mounted on the mounting board, and at least a part of the closed conductor loop is the conductor pattern.
上記特徴の電子回路基板によれば、閉導体ループの少なくとも一部が、実装基板に実装された部品の導体パターンであることによって、主に、コンデンサの寄生インダクタ成分である第1のインダクタのインダクタンスに対応する磁束の時間変動を妨げ、コンデンサの寄生インダクタンス(等価直列インダクタンス)を主に減らすことができる。
According to the electronic circuit board having the above characteristics, at least a part of the closed conductor loop is a conductor pattern of a component mounted on the mounting board, so that the inductance of the first inductor that is a parasitic inductor component of the capacitor is mainly used. Can be prevented, and the parasitic inductance (equivalent series inductance) of the capacitor can be mainly reduced.
さらに、本発明の電子回路基板は、前記コンデンサと前記部品とが一体で形成されていることが好ましい。
Furthermore, in the electronic circuit board of the present invention, it is preferable that the capacitor and the component are integrally formed.
上記特徴の電子回路基板によれば、コンデンサと閉導体ループの少なくとも一部である導体パターンを有する部品とが一体で形成されていることによって、コンデンサの寄生インダクタ成分である第1のインダクタが、閉導体ループと磁気的に大きな結合係数で結合することができる。これによって、コンデンサの寄生インダクタンス(等価直列インダクタンス)を大きく減らすことができる。
According to the electronic circuit board having the above characteristics, the capacitor and the part having the conductor pattern that is at least a part of the closed conductor loop are integrally formed, whereby the first inductor that is the parasitic inductor component of the capacitor is It can be coupled to the closed conductor loop with a magnetically large coupling coefficient. Thereby, the parasitic inductance (equivalent series inductance) of the capacitor can be greatly reduced.
さらに、本発明の電子回路基板は、前記閉導体ループを複数有することが好ましい。
Furthermore, the electronic circuit board of the present invention preferably has a plurality of the closed conductor loops.
上記特徴の電子回路基板によれば、閉導体ループを複数有することによって、より大きな等価直列インダクタンスの減少効果を得ることができる。
According to the electronic circuit board having the above characteristics, by having a plurality of closed conductor loops, a larger effect of reducing the equivalent series inductance can be obtained.
本発明によれば、コンデンサまたは実装基板の配線の等価直列インダクタンスを低減し得る電子回路基板を提供することができる。
ADVANTAGE OF THE INVENTION According to this invention, the electronic circuit board which can reduce the equivalent series inductance of the wiring of a capacitor | condenser or a mounting board can be provided.
以下、本発明の実施の形態について図面を参照して詳細に説明する。なお、以下の説明は本発明の実施形態の一部を例示するものであり、本発明はこれら実施形態に限定されるものではなく、形態が本発明の技術的思想を有するものである限り、本発明の範囲に含まれる。各実施形態における各構成及びそれらの組み合わせなどは一例であり、本発明の趣旨から逸脱しない範囲内で、構成の付加、省略、置換、およびその他の変更が可能である。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following description exemplifies a part of the embodiments of the present invention, and the present invention is not limited to these embodiments, so long as the form has the technical idea of the present invention. It is included in the scope of the present invention. Each configuration in each embodiment, a combination thereof, and the like are examples, and the addition, omission, replacement, and other changes of the configuration can be made without departing from the spirit of the present invention.
<第1の実施の形態>
図1は、本発明の第1の実施の形態に係る電子回路基板1の構成例を示す斜視図であり、図2は、図1のA-A線に沿った断面図である。図3は、図1のB-B線に沿った断面図である。図1~3に示すように、電子回路基板1は、グランド層101およびDC電源層102を有する実装基板111とコンデンサ104とを有しており、コンデンサ104が、グランド層101とDC電源層102に実装基板111の配線103a、103bを介して接続されて実装基板111の表面に実装されている。 <First Embodiment>
FIG. 1 is a perspective view showing a configuration example of anelectronic circuit board 1 according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line AA of FIG. FIG. 3 is a sectional view taken along line BB in FIG. As shown in FIGS. 1 to 3, the electronic circuit board 1 includes a mounting substrate 111 having a ground layer 101 and a DC power supply layer 102 and a capacitor 104, and the capacitor 104 includes the ground layer 101 and the DC power supply layer 102. Are mounted on the surface of the mounting substrate 111 by being connected via the wirings 103 a and 103 b of the mounting substrate 111.
図1は、本発明の第1の実施の形態に係る電子回路基板1の構成例を示す斜視図であり、図2は、図1のA-A線に沿った断面図である。図3は、図1のB-B線に沿った断面図である。図1~3に示すように、電子回路基板1は、グランド層101およびDC電源層102を有する実装基板111とコンデンサ104とを有しており、コンデンサ104が、グランド層101とDC電源層102に実装基板111の配線103a、103bを介して接続されて実装基板111の表面に実装されている。 <First Embodiment>
FIG. 1 is a perspective view showing a configuration example of an
コンデンサ104は複数の第1の内部電極1041と複数の第2の内部電極1042を有し、各々の第1の内部電極1041と各々の第2の内部電極1042は誘電体1043を介して積層されている。コンデンサ104は、第1の端子電極1044と第2の端子電極1045とを有し、複数の第1の内部電極1041は第1の端子電極1044に接続され、複数の第2の内部電極1042は第2の端子電極1045に接続されている。第1の端子電極1044が配線103aを介してグランド層101に接続され、第2の端子電極1045が配線103bを介して、DC電源層102に接続されている。これによって、図5の等価回路図に示すように、DC電源層102とグランド層101の間に、コンデンサ104(の容量成分)とコンデンサ104の寄生インダクタ成分である第1のインダクタ301と配線103a、103bのインダクタ成分である第2のインダクタ302とが直列に接続されている。尚、図3においては、第1の内部電極1041と第2の内部電極1042は略して1つずつのみを描いている。
The capacitor 104 has a plurality of first internal electrodes 1041 and a plurality of second internal electrodes 1042, and each first internal electrode 1041 and each second internal electrode 1042 are stacked via a dielectric 1043. ing. The capacitor 104 includes a first terminal electrode 1044 and a second terminal electrode 1045. The plurality of first internal electrodes 1041 are connected to the first terminal electrode 1044, and the plurality of second internal electrodes 1042 are The second terminal electrode 1045 is connected. The first terminal electrode 1044 is connected to the ground layer 101 through the wiring 103a, and the second terminal electrode 1045 is connected to the DC power supply layer 102 through the wiring 103b. As a result, as shown in the equivalent circuit diagram of FIG. 5, between the DC power supply layer 102 and the ground layer 101, the capacitor 104 (capacitance component thereof) and the first inductor 301 that is a parasitic inductor component of the capacitor 104 and the wiring 103a. , 103b, the second inductor 302, which is the inductor component, is connected in series. In FIG. 3, only one each of the first internal electrode 1041 and the second internal electrode 1042 is drawn for short.
図1、2に示すように、電子回路基板1は、実装基板111の表面に形成された配線パターン105を有している。電子回路基板1は、配線パターン105の両端が実装基板111の内部に形成された配線103c、103dを介してDC電源層102に接続されることによって形成される閉導体ループ110を有している。この閉導体ループ110の等価回路は、図5に示すように、閉導体ループ110のインダクタ成分であるインダクタ303と抵抗成分である抵抗304を直列にループ状に接続することで表される。
As shown in FIGS. 1 and 2, the electronic circuit board 1 has a wiring pattern 105 formed on the surface of the mounting board 111. The electronic circuit board 1 has a closed conductor loop 110 formed by connecting both ends of the wiring pattern 105 to the DC power supply layer 102 via wirings 103 c and 103 d formed inside the mounting substrate 111. . As shown in FIG. 5, the equivalent circuit of the closed conductor loop 110 is represented by connecting an inductor 303, which is an inductor component of the closed conductor loop 110, and a resistor 304, which is a resistance component, in series in a loop shape.
本実施形態では、閉導体ループ110は、主に実装基板111内に形成されるため、閉導体ループ110のインダクタ303は、主に、配線103a、103bのインダクタ成分である第2のインダクタ302と、発生する磁界を介して結合する。この結合によって、ファラデーの法則により、配線103a、103bを通るノイズ電流によって発生する磁束の時間変動を妨げるように、閉導体ループ110に逆起電力が発生する(この逆起電力により閉回路ループ110に発生する渦電流による磁束が、配線103a、103bを通るノイズ電流によって発生する磁束の時間変動を妨げるように発生する)。これにより、配線103a、103bのインダクタ成分である第2のインダクタ302のインダクタンス(等価直列インダクタス)を主に減らすことができる。
In this embodiment, since the closed conductor loop 110 is mainly formed in the mounting substrate 111, the inductor 303 of the closed conductor loop 110 is mainly composed of the second inductor 302 that is an inductor component of the wirings 103a and 103b. , Coupled through the generated magnetic field. Due to this coupling, a counter electromotive force is generated in the closed conductor loop 110 so as to prevent the time fluctuation of the magnetic flux generated by the noise current passing through the wirings 103a and 103b according to Faraday's law (the closed circuit loop 110 is generated by this counter electromotive force). The magnetic flux generated by the eddy current generated in the circuit is generated so as to prevent the time fluctuation of the magnetic flux generated by the noise current passing through the wirings 103a and 103b). As a result, the inductance (equivalent series inductance) of the second inductor 302 that is the inductor component of the wirings 103a and 103b can be mainly reduced.
この原理について、以下に詳しく説明する。インダクタンスLは、電流I、磁束密度B、面積Sおよび時間tを用いて以下の数式(1)で定義される。この定義に従って考えると、インダクタンスは磁束B・dSの時間変動に比例する。従って、発生する磁束の時間変動を抑えればインダクタンスを低減できる。
This principle will be described in detail below. The inductance L is defined by the following formula (1) using the current I, the magnetic flux density B, the area S, and the time t. Considering this definition, the inductance is proportional to the time variation of the magnetic flux B · dS. Therefore, the inductance can be reduced by suppressing the time variation of the generated magnetic flux.
図4に閉じた導体であるループ導体201を示す。ループ導体201のループの内部を貫く磁束202が発生すると、ファラデーの法則により、その発生した磁束202を打ち消す方向に起電力が発生し、ループ導体201に渦電流204が流れ、磁束202とは逆向きの磁束203が発生し、磁束の時間変動が抑制される。
FIG. 4 shows a loop conductor 201 which is a closed conductor. When the magnetic flux 202 penetrating the inside of the loop of the loop conductor 201 is generated, an electromotive force is generated in a direction that cancels the generated magnetic flux 202 according to Faraday's law, an eddy current 204 flows in the loop conductor 201, and is opposite to the magnetic flux 202. Directional magnetic flux 203 is generated, and temporal fluctuation of the magnetic flux is suppressed.
図3において、DC電源層102にノイズが発生すると、配線103a、103bを介して、コンデンサ104を通過してグランド層101にノイズ電流108が流れる。その時、断面(図3における紙面)に垂直な方向の磁束が発生する。
In FIG. 3, when noise is generated in the DC power supply layer 102, a noise current 108 flows through the capacitor 104 through the wirings 103 a and 103 b to the ground layer 101. At that time, a magnetic flux in a direction perpendicular to the cross section (paper surface in FIG. 3) is generated.
図2に示すように、配線パターン105の両端が配線103c、103dを介してDC電源層102に接続されることで、閉導体ループ110が形成されている。ファラデーの法則によって、ノイズ電流108が流れることによって発生する磁束の増加を妨げる方向の起電力が発生し、ノイズ電流108とは逆向きの渦電流107がこの閉導体ループ110に流れ、ノイズ電流108により発生する磁束の時間変動を妨げる。渦電流107により発生した磁束は、ノイズ電流108により発生する実装基板111内部の磁束を打ち消すため、実装基板111の配線103a、103bのインダクタ成分である第2のインダクタ302の等価直列インダクタンスを低減することができる。
As shown in FIG. 2, a closed conductor loop 110 is formed by connecting both ends of the wiring pattern 105 to the DC power supply layer 102 via wirings 103c and 103d. According to Faraday's law, an electromotive force is generated in a direction that prevents an increase in magnetic flux generated by the flow of the noise current 108, and an eddy current 107 opposite to the noise current 108 flows through the closed conductor loop 110. This prevents the time fluctuation of the magnetic flux generated by. Since the magnetic flux generated by the eddy current 107 cancels out the magnetic flux inside the mounting substrate 111 generated by the noise current 108, the equivalent series inductance of the second inductor 302 that is the inductor component of the wirings 103a and 103b of the mounting substrate 111 is reduced. be able to.
このように、電子回路基板1は、DC電源層102とグランド層101を有する実装基板111とコンデンサ104とを有し、コンデンサ104が、DC電源層102とグランド層101に配線103a、103bを介して接続されて実装基板111に実装され、コンデンサ104の寄生インダクタ成分である第1のインダクタ301と、配線103a、103bのインダクタ成分である第2のインダクタ302とが直列に接続され、第2のインダクタ302と磁気結合する閉導体ループ110を有するので、第2のインダクタ302と閉導体ループ110が磁気的に結合することによって、ファラデーの法則により、第2のインダクタ302のインダクタンスに対応する磁束の時間変動を妨げるように閉導体ループ110に逆起電力が発生する。これにより、実装基板111の配線103a、103bのインダクタンスである等価直列インダクタンスを減少させることができる。
As described above, the electronic circuit board 1 includes the mounting substrate 111 having the DC power supply layer 102 and the ground layer 101, and the capacitor 104. The first inductor 301, which is the parasitic inductor component of the capacitor 104, and the second inductor 302, which is the inductor component of the wirings 103a and 103b, are connected in series, and are mounted on the mounting substrate 111. Since the closed conductor loop 110 magnetically coupled to the inductor 302 is provided, the magnetic flux coupling corresponding to the inductance of the second inductor 302 is obtained by Faraday's law by magnetically coupling the second inductor 302 and the closed conductor loop 110. Back electromotive force is generated in closed conductor loop 110 to prevent time fluctuation That. Thereby, the equivalent series inductance which is the inductance of the wirings 103a and 103b of the mounting substrate 111 can be reduced.
さらに、電子回路基板1は、閉導体ループ110は、実装基板111の内部または実装基板111の表面に形成された配線パターン(配線103c、103d、配線パターン105およびDC電源層102)によって構成されているので、主に、配線103a、103bのインダクタ成分である第2のインダクタ302のインダクタンスに対応する磁束の時間変動を妨げ、実装基板111の配線103a、103bのインダクタンス(等価直列インダクタンス)を主に減らすことができる。
Further, in the electronic circuit board 1, the closed conductor loop 110 is configured by wiring patterns ( wirings 103 c and 103 d, the wiring pattern 105 and the DC power supply layer 102) formed inside the mounting board 111 or on the surface of the mounting board 111. Therefore, the time variation of the magnetic flux corresponding to the inductance of the second inductor 302 which is the inductor component of the wirings 103a and 103b is prevented, and the inductance (equivalent series inductance) of the wirings 103a and 103b of the mounting substrate 111 is mainly used. Can be reduced.
電子回路基板1は、閉導体ループ110の一部は、DC電源層102であるので、閉導体ループ110の一部として、DC電極層102を用いることで、不要な配線を減らすことができる。
In the electronic circuit board 1, a part of the closed conductor loop 110 is the DC power supply layer 102, and therefore, unnecessary wiring can be reduced by using the DC electrode layer 102 as a part of the closed conductor loop 110.
図5は電子回路基板1について、閉導体ループ110と配線103a、103bによる第2のインダクタ302とが磁気的に結合した場合の等価回路例を示している。この等価回路例は、DC電源層102とグランド層101の間に直列に接続されるコンデンサ104と、コンデンサ104の寄生インダクタである第1のインダクタ301と、実装基板111の配線103a、103bの等価直列インダクタ成分である第2のインダクタ302とが直列に接続された回路と、配線パターン105、実装基板111の配線103c、103d及びDC電源層102で形成される閉導体ループ110の抵抗成分である抵抗304と閉導体ループ110のインダクタ成分であるインダクタ303とが直列に接続された回路とを含み、第2のインダクタ302と閉導体ループ110のインダクタ303が結合係数kで結合しているものである。この等価回路例において、コンデンサ104のキャパシタンスを1μF、第1のインダクタ301のインダクタンスを100pH、第2のインダクタ302のインダクタンスを100pH、閉導体ループ110のインダクタ303のインダクタンスを1pH、抵抗304の抵抗値を0.1μΩとしたときの、等価回路のDC電源層102とグランド層101の間のインピーダンスの回路シミュレータによる計算結果を図6に示す。結合係数kが0、0.8、1と増加するに従って、DC電源層102とグランド層101の間の等価直列インダクタ成分のインダクタンスが減少することが図6よりわかる。k=0の場合は、閉導体ループ110が存在しない場合と等価であり、閉導体ループ110の存在により、DC電源層102とグランド層101の間の等価直列インダクタ成分のインダクタンスが減少することがわかる。
FIG. 5 shows an equivalent circuit example of the electronic circuit board 1 when the closed conductor loop 110 and the second inductor 302 by the wirings 103a and 103b are magnetically coupled. This equivalent circuit example is equivalent to a capacitor 104 connected in series between the DC power supply layer 102 and the ground layer 101, a first inductor 301 that is a parasitic inductor of the capacitor 104, and wirings 103 a and 103 b of the mounting substrate 111. This is a resistance component of a closed conductor loop 110 formed by a circuit in which a second inductor 302 that is a series inductor component is connected in series, the wiring pattern 105, the wirings 103c and 103d of the mounting substrate 111, and the DC power supply layer 102. A circuit in which a resistor 304 and an inductor 303 that is an inductor component of the closed conductor loop 110 are connected in series, and the second inductor 302 and the inductor 303 of the closed conductor loop 110 are coupled with a coupling coefficient k. is there. In this equivalent circuit example, the capacitance of the capacitor 104 is 1 μF, the inductance of the first inductor 301 is 100 pH, the inductance of the second inductor 302 is 100 pH, the inductance of the inductor 303 of the closed conductor loop 110 is 1 pH, and the resistance value of the resistor 304 FIG. 6 shows the result of calculation by the circuit simulator of the impedance between the DC power supply layer 102 and the ground layer 101 of the equivalent circuit when the current is 0.1 μΩ. 6 that the inductance of the equivalent series inductor component between the DC power supply layer 102 and the ground layer 101 decreases as the coupling coefficient k increases to 0, 0.8, and 1. The case where k = 0 is equivalent to the case where the closed conductor loop 110 is not present, and the presence of the closed conductor loop 110 may reduce the inductance of the equivalent series inductor component between the DC power supply layer 102 and the ground layer 101. Recognize.
第1の実施の形態では、実装基板111の表面に形成された配線パターン105が閉導体ループ110の一部を構成していたが、配線パターン105が実装基板111の内部に形成されていても良い。また、第1の実施の形態では、配線パターン105の両端がDC電源層102に配線103c、103dを介して接続されて閉導体ループ110が形成されていたが、閉導体ループ110は、配線パターン105の両端が実装基板111の内部に形成された配線を介してグランド層101に接続されることによって形成されるものであっても良い。この場合でも第1の実施形態の電子回路基板1と同様の効果が得られる。また、図7に示す電子回路基板2のように、閉導体ループ110は、配線パターン105の両端が、実装基板111の内部に形成された配線103e、103fを介して、グランド層101やDC電源層102に接続されていない独立した配線パターン109に接続されることによって形成されるものであっても良い。図7は、図2に示す電子回路基板1の断面図に対応した、電子回路基板2の断面図である。閉導体ループが形成されてさえいれば、ファラデーの法則によって発生する渦電流107によって、実装基板の配線のインダクタンスである等価直列インダクタンスを減らす事ができる。
In the first embodiment, the wiring pattern 105 formed on the surface of the mounting substrate 111 constitutes a part of the closed conductor loop 110, but the wiring pattern 105 may be formed inside the mounting substrate 111. good. In the first embodiment, both ends of the wiring pattern 105 are connected to the DC power supply layer 102 via the wirings 103c and 103d to form the closed conductor loop 110. The both ends of 105 may be formed by being connected to the ground layer 101 via wiring formed inside the mounting substrate 111. Even in this case, the same effect as the electronic circuit board 1 of the first embodiment can be obtained. Further, as in the electronic circuit board 2 shown in FIG. 7, the closed conductor loop 110 is configured such that both ends of the wiring pattern 105 are connected to the ground layer 101 and the DC power source via the wirings 103 e and 103 f formed inside the mounting substrate 111. It may be formed by being connected to an independent wiring pattern 109 that is not connected to the layer 102. FIG. 7 is a cross-sectional view of the electronic circuit board 2 corresponding to the cross-sectional view of the electronic circuit board 1 shown in FIG. As long as the closed conductor loop is formed, the eddy current 107 generated by Faraday's law can reduce the equivalent series inductance that is the inductance of the wiring of the mounting board.
また、第1の実施形態では、閉導体ループ110を1つ有する電子回路基板1で説明しているが、第2のインダクタ302と発生する磁界を介して結合する閉導体ループは複数あってもよい。例えば、2つの閉導体ループがコンデンサ104が実装された箇所を挟むように形成されていても良い。
<第2の実施の形態> In the first embodiment, theelectronic circuit board 1 having one closed conductor loop 110 is described. However, even if there are a plurality of closed conductor loops coupled to the second inductor 302 through a generated magnetic field. Good. For example, two closed conductor loops may be formed so as to sandwich a place where the capacitor 104 is mounted.
<Second Embodiment>
<第2の実施の形態> In the first embodiment, the
<Second Embodiment>
図8は、本発明の第2の実施の形態に係る電子回路基板3の全体構成例を示す斜視図である。電子回路基板3について、第1の実施の形態の電子デバイス1と異なる点について主に説明し、共通する事項は適宜説明を省略する。第1の実施の形態の電子デバイス1と共通している要素は同じ符号を用いており、共通している要素の説明は省略する。電子回路基板3は、第1の実施の形態と同様に、コンデンサ104が、実装基板111の配線103a、103bを介してグランド層101と電源層102に接続されて実装基板111の表面に実装されている。さらに電子回路基板3は、導体パターン305を有する部品112が実装基板111の表面に実装されている。電子回路基板3では、2つの部品112がコンデンサ104を挟んで実装基板111の表面に実装されている。
FIG. 8 is a perspective view showing an overall configuration example of the electronic circuit board 3 according to the second embodiment of the present invention. The electronic circuit board 3 will be described mainly with respect to differences from the electronic device 1 of the first embodiment, and description of common matters will be omitted as appropriate. Elements common to the electronic device 1 of the first embodiment are denoted by the same reference numerals, and description of the common elements is omitted. As in the first embodiment, the electronic circuit board 3 is mounted on the surface of the mounting board 111 with the capacitor 104 connected to the ground layer 101 and the power supply layer 102 via the wirings 103 a and 103 b of the mounting board 111. ing. Further, in the electronic circuit board 3, a component 112 having a conductor pattern 305 is mounted on the surface of the mounting board 111. In the electronic circuit board 3, two components 112 are mounted on the surface of the mounting board 111 with the capacitor 104 interposed therebetween.
図9は、図8のC-C線に沿った断面図である。部品112は、図8、9に示すような導体パターン305を有している。導体パターン305の周囲には誘電体3043が形成されている。図8、9に示すように、電子回路基板3は、導体パターン305の両端が実装基板111の配線103g、103hを介して、DC電源層102に接続されることによって形成される閉導体ループ310を2つ有している。この閉導体ループ310の等価回路は、図10に示すように、閉導体ループ310のインダクタ成分であるインダクタ313と抵抗成分である抵抗304を直列にループ状に接続することで表される。この閉導体ループ310は、コンデンサ104の寄生インダクタである第1のインダクタ301および、そのコンデンサ104に接続される実装基板111の配線103a、103bの等価直列インダクタである第2のインダクタ302と発生する磁界を介して結合する。
FIG. 9 is a cross-sectional view taken along the line CC of FIG. The component 112 has a conductor pattern 305 as shown in FIGS. A dielectric 3043 is formed around the conductor pattern 305. As shown in FIGS. 8 and 9, the electronic circuit board 3 has a closed conductor loop 310 formed by connecting both ends of the conductor pattern 305 to the DC power supply layer 102 via the wirings 103 g and 103 h of the mounting board 111. Have two. As shown in FIG. 10, the equivalent circuit of the closed conductor loop 310 is represented by connecting an inductor 313 that is an inductor component of the closed conductor loop 310 and a resistor 304 that is a resistance component in series in a loop shape. The closed conductor loop 310 is generated with the first inductor 301 that is a parasitic inductor of the capacitor 104 and the second inductor 302 that is an equivalent series inductor of the wirings 103 a and 103 b of the mounting substrate 111 connected to the capacitor 104. Coupling through a magnetic field.
図8のD-D線に沿った断面図は第1の実施の形態と同様に図3で表すことができる。第1の実施の形態と同様に、DC電源層102にノイズが発生すると、配線103a、103bを介して、コンデンサ104を通過してグランド層101にノイズ電流108が流れ、断面(図3における紙面)に垂直な方向の磁束が発生する。ファラデーの法則によって、ノイズ電流108が流れることによって発生する磁束の増加を妨げる方向の起電力が発生し、ノイズ電流108とは逆向きの渦電流107が閉導体ループ310に流れ、ノイズ電流108により発生する磁束の時間変動を妨げる。渦電流107により発生した磁束は、ノイズ電流108により発生するコンデンサ104の内部及び実装基板111の内部の磁束を打ち消すため、コンデンサ104の寄生インダクタである第1のインダクタ301及び、実装基板111の配線103a、103bのインダクタ成分である第2のインダクタ302の等価直列インダクタンスの両方を低減することができる。
A cross-sectional view taken along the line DD in FIG. 8 can be represented in FIG. 3 as in the first embodiment. As in the first embodiment, when noise is generated in the DC power supply layer 102, the noise current 108 flows through the capacitor 104 through the wirings 103a and 103b and flows into the ground layer 101. ) Generates a magnetic flux in a direction perpendicular to. According to Faraday's law, an electromotive force is generated in a direction that prevents an increase in magnetic flux generated by the flow of the noise current 108, and an eddy current 107 opposite to the noise current 108 flows in the closed conductor loop 310. This prevents time fluctuations of the generated magnetic flux. The magnetic flux generated by the eddy current 107 cancels the magnetic flux generated by the noise current 108 inside the capacitor 104 and inside the mounting substrate 111, so that the first inductor 301, which is a parasitic inductor of the capacitor 104, and the wiring of the mounting substrate 111. Both of the equivalent series inductances of the second inductor 302, which are the inductor components 103a and 103b, can be reduced.
図10は電子回路基板3についての等価回路例を示している。この等価回路例は、DC電源層102とグランド層101の間に直列に接続されるコンデンサ104と、コンデンサ104の寄生インダクタである第1のインダクタ301と、実装基板111の配線103a、103bの等価直列インダクタ成分である第2のインダクタ302とが直列に接続された回路と、導体パターン305、実装基板111の配線103g、103h及びDC電源層102で形成される閉導体ループ310の抵抗成分である抵抗304と閉導体ループ310のインダクタ成分であるインダクタ303とが直列に接続された2つの回路とを含み、閉導体ループ310のインダクタ313が、第1のインダクタ301および第2のインダクタ302の両方と結合しているものである。閉導体ループ310のインダクタ成分であるインダクタ313は、第1のインダクタ301および第2のインダクタ302の両方と結合しているため、コンデンサ104の寄生インダクタ成分である第1のインダクタ301及び、配線103a、103bのインダクタ成分である第2のインダクタ302の両方のインダクタンスを低減させることができる。
FIG. 10 shows an equivalent circuit example for the electronic circuit board 3. This equivalent circuit example is equivalent to a capacitor 104 connected in series between the DC power supply layer 102 and the ground layer 101, a first inductor 301 that is a parasitic inductor of the capacitor 104, and wirings 103 a and 103 b of the mounting substrate 111. This is a resistance component of a closed conductor loop 310 formed by a circuit in which a second inductor 302 that is a series inductor component is connected in series, a conductor pattern 305, wirings 103g and 103h of a mounting substrate 111, and a DC power supply layer 102. A resistor 304 and an inductor 303, which is an inductor component of the closed conductor loop 310, are connected in series, and the inductor 313 of the closed conductor loop 310 includes both the first inductor 301 and the second inductor 302. It is something that is combined with. Since the inductor 313 that is the inductor component of the closed conductor loop 310 is coupled to both the first inductor 301 and the second inductor 302, the first inductor 301 that is the parasitic inductor component of the capacitor 104 and the wiring 103a. , 103b, both inductances of the second inductor 302, which is the inductor component, can be reduced.
また、電子回路基板3は、閉導体ループ310が複数形成されているので、等価直列インダクタンスのより大きな減少効果を得ることができる。第1の実施形態に示したシミュレーションの計算結果からわかるように、閉導体ループ310と第1のインダクタ301または第2のインダクタ302との結合係数が大きい(1に近い)ほど、等価直列インダクタンスを低減する効果が大きくなるが、現実には、結合係数を1にするのは困難である。複数の閉導体ループ310を有することで、各々の閉導体ループ310と第1のインダクタ301または第2のインダクタ301との結合係数が1よりも小さくても、各々の閉導体ループ310に発生する逆起電力による効果が足し合されることにより、等価直列インダクタンスのより大きな減少効果を得ることができる。
In addition, since the electronic circuit board 3 is formed with a plurality of closed conductor loops 310, it is possible to obtain a greater effect of reducing the equivalent series inductance. As can be seen from the simulation results shown in the first embodiment, the larger the coupling coefficient between the closed conductor loop 310 and the first inductor 301 or the second inductor 302 (closer to 1), the more the equivalent series inductance becomes. Although the effect of reducing becomes large, in reality, it is difficult to set the coupling coefficient to 1. By having the plurality of closed conductor loops 310, even if the coupling coefficient between each closed conductor loop 310 and the first inductor 301 or the second inductor 301 is smaller than 1, it is generated in each closed conductor loop 310. By adding the effects of the back electromotive force, it is possible to obtain a greater reduction effect of the equivalent series inductance.
閉導体ループ310は、導体パターン305の両端が実装基板111の内部に形成された配線を介してグランド層101に接続されることによって形成されるものであっても良い。また、閉導体ループ310は、導体パターン305の両端が、実装基板111の内部に形成された配線を介して、グランド層101やDC電源層102に接続されていない独立した配線パターンに接続されることによって形成されるものであっても良い。
The closed conductor loop 310 may be formed by connecting both ends of the conductor pattern 305 to the ground layer 101 via wiring formed inside the mounting substrate 111. In addition, the closed conductor loop 310 is connected at both ends of the conductor pattern 305 to independent wiring patterns that are not connected to the ground layer 101 or the DC power supply layer 102 via wiring formed inside the mounting substrate 111. It may be formed by this.
また、閉導体ループ310が、配線パターン305の両端が、グランド層101やDC電源層102に接続されていない独立した配線パターンに接続されることによって形成され、その独立した配線パターンが、実装基板111の表面または部品112の内部に形成されているものでも良い。この場合は、コンデンサ104の寄生インダクタンス(等価直列インダクタンス)を主に減らすことができる。
Further, the closed conductor loop 310 is formed by connecting both ends of the wiring pattern 305 to independent wiring patterns that are not connected to the ground layer 101 or the DC power supply layer 102, and the independent wiring patterns are formed on the mounting substrate. It may be formed on the surface of 111 or inside the component 112. In this case, the parasitic inductance (equivalent series inductance) of the capacitor 104 can be mainly reduced.
<第3の実施の形態>
図11は、本発明の第3の実施の形態に係る電子回路基板4の構成例を示す斜視図である。電子回路基板4について、第2の実施の形態の電子回路基板3と異なる点について主に説明し、共通する事項は適宜説明を省略する。第2の実施の形態の電子回路基板3と共通している要素は同じ符号を用いており、共通している要素の説明は省略する。電子回路基板4では、第2の実施の形態の電子回路基板3におけるコンデンサ104および、導体パターン305を有する2つの部品112にかえて、導体パターン305を有する部品とコンデンサ104とが一体で形成された部品411が実装基板111の表面に実装されている。図11に示す電子回路基板4では、部品411が導体パターン305を1つ有する例で示している。 <Third Embodiment>
FIG. 11 is a perspective view showing a configuration example of anelectronic circuit board 4 according to the third embodiment of the present invention. The electronic circuit board 4 will be described mainly with respect to differences from the electronic circuit board 3 of the second embodiment, and description of common matters will be omitted as appropriate. Elements common to the electronic circuit board 3 of the second embodiment are denoted by the same reference numerals, and description of the common elements is omitted. In the electronic circuit board 4, the component having the conductor pattern 305 and the capacitor 104 are integrally formed in place of the capacitor 104 and the two components 112 having the conductor pattern 305 in the electronic circuit substrate 3 of the second embodiment. The component 411 is mounted on the surface of the mounting substrate 111. In the electronic circuit board 4 shown in FIG. 11, the component 411 shows an example having one conductor pattern 305.
図11は、本発明の第3の実施の形態に係る電子回路基板4の構成例を示す斜視図である。電子回路基板4について、第2の実施の形態の電子回路基板3と異なる点について主に説明し、共通する事項は適宜説明を省略する。第2の実施の形態の電子回路基板3と共通している要素は同じ符号を用いており、共通している要素の説明は省略する。電子回路基板4では、第2の実施の形態の電子回路基板3におけるコンデンサ104および、導体パターン305を有する2つの部品112にかえて、導体パターン305を有する部品とコンデンサ104とが一体で形成された部品411が実装基板111の表面に実装されている。図11に示す電子回路基板4では、部品411が導体パターン305を1つ有する例で示している。 <Third Embodiment>
FIG. 11 is a perspective view showing a configuration example of an
図12は、部品411の分解斜視図であり、図13は、図11においてE-E線で切断した部品411の断面図であり、図14は、図11においてF-F線で切断した部品411の断面図である。図12~14に示すように、第1の内部電極1041と第2の内部電極1042が誘電体1043を挟んで交互に積層され、導体パターン305は、誘電体1043を介して第1の内部電極1041および第2の内部電極1042から離間して配置されている。第1の内部電極1041と第2の内部電極1042の積層方向から見て、導体パターン305は、その少なくとも一部が第1の内部電極1041および第2の内部電極1042と重なるように配置されている。その他の点は、第2の実施の形態の電子回路基板3と同じである。
12 is an exploded perspective view of the part 411, FIG. 13 is a sectional view of the part 411 cut along the line EE in FIG. 11, and FIG. 14 is a part cut along the line FF in FIG. FIG. As shown in FIGS. 12 to 14, the first internal electrodes 1041 and the second internal electrodes 1042 are alternately stacked with the dielectric 1043 interposed therebetween, and the conductor pattern 305 is connected to the first internal electrodes via the dielectric 1043. 1041 and the second internal electrode 1042 are arranged apart from each other. The conductor pattern 305 is arranged so that at least a part of the conductor pattern 305 overlaps with the first internal electrode 1041 and the second internal electrode 1042 when viewed from the stacking direction of the first internal electrode 1041 and the second internal electrode 1042. Yes. The other points are the same as those of the electronic circuit board 3 of the second embodiment.
電子回路基板4は、コンデンサ104と閉導体ループ310の一部である導体パターン305を有する部品とが一体で形成された部品411が実装基板111に形成されていることによって、コンデンサ104の寄生インダクタ成分である第1のインダクタ301が、閉導体ループ310と磁気的に大きな結合係数で結合することができる。これによって、コンデンサ104の寄生インダクタンス(等価直列インダクタンス)を大きく減らすことができる。
In the electronic circuit board 4, the component 411 in which the capacitor 104 and the component having the conductor pattern 305 that is a part of the closed conductor loop 310 are integrally formed is formed on the mounting substrate 111, so that the parasitic inductor of the capacitor 104 is formed. The first inductor 301 as a component can be coupled to the closed conductor loop 310 with a magnetically large coupling coefficient. Thereby, the parasitic inductance (equivalent series inductance) of the capacitor 104 can be greatly reduced.
以上説明した第1~第3の実施の形態の電子回路基板は、DC-DCコンバーター等の電源モジュール基板として用いられても良いし、スマートフォン、PC、ノートPC等のセットで使われている基板として用いられても良いし、グラフィックボード、マイコンボード、メモリボード、PCIExpressボード等の基板として用いられても良い。
The electronic circuit boards of the first to third embodiments described above may be used as a power supply module board such as a DC-DC converter, or a board used in a set of a smartphone, a PC, a notebook PC, or the like. It may be used as a board such as a graphic board, a microcomputer board, a memory board, and a PCI Express board.
101 グランド層
102 電源層
103a,103b,103c,103d,103e,103f,103g,103h 配線
104 コンデンサ
105 配線パターン
107 渦電流
108 ノイズ電流
109 配線パターン
110 閉導体ループ
111 実装基板
112 部品
201 閉導体ループ
202 磁束
203 磁束
204 渦電流
301 第1のインダクタ
302 第2のインダクタ
303 インダクタ
304 抵抗
305 導体パターン
310 閉導体ループ
313 インダクタ
411 部品
1041 第1の内部電極
1042 第2の内部電極
1043 誘電体
1044 第1の端子電極
1045 第2の端子電極
3043 誘電体 DESCRIPTION OFSYMBOLS 101 Ground layer 102 Power supply layer 103a, 103b, 103c, 103d, 103e, 103f, 103g, 103h Wiring 104 Capacitor 105 Wiring pattern 107 Eddy current 108 Noise current 109 Wiring pattern 110 Closed conductor loop 111 Mounting substrate 112 Component 201 Closed conductor loop 202 Magnetic flux 203 Magnetic flux 204 Eddy current 301 First inductor 302 Second inductor 303 Inductor 304 Resistance 305 Conductor pattern 310 Closed conductor loop 313 Inductor 411 Component 1041 First internal electrode 1042 Second internal electrode 1043 Dielectric 1044 First Terminal electrode 1045 Second terminal electrode 3043 Dielectric
102 電源層
103a,103b,103c,103d,103e,103f,103g,103h 配線
104 コンデンサ
105 配線パターン
107 渦電流
108 ノイズ電流
109 配線パターン
110 閉導体ループ
111 実装基板
112 部品
201 閉導体ループ
202 磁束
203 磁束
204 渦電流
301 第1のインダクタ
302 第2のインダクタ
303 インダクタ
304 抵抗
305 導体パターン
310 閉導体ループ
313 インダクタ
411 部品
1041 第1の内部電極
1042 第2の内部電極
1043 誘電体
1044 第1の端子電極
1045 第2の端子電極
3043 誘電体 DESCRIPTION OF
Claims (6)
- DC電源層とグランド層を有する実装基板とコンデンサとを有し、
前記コンデンサが、前記DC電源層と前記グランド層に配線を介して接続されて前記実装基板に実装され、
前記コンデンサの寄生インダクタ成分である第1のインダクタと、前記配線のインダクタ成分である第2のインダクタとが直列に接続され、
前記第1のインダクタおよび前記第2のインダクタの少なくとも一方と磁気結合する閉導体ループを有することを特徴とする電子回路基板。 A mounting board having a DC power supply layer and a ground layer and a capacitor;
The capacitor is mounted on the mounting substrate by being connected to the DC power supply layer and the ground layer via wiring,
A first inductor that is a parasitic inductor component of the capacitor and a second inductor that is an inductor component of the wiring are connected in series,
An electronic circuit board comprising a closed conductor loop magnetically coupled to at least one of the first inductor and the second inductor. - 前記閉導体ループは、前記実装基板の内部または前記実装基板の表面に形成された配線パターンによって構成されることを特徴とする請求項1に記載の電子回路基板。 2. The electronic circuit board according to claim 1, wherein the closed conductor loop is configured by a wiring pattern formed inside the mounting board or on a surface of the mounting board.
- 前記閉導体ループの一部は、前記DC電源層または前記グランド層のどちらか一方であることを特徴とする請求項1または2に記載の電子回路基板。 3. The electronic circuit board according to claim 1, wherein a part of the closed conductor loop is one of the DC power supply layer and the ground layer.
- 導体パターンを有する部品が前記実装基板に実装され、前記閉導体ループの少なくとも一部は、前記導体パターンであることを特徴とする請求項1ないし3のいずれか一項に記載の電子回路基板。 4. The electronic circuit board according to claim 1, wherein a component having a conductor pattern is mounted on the mounting board, and at least a part of the closed conductor loop is the conductor pattern.
- 前記コンデンサと前記部品とが一体で形成されていることを特徴とする請求項4に記載の電子回路基板。 5. The electronic circuit board according to claim 4, wherein the capacitor and the component are integrally formed.
- 前記閉導体ループを複数有することを特徴とする請求項1ないし5のいずれか一項に記載の電子回路基板。 6. The electronic circuit board according to claim 1, comprising a plurality of the closed conductor loops.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017536450A JPWO2017033950A1 (en) | 2015-08-26 | 2016-08-24 | Electronic circuit board |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015-166362 | 2015-08-26 | ||
| JP2015166362 | 2015-08-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2017033950A1 true WO2017033950A1 (en) | 2017-03-02 |
Family
ID=58100390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2016/074586 WO2017033950A1 (en) | 2015-08-26 | 2016-08-24 | Electronic circuit substrate |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPWO2017033950A1 (en) |
| WO (1) | WO2017033950A1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06349678A (en) * | 1993-06-07 | 1994-12-22 | Tdk Corp | Feed-through type capacitor, electronic device using it, and its mounting method |
| JP2007115759A (en) * | 2005-10-18 | 2007-05-10 | Tdk Corp | Multilayer capacitor, composite capacitor, capacitor module, and method of arranging capacitor |
| JP2009141217A (en) * | 2007-12-07 | 2009-06-25 | Tdk Corp | Feedthrough capacitor mounting structure |
| JP2012186251A (en) * | 2011-03-04 | 2012-09-27 | Murata Mfg Co Ltd | Three-terminal capacitor, and mounting structure of the same |
-
2016
- 2016-08-24 WO PCT/JP2016/074586 patent/WO2017033950A1/en active Application Filing
- 2016-08-24 JP JP2017536450A patent/JPWO2017033950A1/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06349678A (en) * | 1993-06-07 | 1994-12-22 | Tdk Corp | Feed-through type capacitor, electronic device using it, and its mounting method |
| JP2007115759A (en) * | 2005-10-18 | 2007-05-10 | Tdk Corp | Multilayer capacitor, composite capacitor, capacitor module, and method of arranging capacitor |
| JP2009141217A (en) * | 2007-12-07 | 2009-06-25 | Tdk Corp | Feedthrough capacitor mounting structure |
| JP2012186251A (en) * | 2011-03-04 | 2012-09-27 | Murata Mfg Co Ltd | Three-terminal capacitor, and mounting structure of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2017033950A1 (en) | 2018-06-07 |
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