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WO2017039790A1 - Suivi d'interconnexion en tout endroit - Google Patents

Suivi d'interconnexion en tout endroit Download PDF

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Publication number
WO2017039790A1
WO2017039790A1 PCT/US2016/038687 US2016038687W WO2017039790A1 WO 2017039790 A1 WO2017039790 A1 WO 2017039790A1 US 2016038687 W US2016038687 W US 2016038687W WO 2017039790 A1 WO2017039790 A1 WO 2017039790A1
Authority
WO
WIPO (PCT)
Prior art keywords
wires
dielectric
interconnect
circuit
planes
Prior art date
Application number
PCT/US2016/038687
Other languages
English (en)
Inventor
Thomas P. Warwick
Dhananjaya Turpuseema
James V. Russell
Original Assignee
R&D Circuits, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by R&D Circuits, Inc. filed Critical R&D Circuits, Inc.
Priority to KR1020187009252A priority Critical patent/KR20180050348A/ko
Priority to EP16842470.3A priority patent/EP3345248A1/fr
Priority to CN201680050636.4A priority patent/CN108370109A/zh
Priority to JP2018530485A priority patent/JP2018527761A/ja
Publication of WO2017039790A1 publication Critical patent/WO2017039790A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/50—Fixed connections
    • H01R12/51—Fixed connections for rigid printed circuits or like structures
    • H01R12/52—Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/0278—Polymeric fibers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0314—Elastomeric connector or conductor, e.g. rubber with metallic filler
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10189—Non-printed connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10287—Metal wires as connectors or conductors

Definitions

  • the present application relates to a method and a structure for creating interconnects that are not bound by the limitations of conventional interconnect technology.
  • the present invention relates to forming an electrical interconnect mechanism between two or more discrete contact points such as but not limited to circuit pads within two or more parallel circuit planes with circuitry formed in three-dimensional space between the aforementioned two or more circuit planes in order to allow for electrical coupling of two or more electrical devises through said interconnect device.
  • interconnect structures It is normal for these interconnect structures to have an array of contact pads on either side of the outer major surfaces of the structure and occasionally even on the minor sides or surfaces of the structure. These contact pads are meant to be electrically coupled with electronic components on the outer surfaces.
  • contact pads When there are a large number of contact pads or points on each side to be electrically coupled the internal circuitry layers become very dense and require a large number of routing layers.
  • Each of these layers are traditionally formed in layer pairs of two, sandwiched on both sides of a dielectric sheet. These sheets are manufactures concurrently then bonded together with additional dielectric sheet layers forming multilayered structures. Vias are then formed and metalized through or partially through these layer stacks making the required z axis interconnects. Partial or buried vias can be formed and metalized on each of the layer pairs prior to bonding the layers together.
  • dielectric layers and circuitry layers can be built up one on top of another sequentially with blind vias formed only where necessary. This eliminates the need of through vias, which take up routing space in the x-y planes on layers where the vias is not essential. This via anywhere approach greatly improved routing density but suffers from the cost of time and labor to build these layers sequentially.
  • the present invention provides a method and a structure in which an electrical interconnect mechanism is formed having complex connections between two or more discrete contact points such as but not limited to circuit pads within two or more parallel circuit planes with circuitry formed in three-dimensional space between the
  • the present invention provides for electrical coupling of two or more electrical devices through said interconnect device.
  • the present invention provides for a method and structure for forming three- dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes.
  • These wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes.
  • Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points.
  • Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads.
  • These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side.
  • forming a second coating of dielectric on the metalized surfaces of the discrete wires to a specific thickness as to approximate a coaxial wire.
  • These formed and metalized dielectric wire may be electrically coupled through the metallization process to discrete metallic circuits on the two or more planes or the discrete parallel circuits may be formed as an integral part of the formed dielectric wires and then metalized along with the dielectric wires.
  • Other embodiments and variations of the present invention are described below.
  • FIG. 1A shows a perspective view of a first embodiment of the present invention
  • FIG. lb is a sectional view of FIG 1 A with component or electrical devices added;
  • FIGS. 2a-2c are sectional views of three additional embodiments of the present invention of FIG la having metalized outer layers for the dielectric wires and contact points;
  • FIGS. 3a-3d show alternative embodiments for the dielectric wires of FIG 1A;
  • FIG.4 is another embodiment for the present invention.
  • FIGS.5a and b show alternative embodiments for the present invention
  • FIGS. 6a-6c shows three additional embodiments of the present invention
  • FIG. 7a shows another embodiment of the present invention in which the present invention has a rigid body formed between two or more circuit planes and is filled with a dielectric wherein the fill material extends to the top of the circuit elements;
  • FIG. 7b shows another embodiment of the present invention in which the present invention has a rigid body formed between two or more circuit planes and is filled with a dielectric wherein the fill material extends to the bottom of the circuit elements;
  • FIG. 8 is another embodiment of the present invention in which one of the circuit planes of the interconnect of the present invention acts as a plane for the next sequentially build-up plane connected by the formed wires;
  • FIG 9 is another embodiment of the present invention showing anon -coplanar interconnect
  • FIG. 10 is another embodiment for the present invention in which epoxy scaffolding maintains alignment in the X axis and Y axis and z axis locations of each circuit element;
  • FIG 11 a is another embodiment of the present invention in which the interconnect is provided with a scaffolding of dielectric, dielectric posts or a dielectric block with penetrations for passage of the wires there through:
  • FIG l ib is another embodiment of the present invention in which the interconnect is provided with a scaffolding of dielectric, dielectric posts or a dielectric block with penetrations for passage of the wires there through and showing the interconnect structure when filled with an elastomeric material the scaffolding of dielectric, dielectric posts or a dielectric block with penetrations for passage of the wires there through providing a fixed compression stop of the interconnect structure;
  • FIGS. 12a, 12b and 12c show alternative embodiments of the present invention in which:
  • FIG 12a shows the lattice work of non-conductive dielectric scaffolding for the present invention with the circuit element proud
  • FIG 12b shows the lattice work of non-conductive dielectric scaffolding for the present invention with an air dielectric
  • FIG 12c shows the lattice work of non-conductive dielectric scaffolding for the present invention with the circuit element flush
  • FIG 13 shows another embodiment of the present invention for affixing and electrically cou ling two or more terminal points of a electronic component 23 such as but not limited to resistor, capacitors or inductor to the formed wires and the corresponding circuit elements 10 of the corresponding planes 7 wherein each point to be coupled to its corresponding designated power, ground, or signal wires 6 and or circuit elements 10 in the interconnect structure ;
  • a electronic component 23 such as but not limited to resistor, capacitors or inductor to the formed wires and the corresponding circuit elements 10 of the corresponding planes 7 wherein each point to be coupled to its corresponding designated power, ground, or signal wires 6 and or circuit elements 10 in the interconnect structure ;
  • FIG, 14 is another embodiment of the present invention in which the wires 6 are extended beyond the rigid body of the interconnect 1 with spring shapes conducive for flexing such as but not limited to coils, cantilever, S-shapes with end points conducive for contacting various shapes of electrical devices such as but not limited to sharp points, crown tips, cup shapes acting as a compliant interconnect coupling two non- cop lanar electrical devices.
  • spring shapes conducive for flexing such as but not limited to coils, cantilever, S-shapes with end points conducive for contacting various shapes of electrical devices such as but not limited to sharp points, crown tips, cup shapes acting as a compliant interconnect coupling two non- cop lanar electrical devices.
  • FIG la. shows a first embodiment of the present invention in which an electrical interconnect mechanism 5 forms complex connections between two or more discrete contact points 10 (such as but not limited to circuit pads 10a (FIG lb) or dircrete parallel circuits 8 as shown in FIG 3a-3d, also signal pads 8 power pads 8c and ground pads 8a as shown in FIG 4 and FIG 13 are synonamous with discrete circuit elements 8 as well as with circuit pads 10a as shown in FIG lb) within two or more parallel circuit planes 7 with circuitry 6 formed in three-dimensional space between the aforementioned two or more circuit planes 7 in order to provide for electrical coupling of two or more electrical devices 8 FIG lb through the interconnect device 5.
  • discrete contact points 10 such as but not limited to circuit pads 10a (FIG lb) or dircrete parallel circuits 8 as shown in FIG 3a-3d
  • signal pads 8 power pads 8c and ground pads 8a as shown in FIG 4 and FIG 13 are synonamous with discrete circuit elements 8 as well as with circuit pads 10a as shown
  • three-dimensionally routed dielectric wires 6 are formed between discrete points 10 on the two or more parallel circuit planes 7. These wires 6 may be freely routed in three-dimensional space to create the most efficient routing between the two arbitrarily defined points 10 on the two or more parallel circuit planes 7.
  • the outer surfaces of these three dimensional dielectric wires 6 prior to electrically coupling the discrete wires 6 to their respective discrete contact points 10 should be metalized 3 (see FIG. 2).
  • the three dimensional dielectric wires 6 may be either solid metal wires 3b (FIG 6a) with an optional coating of dielectric 6b (FIG 6b) as well as an optional coating of metallization on the dielectric 3c (FIG 6c) or may be a metalized dielectric 3 (FIG 3d) with a second coating of dielectric 6a (FIG 3c) or may also include a second coating of dielectric 6a (FIG 3b) and a second coating of metallization 3a (FIG 3b).
  • FIG 2c Two or more of these wires 6 may be placed into intimate contact with one another electrically coupling each other as well as two or more discrete contact pads 10a (FIG 2c). These electrically coupled contact pads 10a may be on opposite sides (FIG 2a) or on the same side (FIG 2b) of the structure 5(FIG la).
  • a second coating of dielectric 6a may be formed on the metalized surfaces of the discrete wires 6 to a specific thickness so as to approximate a coaxial wire (SEE FIGS.3a -3b).
  • These formed and metalized dielectric wires may be electrically coupled through the metallization process to discrete metallic circuits on the two or more planes 7 as in (FIG 3c) or the discrete parallel circuits 8 (FIG 3d) may be formed as an integral part of the formed dielectric wires 6 and then metalized along with the dielectric wires 6 (see FIG.3d).
  • the second metallization 3a on the coated wire 6 is limited to just short of making contact to the discrete circuit elements on either plane 7 (FIG 3a). This metallization should be recessed from the discrete circuit elements in the range of lum to 50um (See FIG. 3a embodiment of the present invention).
  • the second metalization coating and or the second dielectric layer on the formed dielectric wires is in intimate contact with one another coupling the outer metallization electrically to each other as well as to one or more points on the outer surface circuit planes. This will have the effect of providing ground shielding and or coaxial wires (See FIG 4).
  • a dielectric wall 15 or plane 15 may be formed in the z-axis or vertically in the structure, transposed between the outer surface circuit planes 7, metalized with the end points electrically coupled to the discrete circuits patterns 8,8a (FIG 5a) on one or both planes. Tying these vertical planes to ground 8a will provide for shielding of adjacently routed circuit wires as well as the ability to control the impedance of these wires as shown in FIGS 5 a and 5b.
  • FIGS. 7a and 7b shows two embodiments in which a rigid body 16 is formed between these two or more circuit planes 7 by filling the area between the planes with a dielectric 14, such as but not limited to epoxy.
  • This fill material 14 may extend to the bottom of the circuit elements (see FIG 7b) making the elements superior to the filled dielectric or to the top of the circuit elements (see FIG 7a) making the elements flush to the fill material.
  • FIG. 9 shows another embodiment of the present invention in which instead of filling the aforementioned interconnect mechanism 1 with rigid material such as epoxy 14, the interconnect structure 1 is filled with a compliant material such as an elastomer 19 to maintain alignment of the three dimensional wires 6 and circuitry end points to their desired location as well as allowing for z-axis compliance in order to allow for electrical coupling of two non-coplanar surfaces 7a intended to be coupled by said electrical interconnect mechanism 1.
  • a compliant material such as an elastomer 19
  • FIG. 10 shows another embodiment of the present invention in which instead of filling the entire internal area of the interconnect mechanism with an epoxy, forming a scaffolding 17a with the least amount on material, such as an epoxy, in intimate contact with each of the circuit element on each of the planes transposed between both circuit planes maintaining the z-axis spacing between each plane as well as the x-y location of each of the circuit elements.
  • This scaffolding structure will provide the interconnect 1 with a rigid structure while maintaining air around the formed circuits wires.
  • FIG. 1 la shows another embodiment of the present invention in which around said interconnect a scaffolding of dielectric, dielectric posts or a solid dielectric block 17a.
  • FIG 11 b shows a similar embodiment of the present invention but with said scaffolding of dielectric, dielectric posts or a solid dielectric block with penetrations 21 provided to permit entry of the wires 6.
  • said dielectric structure When used in conjunction with a filled elastomeric material, said dielectric structure provides a fixed compression stop of the interconnect structure 1 to prevent damage to the wires 6 due to over compression (FIG. 1 lb).
  • Designing the free flow of the three dimensionally formed aforementioned wires to have shapes such as but not limited to coils, cantalievers, and S-shapes to provide spring like characteristics to allow for the compliance of the wires while resisting stress cracking in the metal and or dielectric (See FIG la).
  • FIG 12a shows another embodiment of the present invention in which a lattice work of non-conductive dielectric scaffolding 17b transposed between the two circuit planes 7 in intimate contact to the circuit elements within the circuit planes 7 is provided which both provides for alignment of the individual contact points or circuit elements 10 within the circuit planes 7 and either providing rigidity for the entire structure 1 or allowing for some compliance of the entire structure in the z-axis, while optionally also allowing for air dielectric 22 around the aforementioned wires (See FIG 12b).
  • FIG 12a shows the embodiment with the circuit elements superior to the dielectric
  • FIG. 12c shows the embodiment with the circuit elements flush.
  • the scaffolding can be of varying structures known in the art of mechanical engineering to provide the desired properties described above.
  • FIG 13 shows affixing and electrically coupling two or more terminal points 24 of a electrpnic component 23 such as but not limited to a resistor, capacitors or inductor to the formed wires and the corresponding circuit elements of the corresponding planes 7.
  • a electrpnic component 23 such as but not limited to a resistor, capacitors or inductor
  • capacitance, resistance, inductance, or any other electronic function is provided to the points of the electrical devices the interconnect 1 is intended to couple.
  • FIG. 14 shows another embodiment of the present invention in which the wires 6 are extended beyond the rigid body of the interconnect 1 with shape such as but not limited to coils, cantalievers, and S-shapes to provide spring like characteristics to allow for the compliance of the wires while resisting stress cracking in the metal and or dielectric and end points conducive for contacting various shapes of electrical devices such as but not limited to sharp points, crown tips or cup shapes 25 acting as a compliant interconnect coupling two non-cop lanar electrical devices. Providing the ability for pitch translation and pin remapping as well as compliant probing in one integrated structure. Further each of the aforementioned embodiments of the present invention can be built with one or more silicon wafer ICs' creating multi chip modules interconnecting the two or more ICs' where a silicon layer is the base circuit plane..
  • shape such as but not limited to coils, cantalievers, and S-shapes to provide spring like characteristics to allow for the compliance of the wires while resisting stress cracking in the metal
  • each of the aforementioned embodiments of the present mvention can be built with one or more silicon wafer ICs' creating redistribution packaging for the IC.
  • each of the aforementioned embodiments of the present invention can be built on a flexible circuit base.
  • the starting point is with a flat carrier of glass, ceramic or some other smooth, flat material such as but not limited to s smooth metallic block.
  • a sheet of metallic foil preferably Cu to the flat material carrier to keep the Cu flat with a suitable bonding material such as but not limited to adhesive or wax.
  • This foil thickness should be in the range but not limited to 1 Oum to 35um.
  • form dielectric wires attached to the Cu foil grow-up from predetermined locations on the foil to predetermined location in free space in the z axis.
  • the foil may be treated to promote adhesion of the dielectric wires through micro-etching plasma or other surface treatment known in the art. These wires will typically be in the range of lum to 50um in diameter. These wires will be built up to a z-axis height approximately 25um to lOOum above the overall height of the planned interconnect mechanism typically from lOOum to .200" thick.
  • the free formed wires extending from the Cu sheet are metalized with electroplating, electro-less plating, Chemical vapor deposition, sputter coating or any other technique known in the art.
  • the thickness of this metallization will typically be in the range of lum to 25um. This metallization will in effect coat the dielectric wires as well as the exposed surface area of the base foil making the base foil and the coated wires electrically coupled.
  • the metalized dielectric wires can be coated again with a dielectric via a dip operation, silicon Chemical Vapor deposition (SCVD) Silica Pulsed layer Deposition (PLD), Titania Atomic Layer Deposition (ALD) or other techniques known in the art.
  • SCVD silicon Chemical Vapor deposition
  • PLD Silica Pulsed layer Deposition
  • ALD Titania Atomic Layer Deposition
  • the top side, of the base foil metallization can be coated as well, electrically isolating it from further processes.
  • coated wires are then (optionally) metalized via the techniques previously described. This metallization will have the effect of shorting all the surfaces of the formed wires
  • the structure can be filled with a dielectric such as but not limited to epoxy via a molding operation (commonly known in the art) curing the epoxy into a rigid substrate. It would be best to over mold the epoxy beyond the top end points of the formed wires by approximately 25um-l00um. This permits enough material for a planarization process via grinding, sanding, lapping or other techniques know in the art.
  • a dielectric such as but not limited to epoxy via a molding operation (commonly known in the art) curing the epoxy into a rigid substrate. It would be best to over mold the epoxy beyond the top end points of the formed wires by approximately 25um-l00um. This permits enough material for a planarization process via grinding, sanding, lapping or other techniques know in the art.
  • the top tips of the wires may be coated with a temporary coating such as wax or a temporary polymer to prevent metallization from forming at the last 25um to lOOum (typically) on the second dielectric layer.
  • a temporary coating such as wax or a temporary polymer to prevent metallization from forming at the last 25um to lOOum (typically) on the second dielectric layer.
  • Planarization also reveals the tops of the metalized wires providing the opportunity to build up a second circuit layer while electrically coupling said circuit layer to the wires and the base foil. If the tips of the coated wires have been spared from secondary metallization then carefully controlling the planarization of the interconnect substrate in the z-axis will reveal the first metalized layer of the formed wire exposing it to be electrically coupled to the aforementioned second circuit plane formation without coupling the aforementioned optional second metallization of the formed wire to the second circuit plane layer.
  • the aforementioned second circuit plane layer can then be formed via electro-less plating, Chemical vapor deposition, sputter coating, electro-plating, or any other technique known in the art.
  • This conductive metallization is preferabley Cu, Au or any other suitable conductive material and or multiple layers of different materials.
  • the primary bottom metallic layer, and the secondary top layer may now be formed into discreet circuitry through a traditional photo lithographic etching processes known in the art.
  • the contact points or pads formed through this circuitization process can be additionally plated with suitable metallic alloys for the desired application such as but not limited to wear resistance or solder-ability.
  • a metal core may be substituted through the use of negative 3D printing techniques utilizing but not limited to negative working photo sensitive epoxy known in the art whereby a temporary dielectric is formed through the entire active area of the interconnect except where the core wire metallization is to be formed. Then the metallization is formed through electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or other techniques known in the art to form a sold metallic wire structure. Alternatively, varying metals of varying thicknesses can be formed on the inner walls of the voided structures in the epoxy layers providing the desirable electrical and mechanical properties for the end application. Then the temporary epoxy is removed through stripping techniques known in the art and freestanding metallic wires or tubes remain for continued processing described above.
  • dielectric cored, metallic cored or metallic tubes with or without additional layers of dielectric and metallization for shielding or coaxial vias could be formed on to discrete metallic pads or circuits pre- formed on to said smooth glass or smooth ceramic or other suitable material through electro-plating, electro-less plating, Chemical vapor deposition, sputter coating or any other technique known in the art. Having their dimensions defined through a temporary photo-lithographic process common in the art. Further, these pads or circuits could be formed utilizing a laser stenciling process whereby a metallic foil is adhered temporarily to the smooth flat base material with an adhesive or wax and the aforementioned techniques for wire formation may be build on top of the discrete pads or circuitry.
  • end points of the formed wires are formed discrete pads and or circuitry with varying geometric shapes may be formed based on the intended application of the inter-connect.
  • Solder-able pads or pins of varying shapes for making contact to electrical terminals may be formed and metalized as described previously. This formation and metallization of the end points of the formed wires in one step saves additional processing time and in combination with the formation of the discrete pads on the base metal layer provides the opportunity for flush circuit pads on both ends on the interconnect once the aforementioned epoxy molding process in completed.
  • an elastomer or rubber compound potting material may be substituted for a rigid potting compound providing the interconnect terminals with compliance for mating non-coplanar electronic device surfaces.
  • a latticework posts, or a solid block of a suitable hard material such as but not limited to epoxy may be formed within the open spaces of the inter-connect not occupied by the formed wires or the compliant potting material.
  • a suitable hard material such as but not limited to epoxy
  • These structures can be formed through the same 3D printing techniques, in the open spaces of the interconnect body, with a height slightly thinner than the overall thickness of the interconnect ( ⁇ 10um to 200um) providing the interconnect structure with a hard compression stop against the two mating surfaces of the devices intended to be electrically coupled. This will prevent over compression and damage of the interconnect structure.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

La présente invention concerne un procédé et une structure pour former des fils diélectriques à cheminement tridimensionnel entre des points distincts sur les deux plans de circuit parallèles ou plus. Les fils peuvent être acheminés librement dans un espace tridimensionnel de manière à créer le cheminement le plus efficace entre les deux points définis arbitrairement sur les deux plans de circuit parallèles ou plus. La métallisation des surfaces extérieures de ces fils diélectriques tridimensionnels relie électriquement les fils distincts à leurs points de contact distincts respectifs. Deux de ces fils ou plus peuvent se trouver en contact étroit l'un avec à l'autre, se reliant électriquement l'un à l'autre ainsi qu'à deux pastilles de contact distinctes ou plus. Ces pastilles de contact reliées électriquement peuvent se trouver sur des côtés opposés ou du même côté de la structure, et les fils métallisés formés peuvent provenir d'un côté et se terminer de l'autre ou encore provenir et se terminer du même côté.
PCT/US2016/038687 2015-09-01 2016-06-22 Suivi d'interconnexion en tout endroit WO2017039790A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020187009252A KR20180050348A (ko) 2015-09-01 2016-06-22 모든 상호접속의 트레이스
EP16842470.3A EP3345248A1 (fr) 2015-09-01 2016-06-22 Suivi d'interconnexion en tout endroit
CN201680050636.4A CN108370109A (zh) 2015-09-01 2016-06-22 任意位置走线的互连
JP2018530485A JP2018527761A (ja) 2015-09-01 2016-06-22 あらゆる場での相互接続のトレース

Applications Claiming Priority (2)

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US201562212894P 2015-09-01 2015-09-01
US62/212,894 2015-09-01

Publications (1)

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WO2017039790A1 true WO2017039790A1 (fr) 2017-03-09

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EP (1) EP3345248A1 (fr)
JP (1) JP2018527761A (fr)
KR (1) KR20180050348A (fr)
CN (1) CN108370109A (fr)
WO (1) WO2017039790A1 (fr)

Cited By (3)

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US12036738B2 (en) 2016-12-06 2024-07-16 Chromatic 3D Materials, Inc. Manufacture of three dimensional objects from thermosets
EP4564407A1 (fr) * 2023-11-30 2025-06-04 UNIST (Ulsan National Institute of Science and Technology) Substrat pour substrat électrique pour connexion électrique entre des composants électroniques et dispositif électronique
US12384102B2 (en) 2020-05-21 2025-08-12 Chromatic 3D Materials, Inc. Method for three dimensional printing of parts with overhang

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JP2022536002A (ja) * 2019-05-23 2022-08-10 クロマティック・３ディー・マテリアルズ，インコーポレーテッド 三次元物体上への熱硬化性材料の堆積
CN113207217B (zh) * 2020-01-30 2025-06-24 BeCe私人有限公司 电气触点、连接器及其制造方法
CN114725024A (zh) * 2022-03-21 2022-07-08 芯体素(杭州)科技发展有限公司 基于3d打印的引线键合方法和装置、电子设备及存储介质

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US20080233684A1 (en) * 2003-03-04 2008-09-25 Micron Technology, Inc. Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
US20050023032A1 (en) * 2003-07-29 2005-02-03 Kyocera Corporation Laminated wiring board and its mounting structure

Cited By (5)

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Publication number Priority date Publication date Assignee Title
US12036738B2 (en) 2016-12-06 2024-07-16 Chromatic 3D Materials, Inc. Manufacture of three dimensional objects from thermosets
US12384102B2 (en) 2020-05-21 2025-08-12 Chromatic 3D Materials, Inc. Method for three dimensional printing of parts with overhang
EP4564407A1 (fr) * 2023-11-30 2025-06-04 UNIST (Ulsan National Institute of Science and Technology) Substrat pour substrat électrique pour connexion électrique entre des composants électroniques et dispositif électronique
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EP3345248A1 (fr) 2018-07-11
KR20180050348A (ko) 2018-05-14
CN108370109A (zh) 2018-08-03
JP2018527761A (ja) 2018-09-20

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